summaryrefslogtreecommitdiff
path: root/drivers/reset
diff options
context:
space:
mode:
authorDinh Nguyen <dinguyen@kernel.org>2018-04-04 17:18:20 -0500
committerMarek Vasut <marex@denx.de>2018-04-17 11:39:49 +0200
commit2ac718821a88885bd749976ff3ce6f853f2da0c9 (patch)
treeb888413c64350efdb2e0cddca670eaec87a625f9 /drivers/reset
parent81577a3b044645e6c171743c984c021ab3e41615 (diff)
downloadu-boot-2ac718821a88885bd749976ff3ce6f853f2da0c9.tar.gz
reset: socfpga: add reset driver for SoCFPGA platform
Add a DM compatible reset driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'drivers/reset')
-rw-r--r--drivers/reset/Kconfig7
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/reset-socfpga.c105
3 files changed, 113 insertions, 0 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index ccfdac7823..33c39b7fb6 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -91,4 +91,11 @@ config RESET_MESON
help
Support for reset controller on Amlogic Meson SoC.
+config RESET_SOCFPGA
+ bool "Reset controller driver for SoCFPGA"
+ depends on DM_RESET && ARCH_SOCFPGA
+ default y
+ help
+ Support for reset controller on SoCFPGA platform.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index d1d5146825..ad08be4c8c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
+obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
new file mode 100644
index 0000000000..466455d073
--- /dev/null
+++ b/drivers/reset/reset-socfpga.c
@@ -0,0 +1,105 @@
+/*
+ * Socfpga Reset Controller Driver
+ *
+ * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * based on
+ * Allwinner SoCs Reset Controller driver
+ *
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define BANK_INCREMENT 4
+#define NR_BANKS 8
+
+struct socfpga_reset_data {
+ void __iomem *membase;
+};
+
+static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
+ int id = reset_ctl->id;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+
+ setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
+ return 0;
+}
+
+static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
+ int id = reset_ctl->id;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+
+ clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
+ return 0;
+}
+
+static int socfpga_reset_request(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
+ reset_ctl, reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int socfpga_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static const struct reset_ops socfpga_reset_ops = {
+ .request = socfpga_reset_request,
+ .free = socfpga_reset_free,
+ .rst_assert = socfpga_reset_assert,
+ .rst_deassert = socfpga_reset_deassert,
+};
+
+static int socfpga_reset_probe(struct udevice *dev)
+{
+ struct socfpga_reset_data *data = dev_get_priv(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ u32 modrst_offset;
+
+ data->membase = devfdt_get_addr_ptr(dev);
+
+ modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10);
+ data->membase += modrst_offset;
+
+ return 0;
+}
+
+static const struct udevice_id socfpga_reset_match[] = {
+ { .compatible = "altr,rst-mgr" },
+ { /* sentinel */ },
+};
+
+U_BOOT_DRIVER(socfpga_reset) = {
+ .name = "socfpga-reset",
+ .id = UCLASS_RESET,
+ .of_match = socfpga_reset_match,
+ .probe = socfpga_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
+ .ops = &socfpga_reset_ops,
+};