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| author | Wolfgang Denk <wd@denx.de> | 2012-07-18 10:47:03 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2012-07-18 10:47:03 +0200 |
| commit | 66714b1a6df0a5a9f1656a6d4e6eea3c7ecdf7ae (patch) | |
| tree | 946a13465467eb58f68cf8cf5e121017d380fe2a /drivers/video/ipu_regs.h | |
| parent | 3a9469b5cbd467b3a7b176b4feb2073a04f294b6 (diff) | |
| parent | cf65d478ab4e0bb0247c374e6b0b40ef77eddbe8 (diff) | |
| download | u-boot-66714b1a6df0a5a9f1656a6d4e6eea3c7ecdf7ae.tar.gz | |
Merge branch 'next' of git://git.denx.de/u-boot-video
* 'next' of git://git.denx.de/u-boot-video:
ipu_common: Add ldb_clk for use in parenting the pixel clock
ipu_common: Do not hardcode the ipu_clk frequency
ipu_common: Rename MXC_CCM_BASE
ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
ipu_common: Only apply the erratum to MX51
video: Rename CONFIG_VIDEO_MX5
mx6: Allow mx6 to access the IPUv3 registers
common lcd: minor coding style changes
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'drivers/video/ipu_regs.h')
| -rw-r--r-- | drivers/video/ipu_regs.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index 93b195f2ce..a43aa03735 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -47,14 +47,24 @@ #define IPU_SMFC_REG_BASE 0x00050000 #define IPU_DC_REG_BASE 0x00058000 #define IPU_DMFC_REG_BASE 0x00060000 +#define IPU_VDI_REG_BASE 0x00680000 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #define IPU_CPMEM_REG_BASE 0x01000000 #define IPU_LUT_REG_BASE 0x01020000 #define IPU_SRM_REG_BASE 0x01040000 #define IPU_TPM_REG_BASE 0x01060000 #define IPU_DC_TMPL_REG_BASE 0x01080000 #define IPU_ISP_TBPR_REG_BASE 0x010C0000 -#define IPU_VDI_REG_BASE 0x00680000 +#elif defined(CONFIG_MX6Q) +#define IPU_CPMEM_REG_BASE 0x00100000 +#define IPU_LUT_REG_BASE 0x00120000 +#define IPU_SRM_REG_BASE 0x00140000 +#define IPU_TPM_REG_BASE 0x00160000 +#define IPU_DC_TMPL_REG_BASE 0x00180000 +#define IPU_ISP_TBPR_REG_BASE 0x001C0000 +#endif +#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET) extern u32 *ipu_dc_tmpl_reg; |