diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2020-04-21 09:28:29 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2020-04-27 20:29:33 +0200 |
| commit | caf709229419b3ae6f6748d5c575a44a1bf30c14 (patch) | |
| tree | 9495962d5cdb0f925fd9fd805a3b4bd4eefd73f4 /drivers | |
| parent | 2a9d68e41f6d67432c19dc1d140f908df0401f2c (diff) | |
| download | u-boot-caf709229419b3ae6f6748d5c575a44a1bf30c14.tar.gz | |
sysreset: add reset controller based reboot driver
Some chips provide their sysreset function in reset controller, which is
normally a bit written to 1 to perform the sysreset.
This patch adds a new sysreset driver to take advantage of it.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/sysreset/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/sysreset/Makefile | 1 | ||||
| -rw-r--r-- | drivers/sysreset/sysreset_resetctl.c | 48 |
3 files changed, 55 insertions, 0 deletions
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index f09e138bb8..4be7433404 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -101,6 +101,12 @@ config SYSRESET_WATCHDOG help Reboot support for generic watchdog reset. +config SYSRESET_RESETCTL + bool "Enable support for reset controller reboot driver" + select DM_RESET + help + Reboot support using generic reset controller. + config SYSRESET_X86 bool "Enable support for x86 processor reboot driver" depends on X86 diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 51af68fad3..3ed4bab9e3 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -16,5 +16,6 @@ obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o +obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o diff --git a/drivers/sysreset/sysreset_resetctl.c b/drivers/sysreset/sysreset_resetctl.c new file mode 100644 index 0000000000..b8203ba605 --- /dev/null +++ b/drivers/sysreset/sysreset_resetctl.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <reset.h> + +struct resetctl_reboot_priv { + struct reset_ctl_bulk resets; +}; + +static int resetctl_reboot_request(struct udevice *dev, enum sysreset_t type) +{ + struct resetctl_reboot_priv *priv = dev_get_priv(dev); + + return reset_assert_bulk(&priv->resets); +} + +static struct sysreset_ops resetctl_reboot_ops = { + .request = resetctl_reboot_request, +}; + +int resetctl_reboot_probe(struct udevice *dev) +{ + struct resetctl_reboot_priv *priv = dev_get_priv(dev); + + return reset_get_bulk(dev, &priv->resets); +} + +static const struct udevice_id resetctl_reboot_ids[] = { + { .compatible = "resetctl-reboot" }, + { } +}; + +U_BOOT_DRIVER(resetctl_reboot) = { + .id = UCLASS_SYSRESET, + .name = "resetctl_reboot", + .of_match = resetctl_reboot_ids, + .ops = &resetctl_reboot_ops, + .priv_auto_alloc_size = sizeof(struct resetctl_reboot_priv), + .probe = resetctl_reboot_probe, +}; |