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| author | Tom Rini <trini@konsulko.com> | 2017-04-16 22:08:13 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-04-16 22:08:13 -0400 |
| commit | af8ef2ed21960b894945e37a3217ad67373f3711 (patch) | |
| tree | 203ac289e2df20f5d8892570031f29b3a34888ec /drivers | |
| parent | 51f866e8da758a27af596af73466bd5f0a450c4d (diff) | |
| parent | 7ee16de58bddaa9619c264313008d7e19300b42a (diff) | |
| download | u-boot-af8ef2ed21960b894945e37a3217ad67373f3711.tar.gz | |
Merge git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/i2c/rk_i2c.c | 1 | ||||
| -rw-r--r-- | drivers/sysreset/sysreset_rk3188.c | 15 |
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index af925cecdb..76f41f7e85 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -383,6 +383,7 @@ static const struct udevice_id rockchip_i2c_ids[] = { { .compatible = "rockchip,rk3066-i2c" }, { .compatible = "rockchip,rk3188-i2c" }, { .compatible = "rockchip,rk3288-i2c" }, + { .compatible = "rockchip,rk3399-i2c" }, { } }; diff --git a/drivers/sysreset/sysreset_rk3188.c b/drivers/sysreset/sysreset_rk3188.c index 36ae47600a..053a6344f5 100644 --- a/drivers/sysreset/sysreset_rk3188.c +++ b/drivers/sysreset/sysreset_rk3188.c @@ -7,21 +7,36 @@ #include <common.h> #include <dm.h> #include <errno.h> +#include <syscon.h> #include <sysreset.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/cru_rk3188.h> +#include <asm/arch/grf_rk3188.h> #include <asm/arch/hardware.h> #include <linux/err.h> int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type) { struct rk3188_cru *cru = rockchip_get_cru(); + struct rk3188_grf *grf; if (IS_ERR(cru)) return PTR_ERR(cru); switch (type) { case SYSRESET_WARM: + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(grf)) + return -EPROTONOSUPPORT; + + /* + * warm-reset keeps the remap value, + * so make sure it's disabled. + */ + rk_clrsetreg(&grf->soc_con0, + NOC_REMAP_MASK << NOC_REMAP_SHIFT, + 0 << NOC_REMAP_SHIFT); + rk_clrreg(&cru->cru_mode_con, 0xffff); writel(0xeca8, &cru->cru_glb_srst_snd_value); break; |