diff options
| author | Fabio Estevam <fabio.estevam@nxp.com> | 2017-09-06 13:49:31 -0300 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2017-09-11 12:46:51 +0200 |
| commit | c7430d7d5efc45666476dab0da97466cb8ccff8e (patch) | |
| tree | 98e093b1fd5208be2690cd483684b9f20e0c8840 /drivers | |
| parent | 584f316f115df52fd09a6cf699b29dcf824b4da5 (diff) | |
| download | u-boot-c7430d7d5efc45666476dab0da97466cb8ccff8e.tar.gz | |
ipu_common: Let the MX6 IPU clock be calculated in run-time
MX6Q/QP IPU operates at 264MHz and MX6DL IPU at 198MHz.
When running a SPL target, which supports multiple MX6 variants we cannot
properly setup the IPU clock frequency via CONFIG_IPUV3_CLK option as
such decision is done in build-time currently.
Remove the CONFIG_IPUV3_CLK option and let the IPU clock frequency be
configured in run-time on mx6.
Reported-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
[agust: fixed #endif in cgtqmx6eval.h]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/ipu_common.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index f259fb9633..96229da502 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -19,6 +19,7 @@ #include <linux/errno.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <div64.h> #include "ipu.h" #include "ipu_regs.h" @@ -81,6 +82,11 @@ struct ipu_ch_param { #define IPU_SW_RST_TOUT_USEC (10000) +#define IPUV3_CLK_MX51 133000000 +#define IPUV3_CLK_MX53 200000000 +#define IPUV3_CLK_MX6Q 264000000 +#define IPUV3_CLK_MX6DL 198000000 + void clk_enable(struct clk *clk) { if (clk) { @@ -196,7 +202,6 @@ static void clk_ipu_disable(struct clk *clk) static struct clk ipu_clk = { .name = "ipu_clk", - .rate = CONFIG_IPUV3_CLK, #if defined(CONFIG_MX51) || defined(CONFIG_MX53) .enable_reg = (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5)), @@ -476,6 +481,13 @@ int ipu_probe(void) g_pixel_clk[1] = &pixel_clk[1]; g_ipu_clk = &ipu_clk; +#if defined(CONFIG_MX51) + g_ipu_clk->rate = IPUV3_CLK_MX51; +#elif defined(CONFIG_MX53) + g_ipu_clk->rate = IPUV3_CLK_MX53; +#else + g_ipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q; +#endif debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk)); g_ldb_clk = &ldb_clk; debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk)); |