Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.1

Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling

ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board

Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support

8 files changed, 123 insertions, 65 deletions

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 5e4df19386..690d35c890 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1026,7 +1026,7 @@ void scsi_low_level_init(int busdevfunc)
 
 #ifndef CONFIG_SCSI_AHCI_PLAT
 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
-int achi_init_one_dm(struct udevice *dev)
+int ahci_init_one_dm(struct udevice *dev)
 {
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 
@@ -1035,7 +1035,7 @@ int achi_init_one_dm(struct udevice *dev)
 #endif
 #endif
 
-int achi_start_ports_dm(struct udevice *dev)
+int ahci_start_ports_dm(struct udevice *dev)
 {
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 
diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c
index b16304baed..029b7784f6 100644
--- a/drivers/ata/dwc_ahci.c
+++ b/drivers/ata/dwc_ahci.c
@@ -85,7 +85,7 @@ static int dwc_ahci_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
-	return achi_start_ports_dm(dev);
+	return ahci_start_ports_dm(dev);
 }
 
 static const struct udevice_id dwc_ahci_ids[] = {
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index 3ef7b49215..bae26898ba 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -118,11 +118,11 @@ static int sata_ceva_probe(struct udevice *dev)
 
 	ceva_init_sata(plat->base);
 
-	ret = achi_init_one_dm(dev);
+	ret = ahci_init_one_dm(dev);
 	if (ret)
 		return ret;
 
-	return achi_start_ports_dm(dev);
+	return ahci_start_ports_dm(dev);
 }
 
 static const struct udevice_id sata_ceva_ids[] = {
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index cbdbd2f973..47ec43500c 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -154,6 +154,13 @@ config NAND_ZYNQ
 	  This enables Nand driver support for Nand flash controller
 	  found on Zynq SoC.
 
+config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
+	bool "Enable use of 1st stage bootloader timing for NAND"
+	depends on NAND_ZYNQ
+	help
+	  This flag prevent U-boot reconfigure NAND flash controller and reuse
+	  the NAND timing from 1st stage bootloader.
+
 comment "Generic NAND options"
 
 # Enhance depends when converting drivers to Kconfig which use this config
diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c
index 948f05984c..076b878244 100644
--- a/drivers/mtd/nand/zynq_nand.c
+++ b/drivers/mtd/nand/zynq_nand.c
@@ -35,6 +35,8 @@
 				(0x1 << 4)   |	/* Clear interrupt */ \
 				(0x1 << 6))	/* Disable ECC interrupt */
 
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
+
 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
 #define ZYNQ_NAND_SET_CYCLES	((0x2 << 20) |	/* t_rr from nand_cycles */ \
 				(0x2 << 17)  |	/* t_ar from nand_cycles */ \
@@ -43,6 +45,7 @@
 				(0x2 << 8)   |	/* t_rea from nand_cycles */ \
 				(0x5 << 4)   |	/* t_wc from nand_cycles */ \
 				(0x5 << 0))	/* t_rc from nand_cycles */
+#endif
 
 
 #define ZYNQ_NAND_DIRECT_CMD	((0x4 << 23) |	/* Chip 0 from interface 1 */ \
@@ -81,6 +84,13 @@
 #define ZYNQ_NAND_ECC_BUSY	(1 << 6)	/* ECC block is busy */
 #define ZYNQ_NAND_ECC_MASK	0x00FFFFFF	/* ECC value mask */
 
+#ifndef NAND_CMD_LOCK_TIGHT
+#define NAND_CMD_LOCK_TIGHT 0x2c
+#endif
+
+#ifndef NAND_CMD_LOCK_STATUS
+#define NAND_CMD_LOCK_STATUS 0x7a
+#endif
 
 /* SMC register set */
 struct zynq_nand_smc_regs {
@@ -141,6 +151,11 @@ static const struct zynq_nand_command_format zynq_nand_commands[] = {
 	{NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
 	{NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
 	{NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
+	{NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
+	{NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
+	{NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
+	{NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
+	{NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
 	{NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
 	/* Add all the flash commands supported by the flash device */
 };
@@ -245,8 +260,10 @@ static int zynq_nand_init_nand_flash(int option)
 
 	/* disable interrupts */
 	writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
+#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
 	/* Initialize the NAND interface by setting cycles and operation mode */
 	writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
+#endif
 	if (option & NAND_BUSWIDTH_16)
 		writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
 	else
@@ -989,7 +1006,7 @@ static int zynq_nand_device_ready(struct mtd_info *mtd)
 	return 0;
 }
 
-static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 {
 	struct zynq_nand_info *xnand;
 	struct mtd_info *mtd;
@@ -1175,12 +1192,14 @@ fail:
 	return err;
 }
 
+#ifdef CONFIG_SYS_NAND_SELF_INIT
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
-void board_nand_init(void)
+void __weak board_nand_init(void)
 {
 	struct nand_chip *nand = &nand_chip[0];
 
 	if (zynq_nand_init(nand, 0))
 		puts("ZYNQ NAND init failed\n");
 }
+#endif
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 25c66c6098..9a2a578ff9 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -14,6 +14,7 @@
 #include <asm/io.h>
 #include <phy.h>
 #include <miiphy.h>
+#include <wait_bit.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,6 +51,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define XAE_MDIO_DIV_DFT	29	/* Default MDIO clock divisor */
 
+#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK	0x007FFFFF /* Actual len */
+
 /* DMA macros */
 /* Bitmasks of XAXIDMA_CR_OFFSET register */
 #define XAXIDMA_CR_RUNSTOP_MASK	0x00000001 /* Start/stop DMA channel */
@@ -89,6 +92,7 @@ struct axidma_priv {
 	phy_interface_t interface;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
+	u8 eth_hasnobuf;
 };
 
 /* BD descriptors */
@@ -152,7 +156,7 @@ static inline int mdio_wait(struct axi_regs *regs)
 	u32 timeout = 200;
 
 	/* Wait till MDIO interface is ready to accept a new transaction. */
-	while (timeout && (!(in_be32(&regs->mdio_mcr)
+	while (timeout && (!(readl(&regs->mdio_mcr)
 						& XAE_MDIO_MCR_READY_MASK))) {
 		timeout--;
 		udelay(1);
@@ -180,13 +184,13 @@ static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 			XAE_MDIO_MCR_INITIATE_MASK |
 			XAE_MDIO_MCR_OP_READ_MASK;
 
-	out_be32(&regs->mdio_mcr, mdioctrlreg);
+	writel(mdioctrlreg, &regs->mdio_mcr);
 
 	if (mdio_wait(regs))
 		return 1;
 
 	/* Read data */
-	*val = in_be32(&regs->mdio_mrd);
+	*val = readl(&regs->mdio_mrd);
 	return 0;
 }
 
@@ -207,9 +211,9 @@ static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 			XAE_MDIO_MCR_OP_WRITE_MASK;
 
 	/* Write data */
-	out_be32(&regs->mdio_mwd, data);
+	writel(data, &regs->mdio_mwd);
 
-	out_be32(&regs->mdio_mcr, mdioctrlreg);
+	writel(mdioctrlreg, &regs->mdio_mcr);
 
 	if (mdio_wait(regs))
 		return 1;
@@ -233,7 +237,7 @@ static int axiemac_phy_init(struct udevice *dev)
 			SUPPORTED_1000baseT_Full;
 
 	/* Set default MDIO divisor */
-	out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
+	writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
 
 	if (priv->phyaddr == -1) {
 		/* Detect the PHY address */
@@ -312,12 +316,12 @@ static int setup_phy(struct udevice *dev)
 	}
 
 	/* Setup the emac for the phy speed */
-	emmc_reg = in_be32(&regs->emmc);
+	emmc_reg = readl(&regs->emmc);
 	emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
 	emmc_reg |= speed;
 
 	/* Write new speed setting out to Axi Ethernet */
-	out_be32(&regs->emmc, emmc_reg);
+	writel(emmc_reg, &regs->emmc);
 
 	/*
 	* Setting the operating speed of the MAC needs a delay. There
@@ -336,13 +340,13 @@ static void axiemac_stop(struct udevice *dev)
 	u32 temp;
 
 	/* Stop the hardware */
-	temp = in_be32(&priv->dmatx->control);
+	temp = readl(&priv->dmatx->control);
 	temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
-	out_be32(&priv->dmatx->control, temp);
+	writel(temp, &priv->dmatx->control);
 
-	temp = in_be32(&priv->dmarx->control);
+	temp = readl(&priv->dmarx->control);
 	temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
-	out_be32(&priv->dmarx->control, temp);
+	writel(temp, &priv->dmarx->control);
 
 	debug("axiemac: Halted\n");
 }
@@ -350,7 +354,7 @@ static void axiemac_stop(struct udevice *dev)
 static int axi_ethernet_init(struct axidma_priv *priv)
 {
 	struct axi_regs *regs = priv->iobase;
-	u32 timeout = 200;
+	int err;
 
 	/*
 	 * Check the status of the MgtRdy bit in the interrupt status
@@ -358,33 +362,39 @@ static int axi_ethernet_init(struct axidma_priv *priv)
 	 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
 	 * will be valid until this bit is valid.
 	 * The bit is always a 1 for all other PHY interfaces.
+	 * Interrupt status and enable registers are not available in non
+	 * processor mode and hence bypass in this mode
 	 */
-	while (timeout && (!(in_be32(&regs->is) & XAE_INT_MGTRDY_MASK))) {
-		timeout--;
-		udelay(1);
-	}
-	if (!timeout) {
-		printf("%s: Timeout\n", __func__);
-		return 1;
-	}
+	if (!priv->eth_hasnobuf) {
+		err = wait_for_bit(__func__, (const u32 *)&regs->is,
+				   XAE_INT_MGTRDY_MASK, true, 200, false);
+		if (err) {
+			printf("%s: Timeout\n", __func__);
+			return 1;
+		}
 
-	/* Stop the device and reset HW */
-	/* Disable interrupts */
-	out_be32(&regs->ie, 0);
+		/*
+		 * Stop the device and reset HW
+		 * Disable interrupts
+		 */
+		writel(0, &regs->ie);
+	}
 
 	/* Disable the receiver */
-	out_be32(&regs->rcw1, in_be32(&regs->rcw1) & ~XAE_RCW1_RX_MASK);
+	writel(readl(&regs->rcw1) & ~XAE_RCW1_RX_MASK, &regs->rcw1);
 
 	/*
 	 * Stopping the receiver in mid-packet causes a dropped packet
 	 * indication from HW. Clear it.
 	 */
-	/* Set the interrupt status register to clear the interrupt */
-	out_be32(&regs->is, XAE_INT_RXRJECT_MASK);
+	if (!priv->eth_hasnobuf) {
+		/* Set the interrupt status register to clear the interrupt */
+		writel(XAE_INT_RXRJECT_MASK, &regs->is);
+	}
 
 	/* Setup HW */
 	/* Set default MDIO divisor */
-	out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
+	writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
 
 	debug("axiemac: InitHw done\n");
 	return 0;
@@ -399,11 +409,11 @@ static int axiemac_write_hwaddr(struct udevice *dev)
 	/* Set the MAC address */
 	int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
 		(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
-	out_be32(&regs->uaw0, val);
+	writel(val, &regs->uaw0);
 
 	val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
-	val |= in_be32(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
-	out_be32(&regs->uaw1, val);
+	val |= readl(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
+	writel(val, &regs->uaw1);
 	return 0;
 }
 
@@ -413,15 +423,15 @@ static void axi_dma_init(struct axidma_priv *priv)
 	u32 timeout = 500;
 
 	/* Reset the engine so the hardware starts from a known state */
-	out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
-	out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
+	writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
+	writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
 
 	/* At the initialization time, hardware should finish reset quickly */
 	while (timeout--) {
 		/* Check transmit/receive channel */
 		/* Reset is done when the reset bit is low */
-		if (!((in_be32(&priv->dmatx->control) |
-				in_be32(&priv->dmarx->control))
+		if (!((readl(&priv->dmatx->control) |
+				readl(&priv->dmarx->control))
 						& XAXIDMA_CR_RESET_MASK)) {
 			break;
 		}
@@ -450,12 +460,12 @@ static int axiemac_start(struct udevice *dev)
 		return -1;
 
 	/* Disable all RX interrupts before RxBD space setup */
-	temp = in_be32(&priv->dmarx->control);
+	temp = readl(&priv->dmarx->control);
 	temp &= ~XAXIDMA_IRQ_ALL_MASK;
-	out_be32(&priv->dmarx->control, temp);
+	writel(temp, &priv->dmarx->control);
 
 	/* Start DMA RX channel. Now it's ready to receive data.*/
-	out_be32(&priv->dmarx->current, (u32)&rx_bd);
+	writel((u32)&rx_bd, &priv->dmarx->current);
 
 	/* Setup the BD. */
 	memset(&rx_bd, 0, sizeof(rx_bd));
@@ -470,17 +480,17 @@ static int axiemac_start(struct udevice *dev)
 	flush_cache((u32)&rxframe, sizeof(rxframe));
 
 	/* Start the hardware */
-	temp = in_be32(&priv->dmarx->control);
+	temp = readl(&priv->dmarx->control);
 	temp |= XAXIDMA_CR_RUNSTOP_MASK;
-	out_be32(&priv->dmarx->control, temp);
+	writel(temp, &priv->dmarx->control);
 
 	/* Rx BD is ready - start */
-	out_be32(&priv->dmarx->tail, (u32)&rx_bd);
+	writel((u32)&rx_bd, &priv->dmarx->tail);
 
 	/* Enable TX */
-	out_be32(&regs->tc, XAE_TC_TX_MASK);
+	writel(XAE_TC_TX_MASK, &regs->tc);
 	/* Enable RX */
-	out_be32(&regs->rcw1, XAE_RCW1_RX_MASK);
+	writel(XAE_RCW1_RX_MASK, &regs->rcw1);
 
 	/* PHY setup */
 	if (!setup_phy(dev)) {
@@ -515,22 +525,22 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len)
 	/* Flush the last BD so DMA core could see the updates */
 	flush_cache((u32)&tx_bd, sizeof(tx_bd));
 
-	if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
+	if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
 		u32 temp;
-		out_be32(&priv->dmatx->current, (u32)&tx_bd);
+		writel((u32)&tx_bd, &priv->dmatx->current);
 		/* Start the hardware */
-		temp = in_be32(&priv->dmatx->control);
+		temp = readl(&priv->dmatx->control);
 		temp |= XAXIDMA_CR_RUNSTOP_MASK;
-		out_be32(&priv->dmatx->control, temp);
+		writel(temp, &priv->dmatx->control);
 	}
 
 	/* Start transfer */
-	out_be32(&priv->dmatx->tail, (u32)&tx_bd);
+	writel((u32)&tx_bd, &priv->dmatx->tail);
 
 	/* Wait for transmission to complete */
 	debug("axiemac: Waiting for tx to be done\n");
 	timeout = 200;
-	while (timeout && (!(in_be32(&priv->dmatx->status) &
+	while (timeout && (!(readl(&priv->dmatx->status) &
 			(XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
 		timeout--;
 		udelay(1);
@@ -549,10 +559,10 @@ static int isrxready(struct axidma_priv *priv)
 	u32 status;
 
 	/* Read pending interrupts */
-	status = in_be32(&priv->dmarx->status);
+	status = readl(&priv->dmarx->status);
 
 	/* Acknowledge pending interrupts */
-	out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
+	writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
 
 	/*
 	 * If Reception done interrupt is asserted, call RX call back function
@@ -577,11 +587,14 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
 	debug("axiemac: RX data ready\n");
 
 	/* Disable IRQ for a moment till packet is handled */
-	temp = in_be32(&priv->dmarx->control);
+	temp = readl(&priv->dmarx->control);
 	temp &= ~XAXIDMA_IRQ_ALL_MASK;
-	out_be32(&priv->dmarx->control, temp);
+	writel(temp, &priv->dmarx->control);
+	if (!priv->eth_hasnobuf)
+		length = rx_bd.app4 & 0xFFFF; /* max length mask */
+	else
+		length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
 
-	length = rx_bd.app4 & 0xFFFF; /* max length mask */
 #ifdef DEBUG
 	print_buffer(&rxframe, &rxframe[0], 1, length, 16);
 #endif
@@ -613,7 +626,7 @@ static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
 	flush_cache((u32)&rxframe, sizeof(rxframe));
 
 	/* Rx BD is ready - start again */
-	out_be32(&priv->dmarx->tail, (u32)&rx_bd);
+	writel((u32)&rx_bd, &priv->dmarx->tail);
 
 	debug("axiemac: RX completed, framelength = %d\n", length);
 
@@ -695,8 +708,8 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev)
 		printf("%s: axistream is not found\n", __func__);
 		return -EINVAL;
 	}
-	priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob,
-							  offset, "reg", 0);
+	priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
+							  offset, "reg");
 	if (!priv->dmatx) {
 		printf("%s: axi_dma register space not found\n", __func__);
 		return -EINVAL;
@@ -719,6 +732,9 @@ static int axi_emac_ofdata_to_platdata(struct udevice *dev)
 	}
 	priv->interface = pdata->phy_interface;
 
+	priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
+					     "xlnx,eth-hasnobuf");
+
 	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
 	       priv->phyaddr, phy_string_for_interface(priv->interface));
 
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index f6bbcdc48e..1dfd631e1a 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -182,6 +182,7 @@ struct zynq_gem_priv {
 	int phy_of_handle;
 	struct mii_dev *bus;
 	struct clk clk;
+	bool int_pcs;
 };
 
 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -425,7 +426,12 @@ static int zynq_gem_init(struct udevice *dev)
 
 	nwconfig = ZYNQ_GEM_NWCFG_INIT;
 
-	if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
+	/*
+	 * Set SGMII enable PCS selection only if internal PCS/PMA
+	 * core is used and interface is SGMII.
+	 */
+	if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
+	    priv->int_pcs) {
 		nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
 			    ZYNQ_GEM_NWCFG_PCS_SEL;
 #ifdef CONFIG_ARM64
@@ -697,6 +703,9 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 	}
 	priv->interface = pdata->phy_interface;
 
+	priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
+					"is-internal-pcspma");
+
 	printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
 	       priv->phyaddr, phy_string_for_interface(priv->interface));
 
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 7c54a49bb3..122b8e786a 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -537,6 +537,13 @@ config STM32X7_SERIAL
 	  enable its onboard serial ports, say Y to this option.
 	  If unsure, say N.
 
+config ZYNQ_SERIAL
+	bool "Cadence (Xilinx Zynq) UART support"
+	depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+	help
+	  This driver supports the Cadence UART. It is found e.g. in Xilinx
+	  Zynq/ZynqMP.
+
 config MPC8XX_CONS
 	bool "Console driver for MPC8XX"
 	depends on 8xx