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authorHeiko Schocher <hs@denx.de>2009-09-23 07:56:04 +0200
committerWolfgang Denk <wd@denx.de>2009-09-25 01:19:17 +0200
commit7f625fc6d3ba8f890e843ac01717804c2462ed53 (patch)
treeb1a91054c09231da54bc1b910248215358587fa4 /include/configs/manroland
parent9d142ea8f787882ab732fa531a34db091bfa363d (diff)
downloadu-boot-7f625fc6d3ba8f890e843ac01717804c2462ed53.tar.gz
mpc5200, mucmc52, uc101: config cleanup
- As these boards are similiar, collect common config options in manroland/common.h and manroland/mpc52xx-common.h for mpc5200 specific common options for this manufacturer. - add OF support - update default environment Signed-off-by: Heiko Schocher <hs@denx.de> Minor edit of commit message. Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include/configs/manroland')
-rw-r--r--include/configs/manroland/common.h141
-rw-r--r--include/configs/manroland/mpc5200-common.h229
2 files changed, 370 insertions, 0 deletions
diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h
new file mode 100644
index 0000000000..c0122b7a69
--- /dev/null
+++ b/include/configs/manroland/common.h
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MANROLAND_COMMON_H
+#define __MANROLAND_COMMON_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SNTP
+
+#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addwdt=setenv bootargs ${bootargs} wdt=off\0" \
+ "logval=4\0" \
+ "addlog=setenv bootargs ${bootargs} loglevel=${logval}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "kernel_addr=ff810000\0" \
+ "fdt_addr="xstr(CONFIG_SYS_FLASH_BASE)"\0" \
+ "flash_nfs=run nfsargs addip addcon addwdt addlog;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "rootpath=/opt/eldk/ppc_82xx\0" \
+ "kernel_addr_r=300000\0" \
+ "fdt_addr_r=200000\0" \
+ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
+ xstr(CONFIG_HOSTNAME) ".dtb\0" \
+ "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \
+ "load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttyPSC0,${baudrate}\0"\
+ "net_nfs=run load_fdt load_kernel; " \
+ "run nfsargs addip addcon addwdt addlog;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \
+ "u-boot_addr_r=200000\0" \
+ "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
+ "update=protect off " xstr(TEXT_BASE) " +${filesize};" \
+ "erase " xstr(TEXT_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " xstr(TEXT_BASE) \
+ " ${filesize};" \
+ "protect on " xstr(TEXT_BASE) " +${filesize}\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+#define CONFIG_MISC_INIT_R 1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Enable an alternate, more extensive memory test */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#endif /* __MANROLAND_COMMON_H */
diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h
new file mode 100644
index 0000000000..2f092b1807
--- /dev/null
+++ b/include/configs/manroland/mpc5200-common.h
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MANROLAND_MPC52XX__COMMON_H
+#define __MANROLAND_MPC52XX__COMMON_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\
+ 230400 }
+
+#if (TEXT_BASE == 0xFFF00000) /* Boot low */
+# define CONFIG_SYS_LOWBOOT 1
+#endif
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE 0xFF800000
+
+#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
+
+#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
+ (= chip selects) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SIZE 0x4000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR 0xF0000000
+#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END -\
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */
+#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_DDR 1
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#else
+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT 1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (192 << 10)
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_MII 1
+
+/*use Hardware WDT */
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
+#endif
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL HID0_ICE
+#else
+#define CONFIG_SYS_HID0_INIT 0
+#define CONFIG_SYS_HID0_FINAL 0
+#endif
+
+#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+
+/* 8Mbit SRAM @0x80100000 */
+#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
+
+#define CONFIG_SYS_CS_BURST 0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
+
+#define CONFIG_IDE_PREINIT 1
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE 4
+
+#define CONFIG_ATAPI 1
+
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
+
+#endif /* __MANROLAND_MPC52XX__COMMON_H */