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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2016-01-27 08:46:11 +0100 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2016-01-31 16:32:56 +0100 |
| commit | 3709844f2366cd75eacee1deeedadaa507ddc9a1 (patch) | |
| tree | d89b5d8b6a58a9dc38d18e3415a06a9622932b6e /include/configs/s5p_goni.h | |
| parent | 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc (diff) | |
| download | u-boot-3709844f2366cd75eacee1deeedadaa507ddc9a1.tar.gz | |
armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs/s5p_goni.h')
| -rw-r--r-- | include/configs/s5p_goni.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 8f65d7ed7a..f92c23db51 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -17,6 +17,8 @@ #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ #define CONFIG_MACH_GONI 1 /* working with Goni */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + #include <linux/sizes.h> #include <asm/arch/cpu.h> /* get chip and board defs */ |