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authorTom Rini <trini@konsulko.com>2021-01-18 08:04:28 -0500
committerTom Rini <trini@konsulko.com>2021-01-18 08:04:28 -0500
commit59e4e391df8c254299b1342c3cfa3390e9f1e895 (patch)
tree2dcb7f6fc8b1caab173f2abdbe78f368d254d08c /include/configs/sifive-fu540.h
parentb5b0237d0216db34605ca54b83588fcfcf5e63a8 (diff)
parent9e550e18305fb31af83bfb72d16e86d8c054fb65 (diff)
downloadu-boot-59e4e391df8c254299b1342c3cfa3390e9f1e895.tar.gz
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvWIP/18Jan2021
- Update qemu-riscv.rst build instructions. - Add support for SPI on Kendryte K210. - Add Microchip PolarFire SoC Icicle Kit support. - Add support for an early timer. - Select TIMER_EARLY to avoid infinite recursion for Trace.
Diffstat (limited to 'include/configs/sifive-fu540.h')
-rw-r--r--include/configs/sifive-fu540.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index c1c79db147..0d69d1c548 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -36,6 +36,11 @@
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
+#define RISCV_MMODE_TIMERBASE 0x2000000
+#define RISCV_MMODE_TIMER_FREQ 1000000
+
+#define RISCV_SMODE_TIMER_FREQ 1000000
+
/* Environment options */
#ifndef CONFIG_SPL_BUILD