diff options
| author | Mario Six <mario.six@gdsys.cc> | 2019-01-21 09:18:17 +0100 |
|---|---|---|
| committer | Mario Six <mario.six@gdsys.cc> | 2019-05-21 07:52:33 +0200 |
| commit | 42c9a494f1659db6043f980d5f4fdee86fdf9dfb (patch) | |
| tree | f4a50f87cb3901f0a26b09caa843b48795419c74 /include/configs | |
| parent | 133ec602846d28a7915a7b3149d05d1c8a270873 (diff) | |
| download | u-boot-42c9a494f1659db6043f980d5f4fdee86fdf9dfb.tar.gz | |
mpc83xx: Get rid of CONFIG_SYS_LBC_*
Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value
of either 0x00040000 or 0x00000000.
CONFIG_SYS_LBC_MRTPR always has the value 0x20000000.
CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board.
CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000).
To simplify the configuration files, hardcode the setting of these
values for mpc83xx.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs')
27 files changed, 1 insertions, 172 deletions
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 5d31d4a0b6..85d7ff6c52 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -122,11 +122,6 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - -/* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 6f100fc7e7..4153d609be 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -186,16 +186,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ -/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ - | (0xFF << LBCR_BMT_SHIFT) \ - | 0xF) /* 0x0004ff0f */ - - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ - /* drivers/mtd/nand/raw/nand.c */ #if defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_NAND_BASE 0xFFF00000 diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 0f246dc518..ff8dedf03e 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -159,16 +159,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ -/* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ - | (0xFF << LBCR_BMT_SHIFT) \ - | 0xF) /* 0x0004ff0f */ - - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ - /* drivers/mtd/nand/nand.c */ #define CONFIG_SYS_NAND_BASE 0xE2800000 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 0b94b0c5cf..521c5ca6ee 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -116,11 +116,7 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 -#define CONFIG_FSL_ELBC 1 +#define CONFIG_FSL_ELBC /* * FLASH on the Local Bus diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index a90a9a86f8..418c6729e1 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -114,11 +114,6 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 88b6f87397..df9cc48417 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -114,11 +114,6 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index fdbd15ea93..7640d7610d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -154,14 +154,6 @@ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* * Serial Port */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 1e0e297351..493f6df187 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -151,14 +151,6 @@ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 388910ac38..a3f704c73b 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -251,19 +251,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32*/ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -/* * Serial Port */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 61f9eaf715..724f8afb76 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -134,10 +134,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1 /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 07b206ff9f..13a7682958 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -158,10 +158,6 @@ #define CONFIG_SYS_GBL_DATA_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1 /* diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 928136f325..15ac17985f 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -96,14 +96,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ -/* - * Local Bus LCRR and LBCR regs - * LCRR: no DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ /* diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index d73e848b0c..8029ae9dd7 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -111,11 +111,6 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - -/* * FLASH on the Local Bus */ #if 1 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 155815a881..b1d01c58f9 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -37,15 +37,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR (0x00040000 |\ - (0xFF << LBCR_BMT_SHIFT) |\ - 0xF) - -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -/* * Internal Definitions */ /* diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 0759604810..0094f34ef1 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 319e3bc1ec..5afb969379 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index 85e9101b05..4f61ed0346 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -341,11 +341,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - /* must be after the include because KMBEC_FPGA is otherwise undefined */ #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index 6ec944f942..862fdb7e2d 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index d7cbdde215..802ab9c934 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -333,11 +333,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 0392c3e8b4..3ce4b705b7 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -126,11 +126,6 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - -/* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index b4ae7b7554..d2053cc059 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -123,14 +123,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ /* diff --git a/include/configs/strider.h b/include/configs/strider.h index e92bd1e8f1..22d255aabb 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -111,11 +111,6 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - -/* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 8b3b45416d..9421204f2c 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -286,11 +286,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 5dc9e8997e..3364b5379e 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 9f8c855fb8..db22fe50db 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -289,11 +289,6 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 2116d6bbcf..66f771d818 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -129,13 +129,6 @@ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* - * Local Bus LCRR and LBCR regs - */ -#define CONFIG_SYS_LBC_LBCR 0x00040000 - -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -/* * NAND settings */ #define CONFIG_SYS_NAND_BASE 0x61000000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 1bce6c732d..1c3430d849 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -96,14 +96,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ -/* - * Local Bus LCRR and LBCR regs - * LCRR: no DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 - #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ /* |