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| author | Jagan Teki <jagan@amarulasolutions.com> | 2018-12-31 15:35:01 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-01-18 22:19:09 +0530 |
| commit | 337fcdc06bad484d3af08e0fd0876e22a09358ce (patch) | |
| tree | df491f67132d0a4ac89e6e71bebf9237098b0440 /include/dt-bindings/clock | |
| parent | 8606f960d4e40f1fbd7fb7e1be30c924dbb9dba0 (diff) | |
| download | u-boot-337fcdc06bad484d3af08e0fd0876e22a09358ce.tar.gz | |
clk: sunxi: Add Allwinner H6 CLK driver
Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for
H6, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'include/dt-bindings/clock')
0 files changed, 0 insertions, 0 deletions