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| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2017-04-05 17:32:47 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2017-04-14 14:06:55 +0200 |
| commit | e11b5e8d6ef72f2e83e680d132a0617a4540f0aa (patch) | |
| tree | 887f0804b3091ba95e76ffb4ae451938a8081878 /include/fdtdec.h | |
| parent | cc62ac7578917b0a518c2e56111046c820d6cfa5 (diff) | |
| download | u-boot-e11b5e8d6ef72f2e83e680d132a0617a4540f0aa.tar.gz | |
fdt: Add compatible strings for Arria 10
Add compatible strings for Intel Arria 10 SoCFPGA device.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'include/fdtdec.h')
| -rw-r--r-- | include/fdtdec.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/fdtdec.h b/include/fdtdec.h index d074478f14..2134701c54 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -155,6 +155,14 @@ enum fdt_compat_id { COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* SoCFPGA pinctrl-single */ + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* SoCFPGA hps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG, /* SoCFPGA lwhps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* SoCFPGA fpga2hps bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */ COMPAT_COUNT, }; |