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| author | York Sun <yorksun@freescale.com> | 2015-03-19 09:30:26 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-04-23 08:55:53 -0700 |
| commit | 66869f955417b89dbf6b7cbb72738b2205a26bf8 (patch) | |
| tree | 669eca4ca7d0e4d6d62ce480455d346f2b192f2f /include/fsl_ddr.h | |
| parent | f8cb101e1e3f5ee2007b78b6b12e24120385aeac (diff) | |
| download | u-boot-66869f955417b89dbf6b7cbb72738b2205a26bf8.tar.gz | |
drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_ddr.h')
| -rw-r--r-- | include/fsl_ddr.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index feccef9c9c..4099a74a4a 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -34,9 +34,7 @@ #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) #endif -#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR - -u32 fsl_ddr_get_version(void); +u32 fsl_ddr_get_version(unsigned int ctrl_num); #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* |