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author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-06-23 00:27:31 +0200 |
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committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-08-13 17:12:33 +0200 |
commit | 1ac973a193387afc37b0069c2d011cbf2d5f970f (patch) | |
tree | ddd7b56a93a67a92d78b46c01842808a8244eb36 /include | |
parent | 403e9cbcd5d2da3f5af0e67552c6ecc13a472830 (diff) | |
download | u-boot-1ac973a193387afc37b0069c2d011cbf2d5f970f.tar.gz |
rockchip: rk3368: dts: add DMC node in rk3368.dtsi
For full SPL support, including DRAM initialisation, we need a few
nodes from the DTS: this commit adds the DMC (DRAM controller) node,
the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
as 'u-boot,dm-pre-reloc'. In addition to this, we also include the
dt-binding for the DMC to allow DTS files including this DTSI to refer
to the symbolic constants for the DDR3 bin and for the
memory-schedule.
Note that the DMC contains both the memory regions for the
(Designware) protocol controller as well as the DDR PHY.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions