diff options
| author | Marek Vasut <marex@denx.de> | 2018-05-12 11:56:10 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-05-18 10:30:45 +0200 |
| commit | 19c8fc77e1d3ff45d3ea60e4355039a3a54d4a93 (patch) | |
| tree | 75705333b8024ffdc3cc0d7aadc293864d96a253 /lib/fdtdec.c | |
| parent | 233719cc40b5a00f37949d4173c190edcb4491a1 (diff) | |
| download | u-boot-19c8fc77e1d3ff45d3ea60e4355039a3a54d4a93.tar.gz | |
fdt: Add another Altera Arria10 clock init compatible
The DT bindings for the Arria10 clock init have changed, add another
compatible to make them work with U-Boot until a proper clock driver
gets written.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'lib/fdtdec.c')
| -rw-r--r-- | lib/fdtdec.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 69bf12623e..f4e8dbf699 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -72,6 +72,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"), COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"), COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"), + COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init") }; const char *fdtdec_get_compatible(enum fdt_compat_id id) |