diff options
79 files changed, 2131 insertions, 505 deletions
@@ -291,6 +291,14 @@ config FIT_SIGNATURE_MAX_SIZE device memory. Assure this size does not extend past expected storage space. +config FIT_ENABLE_RSASSA_PSS_SUPPORT + bool "Support rsassa-pss signature scheme of FIT image contents" + depends on FIT_SIGNATURE + default n + help + Enable this to support the pss padding algorithm as described + in the rfc8017 (https://tools.ietf.org/html/rfc8017). + config FIT_VERBOSE bool "Show verbose messages when FIT images fail" help diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 9920d2e719..fff6591c68 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -16,6 +16,20 @@ * access: "lr"/"sr". */ +/* + * Typically 8 least significant bits of Build Configuration Register (BCR) + * describe version of the HW block in question. Moreover if decoded version + * is 0 this means given HW block is absent - this is especially useful because + * we may safely read BRC regardless HW block existence while an attempt to + * access any other AUX regs associated with this HW block lead to imediate + * "instruction error" exception. + * + * I.e. before using any cofigurable HW block it's required to make sure it + * exists at all, and for that we introduce a special macro below. + */ +#define ARC_BCR_VERSION_MASK GENMASK(7, 0) +#define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK) + #define ARC_AUX_IDENTITY 0x04 #define ARC_AUX_STATUS32 0x0a @@ -73,7 +87,7 @@ #define ARC_BCR_CLUSTER 0xcf /* MMU Management regs */ -#define ARC_AUX_MMU_BCR 0x06f +#define ARC_AUX_MMU_BCR 0x6f /* IO coherency related auxiliary registers */ #define ARC_AUX_IO_COH_ENABLE 0x500 @@ -81,6 +95,15 @@ #define ARC_AUX_IO_COH_AP0_BASE 0x508 #define ARC_AUX_IO_COH_AP0_SIZE 0x509 +/* XY-memory related */ +#define ARC_AUX_XY_BUILD 0x79 + +/* DSP-extensions related auxiliary registers */ +#define ARC_AUX_DSP_BUILD 0x7A + +/* ARC Subsystems related auxiliary registers */ +#define ARC_AUX_SUBSYS_BUILD 0xF0 + #ifndef __ASSEMBLY__ /* Accessors for auxiliary registers */ #define read_aux_reg(reg) __builtin_arc_lr(reg) diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index a969a16722..07daaa8d15 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <malloc.h> #include <asm/arcregs.h> #include <asm/cache.h> @@ -35,34 +36,193 @@ int dram_init(void) } #ifdef CONFIG_DISPLAY_CPUINFO -const char *decode_identity(void) +const char *arc_700_version(int arcver, char *name, int name_len) { - int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff; + const char *arc_ver; + + switch (arcver) { + case 0x32: + arc_ver = "v4.4-4.5"; + break; + case 0x33: + arc_ver = "v4.6-v4.9"; + break; + case 0x34: + arc_ver = "v4.10"; + break; + case 0x35: + arc_ver = "v4.11"; + break; + default: + arc_ver = "unknown version"; + } + + snprintf(name, name_len, "ARC 700 %s", arc_ver); + + return name; +} + +struct em_template_t { + const bool cache; + const bool dsp; + const bool xymem; + const char name[8]; +}; + +static const struct em_template_t em_versions[] = { + {false, false, false, "EM4"}, + {true, false, false, "EM6"}, + {false, true, false, "EM5D"}, + {true, true, false, "EM7D"}, + {false, true, true, "EM9D"}, + {true, true, true, "EM11D"}, +}; + +const char *arc_em_version(int arcver, char *name, int name_len) +{ + const char *arc_name = "EM"; + const char *arc_ver; + bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD); + bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD); + bool xymem = ARC_FEATURE_EXISTS(ARC_AUX_XY_BUILD); + int i; + + for (i = 0; i++ < sizeof(em_versions) / sizeof(struct em_template_t);) { + if (em_versions[i].cache == cache && + em_versions[i].dsp == dsp && + em_versions[i].xymem == xymem) { + arc_name = em_versions[i].name; + break; + } + } + + switch (arcver) { + case 0x41: + arc_ver = "v1.1a"; + break; + case 0x42: + arc_ver = "v3.0"; + break; + case 0x43: + arc_ver = "v4.0"; + break; + case 0x44: + arc_ver = "v5.0"; + break; + default: + arc_ver = "unknown version"; + } + + snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver); + + return name; +} + +struct hs_template_t { + const bool cache; + const bool mmu; + const bool dual_issue; + const bool dsp; + const char name[8]; +}; + +static const struct hs_template_t hs_versions[] = { + {false, false, false, false, "HS34"}, + {true, false, false, false, "HS36"}, + {true, true, false, false, "HS38"}, + {false, false, true, false, "HS44"}, + {true, false, true, false, "HS46"}, + {true, true, true, false, "HS48"}, + {false, false, true, true, "HS45D"}, + {true, false, true, true, "HS47D"}, +}; + +const char *arc_hs_version(int arcver, char *name, int name_len) +{ + const char *arc_name = "HS"; + const char *arc_ver; + bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD); + bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD); + bool mmu = !!read_aux_reg(ARC_AUX_MMU_BCR); + bool dual_issue = arcver == 0x54 ? true : false; + int i; + + for (i = 0; i++ < sizeof(hs_versions) / sizeof(struct hs_template_t);) { + if (hs_versions[i].cache == cache && + hs_versions[i].mmu == mmu && + hs_versions[i].dual_issue == dual_issue && + hs_versions[i].dsp == dsp) { + arc_name = hs_versions[i].name; + break; + } + } switch (arcver) { - /* ARCompact cores */ - case 0x32: return "ARC 700 v4.4-4.5"; - case 0x33: return "ARC 700 v4.6-v4.9"; - case 0x34: return "ARC 700 v4.10"; - case 0x35: return "ARC 700 v4.11"; - - /* ARCv2 cores */ - case 0x41: return "ARC EM v1.1a"; - case 0x42: return "ARC EM v3.0"; - case 0x43: return "ARC EM v4.0"; - case 0x50: return "ARC HS v1.0"; - case 0x51: return "ARC EM v2.0"; - case 0x52: return "ARC EM v2.1"; - case 0x53: return "ARC HS v3.0"; - case 0x54: return "ARC HS v4.0"; - - default: return "Unknown ARC core"; + case 0x50: + arc_ver = "v1.0"; + break; + case 0x51: + arc_ver = "v2.0"; + break; + case 0x52: + arc_ver = "v2.1c"; + break; + case 0x53: + arc_ver = "v3.0"; + break; + case 0x54: + arc_ver = "v4.0"; + break; + default: + arc_ver = "unknown version"; } + + snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver); + + return name; +} + +const char *decode_identity(void) +{ +#define MAX_CPU_NAME_LEN 64 + + int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff; + char *name = malloc(MAX_CPU_NAME_LEN); + + if (arcver >= 0x50) + return arc_hs_version(arcver, name, MAX_CPU_NAME_LEN); + else if (arcver >= 0x40) + return arc_em_version(arcver, name, MAX_CPU_NAME_LEN); + else if (arcver >= 0x30) + return arc_700_version(arcver, name, MAX_CPU_NAME_LEN); + else + return "Unknown ARC core"; +} + +const char *decode_subsystem(void) +{ + int subsys_type = read_aux_reg(ARC_AUX_SUBSYS_BUILD) & GENMASK(3, 0); + + switch (subsys_type) { + case 0: return NULL; + case 2: return "ARC Sensor & Control IP Subsystem"; + case 3: return "ARC Data Fusion IP Subsystem"; + case 4: return "ARC Secure Subsystem"; + default: return "Unknown subsystem"; + }; } __weak int print_cpuinfo(void) { - printf("CPU: %s\n", decode_identity()); + const char *subsys_name = decode_subsystem(); + char mhz[8]; + + printf("CPU: %s at %s MHz\n", decode_identity(), + strmhz(mhz, gd->cpu_clk)); + + if (subsys_name) + printf("Subsys:%s\n", subsys_name); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/dts/am335x-baltos.dts b/arch/arm/dts/am335x-baltos.dts new file mode 100644 index 0000000000..f939cf6406 --- /dev/null +++ b/arch/arm/dts/am335x-baltos.dts @@ -0,0 +1,439 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am33xx.dtsi" +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "OnRISC Baltos"; + compatible = "vscom,onrisc", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ + 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ + 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ + 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ + 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ + 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ + 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ + >; + }; + + tps65910_pins: pinmux_tps65910_pins { + pinctrl-single,pins = < + 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ + >; + + }; + tca6416_pins: pinmux_tca6416_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ + + + /* Slave 2 */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + status = "okay"; + + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + ti,nand-xfer-type = "polled"; + + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + + boot@0 { + label = "SPL"; + reg = <0x0 0x20000>; + }; + boot@20000{ + label = "SPL.backup1"; + reg = <0x20000 0x20000>; + }; + boot@40000 { + label = "SPL.backup2"; + reg = <0x40000 0x20000>; + }; + boot@60000 { + label = "SPL.backup3"; + reg = <0x60000 0x20000>; + }; + boot@80000 { + label = "u-boot"; + reg = <0x80000 0x1e0000>; + }; + boot@260000 { + label = "UBI"; + reg = <0x260000 0xfda0000>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <1000>; + + tps: tps@2d { + reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <28 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65910_pins>; + }; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <8>; + reg = <0x50>; + }; + + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tca6416_pins>; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +/include/ "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + ti,en-ck32k-xtal = <1>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <7>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <2>; +}; + +&phy_sel { + rmii-clock-ext = <1>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc_reg>; + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi index 3c31e21cbe..f1e5cdbade 100644 --- a/arch/arm/dts/meson-gx.dtsi +++ b/arch/arm/dts/meson-gx.dtsi @@ -35,10 +35,16 @@ no-map; }; + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved_alt: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0x0 0xbc00000>; + size = <0x0 0x10000000>; alignment = <0x0 0x400000>; linux,cma-default; }; @@ -338,7 +344,7 @@ ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; + compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; reg = <0x0 0x0 0x0 0x100>; pwrc_vpu: power-controller-vpu { @@ -417,6 +423,19 @@ }; }; + dmcbus: bus@c8838000 { + compatible = "simple-bus"; + reg = <0x0 0xc8838000 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; + + canvas: video-lut@48 { + compatible = "amlogic,canvas"; + reg = <0x0 0x48 0x0 0x14>; + }; + }; + hiubus: bus@c883c000 { compatible = "simple-bus"; reg = <0x0 0xc883c000 0x0 0x2000>; @@ -425,7 +444,7 @@ ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; + compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; reg = <0 0 0 0x400>; }; @@ -457,21 +476,21 @@ sd_emmc_a: mmc@70000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x70000 0x0 0x2000>; + reg = <0x0 0x70000 0x0 0x800>; interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; sd_emmc_b: mmc@72000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x72000 0x0 0x2000>; + reg = <0x0 0x72000 0x0 0x800>; interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; sd_emmc_c: mmc@74000 { compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x74000 0x0 0x2000>; + reg = <0x0 0x74000 0x0 0x800>; interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2.dts b/arch/arm/dts/meson-gxbb-nanopi-k2.dts index 7d5709c37e..cbe99bd4e0 100644 --- a/arch/arm/dts/meson-gxbb-nanopi-k2.dts +++ b/arch/arm/dts/meson-gxbb-nanopi-k2.dts @@ -106,6 +106,42 @@ compatible = "mmc-pwrseq-emmc"; reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; }; + + /* CVBS is available on CON1 pin 36, disabled by default */ + cvbs-connector { + compatible = "composite-video-connector"; + status = "disabled"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; }; ðmac { @@ -137,6 +173,18 @@ }; }; +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>; diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi index 562c26a0ba..1ade7e4868 100644 --- a/arch/arm/dts/meson-gxbb.dtsi +++ b/arch/arm/dts/meson-gxbb.dtsi @@ -307,11 +307,10 @@ clock-names = "isfr", "iahb", "venci"; }; -&hiubus { - clkc: clock-controller@0 { +&sysctrl { + clkc: clock-controller { compatible = "amlogic,gxbb-clkc"; #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x3db>; }; }; @@ -391,7 +390,7 @@ }; }; - spi_pins: spi { + spi_pins: spi-pins { mux { groups = "spi_miso", "spi_mosi", @@ -716,6 +715,7 @@ <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; }; &sd_emmc_b { @@ -723,6 +723,7 @@ <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; }; &sd_emmc_c { @@ -730,6 +731,7 @@ <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; }; &spicc { @@ -749,12 +751,12 @@ }; &uart_AO { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; &uart_AO_B { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm/dts/meson-gxl-mali.dtsi b/arch/arm/dts/meson-gxl-mali.dtsi index eb327664a4..6aaafff674 100644 --- a/arch/arm/dts/meson-gxl-mali.dtsi +++ b/arch/arm/dts/meson-gxl-mali.dtsi @@ -6,7 +6,7 @@ &apb { mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; reg = <0x0 0xc0000 0x0 0x40000>; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts index 3e3eb31748..90a56af967 100644 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts @@ -13,7 +13,7 @@ / { compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Libre Technology CC"; + model = "Libre Computer Board AML-S905X-CC"; aliases { serial0 = &uart_AO; @@ -234,9 +234,6 @@ bus-width = <4>; cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; max-frequency = <100000000>; disable-wp; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi index 3bd405079b..a1b31013ab 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -191,8 +191,8 @@ }; &usb2_phy0 { - /* - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; + /* + * HDMI_5V is also used as supply for the USB VBUS. + */ + phy-supply = <&hdmi_5v>; }; diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi index dba365ed4b..8f0bb3c44b 100644 --- a/arch/arm/dts/meson-gxl.dtsi +++ b/arch/arm/dts/meson-gxl.dtsi @@ -13,14 +13,6 @@ / { compatible = "amlogic,meson-gxl"; - reserved-memory { - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved_alt: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - }; - soc { usb0: usb@c9000000 { status = "disabled"; @@ -267,11 +259,10 @@ clock-names = "isfr", "iahb", "venci"; }; -&hiubus { - clkc: clock-controller@0 { - compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc"; +&sysctrl { + clkc: clock-controller { + compatible = "amlogic,gxl-clkc"; #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x3db>; }; }; @@ -346,7 +337,7 @@ }; }; - spi_pins: spi { + spi_pins: spi-pins { mux { groups = "spi_miso", "spi_mosi", @@ -725,13 +716,15 @@ <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; }; &sd_emmc_b { clocks = <&clkc CLKID_SD_EMMC_B>, <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; }; &sd_emmc_c { @@ -739,6 +732,7 @@ <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; }; &spicc { @@ -758,12 +752,12 @@ }; &uart_AO { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; &uart_AO_B { - clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts index 0868da476e..313f88f875 100644 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts @@ -209,10 +209,34 @@ #cooling-cells = <2>; }; +&cpu1 { + #cooling-cells = <2>; +}; + +&cpu2 { + #cooling-cells = <2>; +}; + +&cpu3 { + #cooling-cells = <2>; +}; + &cpu4 { #cooling-cells = <2>; }; +&cpu5 { + #cooling-cells = <2>; +}; + +&cpu6 { + #cooling-cells = <2>; +}; + +&cpu7 { + #cooling-cells = <2>; +}; + ðmac { pinctrl-0 = <ð_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index 5e3c195d4c..0f269d0469 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -46,6 +46,54 @@ regulator-boot-on; regulator-always-on; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &avb { @@ -94,14 +142,38 @@ function = "scif_clk"; }; + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + sdhi3_pins: sd2 { - groups = "sdhi3_data8", "sdhi3_ctrl"; + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; function = "sdhi3"; power-source = <1800>; }; sdhi3_pins_uhs: sd2_uhs { - groups = "sdhi3_data8", "sdhi3_ctrl"; + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; function = "sdhi3"; power-source = <1800>; }; @@ -120,11 +192,40 @@ }; &sdhi0 { + /* full size SD */ + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + max-frequency = <208000000>; }; &sdhi1 { + /* microSD */ + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + max-frequency = <208000000>; }; &sdhi3 { @@ -137,6 +238,7 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; + mmc-hs400-1_8v; non-removable; status = "okay"; }; diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index a36e0ebca0..b036a713ea 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -480,13 +480,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -618,8 +618,13 @@ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + + max-frequency = <208000000>; }; &sdhi2 { @@ -632,9 +637,11 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; + mmc-hs400-1_8v; non-removable; fixed-emmc-driver-type = <1>; status = "okay"; + max-frequency = <200000000>; }; &sdhi3 { @@ -647,8 +654,12 @@ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + max-frequency = <208000000>; }; &ssi1 { diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index ab886650cd..e16c7f245e 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -308,13 +308,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -396,8 +396,12 @@ vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; sd-uhs-sdr50; + sd-uhs-sdr104; status = "okay"; + max-frequency = <208000000>; }; &sdhi2 { @@ -410,8 +414,10 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; + mmc-hs400-1_8v; non-removable; status = "okay"; + max-frequency = <200000000>; }; &ssi1 { diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 8dde4beeea..b8bdaaec2f 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -144,9 +144,11 @@ in_flash: ori r2, r2, CONFIG_SYS_DER@l mtspr DER, r2 - /* set up the stack in internal DPRAM */ + /* set up the stack on top of internal DPRAM */ lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + stw r0, -4(r3) + stw r0, -8(r3) addi r1, r3, -8 bl board_init_f_alloc_reserve diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index a19aa56300..172bed4c20 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb +dtb-$(CONFIG_MCR3000) += mcr3000.dtb targets += $(dtb-y) diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts new file mode 100644 index 0000000000..5abf111dc5 --- /dev/null +++ b/arch/powerpc/dts/mcr3000.dts @@ -0,0 +1,22 @@ +/* + * MCR3000 Device Tree Source + * + * Copyright 2017 CS Systemes d'Information + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/ { + WDT: watchdog@0 { + compatible = "fsl,pq1-wdt"; + }; + SERIAL: smc@0 { + compatible = "fsl,pq1-smc"; + }; + + chosen { + stdout-path = &SERIAL; + }; +}; diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c index ffbeb14ed0..d26ac35b44 100644 --- a/board/cssi/MCR3000/MCR3000.c +++ b/board/cssi/MCR3000/MCR3000.c @@ -12,6 +12,8 @@ #include <mpc8xx.h> #include <fdt_support.h> #include <asm/io.h> +#include <dm/uclass.h> +#include <wdt.h> DECLARE_GLOBAL_DATA_PTR; @@ -143,3 +145,17 @@ int board_early_init_f(void) return 0; } + +int board_early_init_r(void) +{ + struct udevice *watchdog_dev = NULL; + + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { + puts("Cannot find watchdog!\n"); + } else { + puts("Enabling watchdog.\n"); + wdt_start(watchdog_dev, 0xffff, 0); + } + + return 0; +} diff --git a/board/cssi/MCR3000/u-boot.lds b/board/cssi/MCR3000/u-boot.lds index a32c0e721e..70aef3241c 100644 --- a/board/cssi/MCR3000/u-boot.lds +++ b/board/cssi/MCR3000/u-boot.lds @@ -19,7 +19,6 @@ SECTIONS arch/powerpc/cpu/mpc8xx/start.o (.text) arch/powerpc/cpu/mpc8xx/traps.o (.text*) arch/powerpc/lib/built-in.o (.text*) - board/cssi/MCR3000/built-in.o (.text*) drivers/net/built-in.o (.text*) . = DEFINED(env_offset) ? env_offset : .; @@ -69,6 +68,12 @@ SECTIONS __ex_table : { *(__ex_table) } __stop___ex_table = .; + /* + * _end - This is end of u-boot.bin image. + * dtb will be appended here to make u-boot-dtb.bin + */ + _end = .; + . = ALIGN(4096); __init_begin = .; .text.init : { *(.text.init) } diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c index c95f7af7a7..ffa7c154b5 100644 --- a/board/synopsys/axs10x/axs10x.c +++ b/board/synopsys/axs10x/axs10x.c @@ -109,3 +109,11 @@ void smp_kick_all_cpus(void) writel(cmd, (void __iomem *)AXC003_CREG_CPU_START); } #endif + +int checkboard(void) +{ + printf("Board: ARC Software Development Platform AXS%s\n", + is_isa_arcv2() ? "103" : "101"); + + return 0; +}; diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c index b5ec7f17ec..c0770b58c1 100644 --- a/board/synopsys/emsdp/emsdp.c +++ b/board/synopsys/emsdp/emsdp.c @@ -7,10 +7,46 @@ #include <dwmmc.h> #include <malloc.h> +#include <asm/arcregs.h> + DECLARE_GLOBAL_DATA_PTR; -#define ARC_PERIPHERAL_BASE 0xF0000000 -#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0x10000) +#define ARC_PERIPHERAL_BASE 0xF0000000 + +#define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84) +#define CGU_ARC_FMEAS_ARC_START BIT(31) +#define CGU_ARC_FMEAS_ARC_DONE BIT(30) +#define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0) +#define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0 +#define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15 + +#define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000) + +int mach_cpu_init(void) +{ + int rcnt, fcnt; + u32 data; + + /* Start frequency measurement */ + writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC); + + /* Poll DONE bit */ + do { + data = readl(CGU_ARC_FMEAS_ARC); + } while (!(data & CGU_ARC_FMEAS_ARC_DONE)); + + /* Amount of reference 100 MHz clocks */ + rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) & + CGU_ARC_FMEAS_ARC_CNT_MASK); + + /* Amount of CPU clocks */ + fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) & + CGU_ARC_FMEAS_ARC_CNT_MASK); + + gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000; + + return 0; +} int board_mmc_init(bd_t *bis) { @@ -24,7 +60,7 @@ int board_mmc_init(bd_t *bis) memset(host, 0, sizeof(struct dwmci_host)); host->name = "Synopsys Mobile storage"; - host->ioaddr = (void *)SDIO_BASE; + host->ioaddr = SDIO_BASE; host->buswidth = 4; host->dev_index = 0; host->bus_hz = 50000000; @@ -42,31 +78,32 @@ int board_mmc_getcd(struct mmc *mmc) } #define CREG_BASE 0xF0001000 -#define CREG_BOOT_OFFSET 0 -#define CREG_BOOT_WP_OFFSET 8 +#define CREG_BOOT (void *)(CREG_BASE + 0x0FF0) +#define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0) +#define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8) -#define CGU_BASE 0xF0000000 -#define CGU_IP_SW_RESET 0x0FF0 +/* Bits in CREG_BOOT register */ +#define CREG_BOOT_WP_BIT BIT(8) void reset_cpu(ulong addr) { - writel(1, (u32 *)(CGU_BASE + CGU_IP_SW_RESET)); + writel(1, CREG_IP_SW_RESET); while (1) ; /* loop forever till reset */ } static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - u32 creg_boot = readl((u32 *)(CREG_BASE + CREG_BOOT_OFFSET)); + u32 creg_boot = readl(CREG_BOOT); if (!strcmp(argv[1], "unlock")) - creg_boot &= ~BIT(CREG_BOOT_WP_OFFSET); + creg_boot &= ~CREG_BOOT_WP_BIT; else if (!strcmp(argv[1], "lock")) - creg_boot |= BIT(CREG_BOOT_WP_OFFSET); + creg_boot |= CREG_BOOT_WP_BIT; else return CMD_RET_USAGE; - writel(creg_boot, (u32 *)(CREG_BASE + CREG_BOOT_OFFSET)); + writel(creg_boot, CREG_BOOT); return CMD_RET_SUCCESS; } @@ -97,3 +134,12 @@ U_BOOT_CMD( "rom unlock - Unlock non-volatile memory for writing\n" "emsdp rom lock - Lock non-volatile memory to prevent writing\n" ); + +int checkboard(void) +{ + int version = readl(CREG_IP_VERSION); + + printf("Board: ARC EM Software Development Platform v%d.%d\n", + (version >> 16) & 0xff, version & 0xff); + return 0; +}; diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index b6aefdbe6d..8a2c201477 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -1054,10 +1054,8 @@ int board_mmc_init(bd_t *bis) return 0; } -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void) +int checkboard(void) { - printf("CPU: ARC HS38 v2.1c\n"); + puts("Board: Synopsys ARC HS Development Kit\n"); return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ +}; diff --git a/board/synopsys/iot_devkit/iot_devkit.c b/board/synopsys/iot_devkit/iot_devkit.c index f8838fb3ce..8424e09bd3 100644 --- a/board/synopsys/iot_devkit/iot_devkit.c +++ b/board/synopsys/iot_devkit/iot_devkit.c @@ -189,13 +189,3 @@ int checkboard(void) puts("Board: Synopsys IoT Development Kit\n"); return 0; }; - -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void) -{ - char mhz[8]; - - printf("CPU: ARC EM9D at %s MHz\n", strmhz(mhz, gd->cpu_clk)); - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index df0a2d2b7a..c5949ad267 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -27,7 +27,6 @@ #include <i2c.h> #include <miiphy.h> #include <cpsw.h> -#include <power/tps65217.h> #include <power/tps65910.h> #include <environment.h> #include <watchdog.h> @@ -35,8 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; -/* GPIO that controls power to DDR on EVM-SK */ -#define GPIO_DDR_VTT_EN 7 +/* GPIO that controls DIP switch and mPCIe slot */ #define DIP_S1 44 #define MPCIE_SW 100 @@ -248,9 +246,6 @@ const struct ctrl_ioregs ioregs_baltos = { void sdram_init(void) { - gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); - gpio_direction_output(GPIO_DDR_VTT_EN, 1); - config_ddr(400, &ioregs_baltos, &ddr3_baltos_data, &ddr3_baltos_cmd_ctrl_data, diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c index 94410ae35e..9c5542ea02 100644 --- a/board/vscom/baltos/mux.c +++ b/board/vscom/baltos/mux.c @@ -34,7 +34,6 @@ static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ - //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ {-1}, }; @@ -46,11 +45,6 @@ static struct module_pin_mux i2c1_pin_mux[] = { {-1}, }; -static struct module_pin_mux gpio0_7_pin_mux[] = { - {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ - {-1}, -}; - static struct module_pin_mux rmii1_pin_mux[] = { {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ @@ -114,7 +108,6 @@ void enable_i2c1_pin_mux(void) void enable_board_pin_mux() { configure_module_pin_mux(i2c1_pin_mux); - configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii2_pin_mux); configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 4052cf494a..e88cb131a1 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -137,6 +137,23 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen, spi_write(addr, alen, buffer, len); #else /* I2C */ +#if defined(CONFIG_DM_I2C) && defined(CONFIG_SYS_I2C_EEPROM_BUS) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_EEPROM_BUS, addr[0], + alen - 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_I2C_EEPROM_BUS); + return CMD_RET_FAILURE; + } + + if (read) + ret = dm_i2c_read(dev, offset, buffer, len); + else + ret = dm_i2c_write(dev, offset, buffer, len); + +#else /* Non DM I2C support - will be removed */ #if defined(CONFIG_SYS_I2C_EEPROM_BUS) i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); #endif @@ -145,10 +162,11 @@ static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen, ret = i2c_read(addr[0], offset, alen - 1, buffer, len); else ret = i2c_write(addr[0], offset, alen - 1, buffer, len); - - if (ret) - ret = 1; #endif +#endif /* CONFIG_DM_I2C && CONFIG_SYS_I2C_EEPROM_BUS */ + if (ret) + ret = CMD_RET_FAILURE; + return ret; } diff --git a/common/board_r.c b/common/board_r.c index 745212be71..21d3b3c64c 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -744,7 +744,7 @@ static init_fnc_t init_sequence_r[] = { /* initialize higher level parts of CPU like time base and timers */ cpu_init_r, #endif -#ifdef CONFIG_PPC +#if defined(CONFIG_PPC) && !defined(CONFIG_DM_SPI) initr_spi, #endif #ifdef CONFIG_CMD_NAND diff --git a/common/image-fit.c b/common/image-fit.c index 8d39a243f8..ac901e131c 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -165,6 +165,7 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p, uint8_t *value; int value_len; char *algo; + const char *padding; int required; int ret, i; @@ -184,6 +185,10 @@ static void fit_image_print_data(const void *fit, int noffset, const char *p, printf(" (required)"); printf("\n"); + padding = fdt_getprop(fit, noffset, "padding", NULL); + if (padding) + printf("%s %s padding: %s\n", p, type, padding); + ret = fit_image_hash_get_value(fit, noffset, &value, &value_len); printf("%s %s value: ", p, type); diff --git a/common/image-sig.c b/common/image-sig.c index 5d860e1266..4f6b4ec412 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -71,6 +71,19 @@ struct crypto_algo crypto_algos[] = { }; +struct padding_algo padding_algos[] = { + { + .name = "pkcs-1.5", + .verify = padding_pkcs_15_verify, + }, +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT + { + .name = "pss", + .verify = padding_pss_verify, + } +#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */ +}; + struct checksum_algo *image_get_checksum_algo(const char *full_name) { int i; @@ -106,6 +119,21 @@ struct crypto_algo *image_get_crypto_algo(const char *full_name) return NULL; } +struct padding_algo *image_get_padding_algo(const char *name) +{ + int i; + + if (!name) + return NULL; + + for (i = 0; i < ARRAY_SIZE(padding_algos); i++) { + if (!strcmp(padding_algos[i].name, name)) + return &padding_algos[i]; + } + + return NULL; +} + /** * fit_region_make_list() - Make a list of image regions * @@ -155,6 +183,7 @@ static int fit_image_setup_verify(struct image_sign_info *info, char **err_msgp) { char *algo_name; + const char *padding_name; if (fdt_totalsize(fit) > CONFIG_FIT_SIGNATURE_MAX_SIZE) { *err_msgp = "Total size too large"; @@ -165,6 +194,11 @@ static int fit_image_setup_verify(struct image_sign_info *info, *err_msgp = "Can't get hash algo property"; return -1; } + + padding_name = fdt_getprop(fit, noffset, "padding", NULL); + if (!padding_name) + padding_name = RSA_DEFAULT_PADDING_NAME; + memset(info, '\0', sizeof(*info)); info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); info->fit = (void *)fit; @@ -172,6 +206,7 @@ static int fit_image_setup_verify(struct image_sign_info *info, info->name = algo_name; info->checksum = image_get_checksum_algo(algo_name); info->crypto = image_get_crypto_algo(algo_name); + info->padding = image_get_padding_algo(padding_name); info->fdt_blob = gd_fdt_blob(); info->required_keynode = required_keynode; printf("%s:%s", algo_name, info->keyname); diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 29a60e3a98..33c6073648 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -42,6 +42,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flashboot" CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="S3K> " @@ -73,3 +74,9 @@ CONFIG_MPC8XX_FEC=y CONFIG_SHA256=y CONFIG_LZMA=y CONFIG_OF_LIBFDT=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="mcr3000" +CONFIG_WDT=y +CONFIG_WDT_MPC8xx=y +CONFIG_DM_SERIAL=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index a61b13b6fc..05d41aea87 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_AM33XX=y @@ -39,17 +38,26 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)" CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_OMAP24_I2C_SPEED=1000 +CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_OMAP_HS_ADMA=y CONFIG_NAND=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x00080000 CONFIG_PHY_ADDR_ENABLE=y -CONFIG_DRIVER_TI_CPSW=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_SMSC=y CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_DSPS=y @@ -59,7 +67,7 @@ CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_ETHER=y CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index cf1fd0b6c6..9e31b4ac97 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -40,6 +40,7 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y +CONFIG_RTC_M41T62=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_SPI=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 795f8a3ebc..dd7aed324f 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -49,6 +49,7 @@ CONFIG_NAND=y CONFIG_NAND_MXC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y +CONFIG_RTC_M41T62=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 0c8e31a9ec..e207df51a8 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -35,5 +35,6 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y +CONFIG_RTC_M41T62=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index 40712a44c3..149d6274aa 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -41,6 +41,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index f1d150b5a0..8d765e2804 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -41,6 +41,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig index 72549e2836..2d6b86f0bb 100644 --- a/configs/r8a77965_salvator-x_defconfig +++ b/configs/r8a77965_salvator-x_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index 7c39268a43..352504532d 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index ef5c9443f9..b68bb7c647 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 7363310d52..5a8fc04e17 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 5a744f4791..1a76785498 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -5,6 +5,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index c8f5f66232..a96f54c737 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -52,6 +52,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_RTC_M41T62=y CONFIG_CONS_INDEX=0 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index a765722679..bfff6fdc73 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -106,6 +106,9 @@ When the image is signed, the following properties are optional: - comment: Additional information about the signer or image +- padding: The padding algorithm, it may be pkcs-1.5 or pss, + if no value is provided we assume pkcs-1.5 + For config bindings (see Signed Configurations below), the following additional properties are optional: diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c index 0df8b91d42..2cb53fb92d 100644 --- a/drivers/clk/clk_meson.c +++ b/drivers/clk/clk_meson.c @@ -11,6 +11,8 @@ #include <clk-uclass.h> #include <div64.h> #include <dm.h> +#include <regmap.h> +#include <syscon.h> #include <dt-bindings/clock/gxbb-clkc.h> #include "clk_meson.h" @@ -65,7 +67,7 @@ #define XTAL_RATE 24000000 struct meson_clk { - void __iomem *addr; + struct regmap *map; }; static ulong meson_div_get_rate(struct clk *clk, unsigned long id); @@ -217,8 +219,8 @@ static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on) debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id); - clrsetbits_le32(priv->addr + gate->reg, - BIT(gate->bit), on ? BIT(gate->bit) : 0); + regmap_update_bits(priv->map, gate->reg, + BIT(gate->bit), on ? BIT(gate->bit) : 0); /* Propagate to next gate(s) */ switch (id) { @@ -269,7 +271,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id) unsigned int rate, parent_rate; struct parm *parm; int parent; - u32 reg; + uint reg; switch (id) { case CLKID_VPU_0_DIV: @@ -292,7 +294,7 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id) return -ENOENT; } - reg = readl(priv->addr + parm->reg_off); + regmap_read(priv->map, parm->reg_off, ®); reg = PARM_GET(parm->width, parm->shift, reg); debug("%s: div of %ld is %d\n", __func__, id, reg + 1); @@ -318,7 +320,6 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, unsigned long parent_rate; struct parm *parm; int parent; - u32 reg; int ret; if (current_rate == rate) @@ -383,9 +384,8 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, debug("%s: setting div of %ld to %d\n", __func__, id, new_div); - reg = readl(priv->addr + parm->reg_off); - writel(PARM_SET(parm->width, parm->shift, reg, new_div - 1), - priv->addr + parm->reg_off); + regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift), + (new_div - 1) << parm->shift); debug("%s: new rate of %ld is %ld\n", __func__, id, meson_div_get_rate(clk, id)); @@ -446,7 +446,7 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id) struct meson_clk *priv = dev_get_priv(clk->dev); struct parm *parm; int *parents; - u32 reg; + uint reg; switch (id) { case CLKID_VPU: @@ -477,7 +477,7 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id) return -ENOENT; } - reg = readl(priv->addr + parm->reg_off); + regmap_read(priv->map, parm->reg_off, ®); reg = PARM_GET(parm->width, parm->shift, reg); debug("%s: parent of %ld is %d (%d)\n", @@ -494,7 +494,6 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id, unsigned int new_index = -EINVAL; struct parm *parm; int *parents; - u32 reg; int i; if (IS_ERR_VALUE(cur_parent)) @@ -546,9 +545,8 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id, debug("%s: new index of %ld is %d\n", __func__, id, new_index); - reg = readl(priv->addr + parm->reg_off); - writel(PARM_SET(parm->width, parm->shift, reg, new_index), - priv->addr + parm->reg_off); + regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift), + new_index << parm->shift); debug("%s: new parent of %ld is %ld\n", __func__, id, meson_mux_get_parent(clk, id)); @@ -570,7 +568,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) { struct meson_clk *priv = dev_get_priv(clk->dev); unsigned long parent_rate; - u32 reg; + uint reg; int parents[] = { -1, -1, @@ -583,7 +581,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) }; /* mux */ - reg = readl(priv->addr + HHI_MPEG_CLK_CNTL); + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); reg = (reg >> 12) & 7; switch (reg) { @@ -597,7 +595,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) } /* divider */ - reg = readl(priv->addr + HHI_MPEG_CLK_CNTL); + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); reg = reg & ((1 << 7) - 1); /* clk81 divider is zero based */ @@ -641,8 +639,9 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id) { struct meson_clk *priv = dev_get_priv(clk->dev); struct parm *psdm, *pn2; - unsigned long reg, sdm, n2; + unsigned long sdm, n2; unsigned long parent_rate; + uint reg; switch (id) { case CLKID_MPLL0: @@ -665,10 +664,10 @@ static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id) if (IS_ERR_VALUE(parent_rate)) return parent_rate; - reg = readl(priv->addr + psdm->reg_off); + regmap_read(priv->map, psdm->reg_off, ®); sdm = PARM_GET(psdm->width, psdm->shift, reg); - reg = readl(priv->addr + pn2->reg_off); + regmap_read(priv->map, pn2->reg_off, ®); n2 = PARM_GET(pn2->width, pn2->shift, reg); return mpll_rate_from_params(parent_rate, sdm, n2); @@ -692,7 +691,7 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) struct parm *pm, *pn, *pod; unsigned long parent_rate_mhz = XTAL_RATE / 1000000; u16 n, m, od; - u32 reg; + uint reg; switch (id) { case CLKID_FIXED_PLL: @@ -709,13 +708,13 @@ static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) return -ENOENT; } - reg = readl(priv->addr + pn->reg_off); + regmap_read(priv->map, pn->reg_off, ®); n = PARM_GET(pn->width, pn->shift, reg); - reg = readl(priv->addr + pm->reg_off); + regmap_read(priv->map, pm->reg_off, ®); m = PARM_GET(pm->width, pm->shift, reg); - reg = readl(priv->addr + pod->reg_off); + regmap_read(priv->map, pod->reg_off, ®); od = PARM_GET(pod->width, pod->shift, reg); return ((parent_rate_mhz * m / n) >> od) * 1000000; @@ -876,8 +875,8 @@ static ulong meson_clk_set_rate(struct clk *clk, ulong rate) if (IS_ERR_VALUE(ret)) return ret; - printf("clock %lu has new rate %lu\n", clk->id, - meson_clk_get_rate_by_id(clk, clk->id)); + debug("clock %lu has new rate %lu\n", clk->id, + meson_clk_get_rate_by_id(clk, clk->id)); return 0; } @@ -886,9 +885,11 @@ static int meson_clk_probe(struct udevice *dev) { struct meson_clk *priv = dev_get_priv(dev); - priv->addr = dev_read_addr_ptr(dev); + priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); - debug("meson-clk: probed at addr %p\n", priv->addr); + debug("meson-clk: probed\n"); return 0; } diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 99698b1f46..0529fc8763 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -107,7 +107,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, return renesas_clk_get_parent(clk, info, parent); } -static int gen3_clk_setup_sdif_div(struct clk *clk) +static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); struct cpg_mssr_info *info = priv->info; @@ -133,7 +133,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk) debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset); - writel(1, priv->base + core->offset); + writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset); return 0; } @@ -141,10 +141,6 @@ static int gen3_clk_setup_sdif_div(struct clk *clk) static int gen3_clk_enable(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); - int ret = gen3_clk_setup_sdif_div(clk); - - if (ret) - return ret; return renesas_clk_endisable(clk, priv->base, true); } @@ -328,7 +324,7 @@ static ulong gen3_clk_get_rate(struct clk *clk) static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) { /* Force correct SD-IF divider configuration if applicable */ - gen3_clk_setup_sdif_div(clk); + gen3_clk_setup_sdif_div(clk, rate); return gen3_clk_get_rate64(clk); } diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index f73f07254b..76225b7939 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -166,6 +166,10 @@ int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg) cfg->host_caps |= MMC_CAP(MMC_HS_200); if (dev_read_bool(dev, "mmc-hs200-1_2v")) cfg->host_caps |= MMC_CAP(MMC_HS_200); + if (dev_read_bool(dev, "mmc-hs400-1_8v")) + cfg->host_caps |= MMC_CAP(MMC_HS_400); + if (dev_read_bool(dev, "mmc-hs400-1_2v")) + cfg->host_caps |= MMC_CAP(MMC_HS_400); return 0; } diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index e7f96f8bf2..733b6d62f5 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -17,7 +17,9 @@ #include "tmio-common.h" -#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) /* SCC registers */ #define RENESAS_SDHI_SCC_DTCNTL 0x800 @@ -107,6 +109,56 @@ static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv) tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); } +static int renesas_sdhi_hs400(struct udevice *dev) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + bool hs400 = (mmc->selected_mode == MMC_HS_400); + int ret, taps = hs400 ? priv->nrtaps : 8; + u32 reg; + + if (taps == 4) /* HS400 on 4tap SoC needs different clock */ + ret = clk_set_rate(&priv->clk, 400000000); + else + ret = clk_set_rate(&priv->clk, 200000000); + if (ret < 0) + return ret; + + tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2); + if (hs400) { + reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN | + RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL; + } else { + reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN | + RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL); + } + + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2); + + tmio_sd_writel(priv, (taps << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) | + RENESAS_SDHI_SCC_DTCNTL_TAPEN, + RENESAS_SDHI_SCC_DTCNTL); + + if (taps == 4) { + tmio_sd_writel(priv, priv->tap_set >> 1, + RENESAS_SDHI_SCC_TAPSET); + } else { + tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); + } + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); + reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); + + return 0; +} + static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv, unsigned long tap) { @@ -125,7 +177,6 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, unsigned int smpcmp) { unsigned long tap_cnt; /* counter of tuning success */ - unsigned long tap_set; /* tap position */ unsigned long tap_start;/* start position of tuning success */ unsigned long tap_end; /* end position of tuning success */ unsigned long ntap; /* temporary counter of tuning success */ @@ -209,12 +260,12 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, select = true; if (select) - tap_set = ((tap_start + tap_end) / 2) % tap_num; + priv->tap_set = ((tap_start + tap_end) / 2) % tap_num; else return -EIO; /* Set SCC */ - tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET); + tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); /* Enable auto re-tuning */ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); @@ -240,6 +291,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) /* clock tuning is not needed for upto 52MHz */ if (!((mmc->selected_mode == MMC_HS_200) || + (mmc->selected_mode == MMC_HS_400) || (mmc->selected_mode == UHS_SDR104) || (mmc->selected_mode == UHS_SDR50))) return 0; @@ -287,19 +339,42 @@ out: return ret; } +#else +static int renesas_sdhi_hs400(struct udevice *dev) +{ + return 0; +} #endif static int renesas_sdhi_set_ios(struct udevice *dev) { - int ret = tmio_sd_set_ios(dev); + struct tmio_sd_priv *priv = dev_get_priv(dev); + u32 tmp; + int ret; - mdelay(10); + /* Stop the clock before changing its rate to avoid a glitch signal */ + tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); + tmp &= ~TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); -#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) - struct tmio_sd_priv *priv = dev_get_priv(dev); + ret = renesas_sdhi_hs400(dev); + if (ret) + return ret; + + ret = tmio_sd_set_ios(dev); - if (priv->caps & TMIO_SD_CAP_RCAR_UHS) + mdelay(10); + +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + struct mmc *mmc = mmc_get_mmc_dev(dev); + if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) && + (mmc->selected_mode != UHS_SDR104) && + (mmc->selected_mode != MMC_HS_200) && + (mmc->selected_mode != MMC_HS_400)) { renesas_sdhi_reset_tuning(priv); + } #endif return ret; @@ -331,7 +406,9 @@ static const struct dm_mmc_ops renesas_sdhi_ops = { .send_cmd = tmio_sd_send_cmd, .set_ios = renesas_sdhi_set_ios, .get_cd = tmio_sd_get_cd, -#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) .execute_tuning = renesas_sdhi_execute_tuning, #endif #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) @@ -358,15 +435,45 @@ static const struct udevice_id renesas_sdhi_match[] = { { /* sentinel */ } }; +static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv) +{ + return clk_get_rate(&priv->clk); +} + +static void renesas_sdhi_filter_caps(struct udevice *dev) +{ + struct tmio_sd_plat *plat = dev_get_platdata(dev); + struct tmio_sd_priv *priv = dev_get_priv(dev); + + if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3)) + return; + + /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */ + if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() <= 1)) || + ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() <= 1))) + plat->cfg.host_caps &= ~MMC_MODE_HS400; + + /* H3 ES2.0 uses 4 tuning taps */ + if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() == 2)) + priv->nrtaps = 4; + else + priv->nrtaps = 8; +} + static int renesas_sdhi_probe(struct udevice *dev) { struct tmio_sd_priv *priv = dev_get_priv(dev); u32 quirks = dev_get_driver_data(dev); struct fdt_resource reg_res; - struct clk clk; DECLARE_GLOBAL_DATA_PTR; int ret; + priv->clk_get_rate = renesas_sdhi_clk_get_rate; + if (quirks == RENESAS_GEN2_QUIRKS) { ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", 0, ®_res); @@ -380,29 +487,33 @@ static int renesas_sdhi_probe(struct udevice *dev) quirks |= TMIO_SD_CAP_16BIT; } - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) { dev_err(dev, "failed to get host clock\n"); return ret; } /* set to max rate */ - priv->mclk = clk_set_rate(&clk, ULONG_MAX); - if (IS_ERR_VALUE(priv->mclk)) { + ret = clk_set_rate(&priv->clk, 200000000); + if (ret < 0) { dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&clk); - return priv->mclk; + clk_free(&priv->clk); + return ret; } - ret = clk_enable(&clk); - clk_free(&clk); + ret = clk_enable(&priv->clk); if (ret) { dev_err(dev, "failed to enable host clock\n"); return ret; } ret = tmio_sd_probe(dev, quirks); -#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) + + renesas_sdhi_filter_caps(dev); + +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS)) renesas_sdhi_reset_tuning(priv); #endif diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 0eca83a0f4..201492001f 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -555,55 +555,76 @@ static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv, tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE); } -static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, - struct mmc *mmc) +static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv) { - unsigned int divisor; - u32 val, tmp; + return priv->clk_get_rate(priv); +} - if (!mmc->clock) - return; - - divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); - - if (divisor <= 1) - val = (priv->caps & TMIO_SD_CAP_RCAR) ? - TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; - else if (divisor <= 2) - val = TMIO_SD_CLKCTL_DIV2; - else if (divisor <= 4) - val = TMIO_SD_CLKCTL_DIV4; - else if (divisor <= 8) - val = TMIO_SD_CLKCTL_DIV8; - else if (divisor <= 16) - val = TMIO_SD_CLKCTL_DIV16; - else if (divisor <= 32) - val = TMIO_SD_CLKCTL_DIV32; - else if (divisor <= 64) - val = TMIO_SD_CLKCTL_DIV64; - else if (divisor <= 128) - val = TMIO_SD_CLKCTL_DIV128; - else if (divisor <= 256) - val = TMIO_SD_CLKCTL_DIV256; - else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024)) - val = TMIO_SD_CLKCTL_DIV512; - else - val = TMIO_SD_CLKCTL_DIV1024; +static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc) +{ + unsigned int divisor; + u32 tmp, val = 0; + ulong mclk; + + if (mmc->clock) { + mclk = tmio_sd_clk_get_rate(priv); + + divisor = DIV_ROUND_UP(mclk, mmc->clock); + + /* Do not set divider to 0xff in DDR mode */ + if (mmc->ddr_mode && (divisor == 1)) + divisor = 2; + + if (divisor <= 1) + val = (priv->caps & TMIO_SD_CAP_RCAR) ? + TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; + else if (divisor <= 2) + val = TMIO_SD_CLKCTL_DIV2; + else if (divisor <= 4) + val = TMIO_SD_CLKCTL_DIV4; + else if (divisor <= 8) + val = TMIO_SD_CLKCTL_DIV8; + else if (divisor <= 16) + val = TMIO_SD_CLKCTL_DIV16; + else if (divisor <= 32) + val = TMIO_SD_CLKCTL_DIV32; + else if (divisor <= 64) + val = TMIO_SD_CLKCTL_DIV64; + else if (divisor <= 128) + val = TMIO_SD_CLKCTL_DIV128; + else if (divisor <= 256) + val = TMIO_SD_CLKCTL_DIV256; + else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024)) + val = TMIO_SD_CLKCTL_DIV512; + else + val = TMIO_SD_CLKCTL_DIV1024; + } tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); - if (tmp & TMIO_SD_CLKCTL_SCLKEN && - (tmp & TMIO_SD_CLKCTL_DIV_MASK) == val) - return; + if (mmc->clock && + !((tmp & TMIO_SD_CLKCTL_SCLKEN) && + ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) { + /* + * Stop the clock before changing its rate + * to avoid a glitch signal + */ + tmp &= ~TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); - /* stop the clock before changing its rate to avoid a glitch signal */ - tmp &= ~TMIO_SD_CLKCTL_SCLKEN; - tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); + /* Change the clock rate. */ + tmp &= ~TMIO_SD_CLKCTL_DIV_MASK; + tmp |= val; + } - tmp &= ~TMIO_SD_CLKCTL_DIV_MASK; - tmp |= val | TMIO_SD_CLKCTL_OFFEN; - tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); + /* Enable or Disable the clock */ + if (mmc->clk_disable) { + tmp |= TMIO_SD_CLKCTL_OFFEN; + tmp &= ~TMIO_SD_CLKCTL_SCLKEN; + } else { + tmp &= ~TMIO_SD_CLKCTL_OFFEN; + tmp |= TMIO_SD_CLKCTL_SCLKEN; + } - tmp |= TMIO_SD_CLKCTL_SCLKEN; tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); udelay(1000); @@ -708,6 +729,7 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) struct tmio_sd_priv *priv = dev_get_priv(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); fdt_addr_t base; + ulong mclk; int ret; base = devfdt_get_addr(dev); @@ -750,10 +772,12 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) tmio_sd_host_init(priv); + mclk = tmio_sd_clk_get_rate(priv); + plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; - plat->cfg.f_min = priv->mclk / + plat->cfg.f_min = mclk / (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512); - plat->cfg.f_max = priv->mclk; + plat->cfg.f_max = mclk; plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ upriv->mmc = &plat->mmc; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 792b1ba5ae..192026ce3e 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -117,7 +117,6 @@ struct tmio_sd_plat { struct tmio_sd_priv { void __iomem *regbase; - unsigned long mclk; unsigned int version; u32 caps; #define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ @@ -133,6 +132,14 @@ struct tmio_sd_priv { #ifdef CONFIG_DM_REGULATOR struct udevice *vqmmc_dev; #endif +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif +#if CONFIG_IS_ENABLED(RENESAS_SDHI) + u8 tap_set; + u8 nrtaps; +#endif + ulong (*clk_get_rate)(struct tmio_sd_priv *); }; int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 813c28494c..6539880ab5 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -31,35 +31,45 @@ static const struct udevice_id uniphier_sd_match[] = { { /* sentinel */ } }; +static ulong uniphier_sd_clk_get_rate(struct tmio_sd_priv *priv) +{ +#if CONFIG_IS_ENABLED(CLK) + return clk_get_rate(&priv->clk); +#elif CONFIG_SPL_BUILD + return 100000000; +#else + return 0; +#endif +} + static int uniphier_sd_probe(struct udevice *dev) { struct tmio_sd_priv *priv = dev_get_priv(dev); + + priv->clk_get_rate = uniphier_sd_clk_get_rate; + #ifndef CONFIG_SPL_BUILD - struct clk clk; int ret; - ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) { dev_err(dev, "failed to get host clock\n"); return ret; } /* set to max rate */ - priv->mclk = clk_set_rate(&clk, ULONG_MAX); - if (IS_ERR_VALUE(priv->mclk)) { + ret = clk_set_rate(&priv->clk, ULONG_MAX); + if (ret < 0) { dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&clk); - return priv->mclk; + clk_free(&priv->clk); + return ret; } - ret = clk_enable(&clk); - clk_free(&clk); + ret = clk_enable(&priv->clk); if (ret) { dev_err(dev, "failed to enable host clock\n"); return ret; } -#else - priv->mclk = 100000000; #endif return tmio_sd_probe(dev, 0); diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 6038b43230..fd0009b2e2 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -104,4 +104,10 @@ config RTC_MC146818 clock with a wide array of features and 50 bytes of general-purpose, battery-backed RAM. The driver supports access to the clock and RAM. +config RTC_M41T62 + bool "Enable M41T62 driver" + help + Enable driver for ST's M41T62 compatible RTC devices (like RV-4162). + It is a serial (I2C) real-time clock (RTC) with alarm. + endmenu diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 137438389d..2ee7e00b02 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * (C) Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de. + * * (C) Copyright 2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -15,6 +18,7 @@ #include <common.h> #include <command.h> +#include <dm.h> #include <rtc.h> #include <i2c.h> @@ -49,12 +53,8 @@ #define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ -int rtc_get(struct rtc_time *tm) +static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf) { - u8 buf[M41T62_DATETIME_REG_SIZE]; - - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); - debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", __FUNCTION__, @@ -77,20 +77,14 @@ int rtc_get(struct rtc_time *tm) __FUNCTION__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); - - return 0; } -int rtc_set(struct rtc_time *tm) +static void m41t62_set_rtc_buf(const struct rtc_time *tm, u8 *buf) { - u8 buf[M41T62_DATETIME_REG_SIZE]; - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); - /* Merge time-data and register flags into buf[0..7] */ buf[M41T62_REG_SSEC] = 0; buf[M41T62_REG_SEC] = @@ -107,8 +101,99 @@ int rtc_set(struct rtc_time *tm) bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f); /* assume 20YY not 19YY */ buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100); +} + +#ifdef CONFIG_DM_RTC +static int m41t62_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + int ret; + + ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); + if (ret) + return ret; + + m41t62_update_rtc_time(tm, buf); + + return 0; +} + +static int m41t62_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + int ret; + + ret = dm_i2c_read(dev, 0, buf, sizeof(buf)); + if (ret) + return ret; + + m41t62_set_rtc_buf(tm, buf); + + ret = dm_i2c_write(dev, 0, buf, sizeof(buf)); + if (ret) { + printf("I2C write failed in %s()\n", __func__); + return ret; + } + + return 0; +} + +static int m41t62_rtc_reset(struct udevice *dev) +{ + u8 val; + + /* + * M41T82: Make sure HT (Halt Update) bit is cleared. + * This bit is 0 in M41T62 so its save to clear it always. + */ + + int ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val)); + + val &= ~M41T80_ALHOUR_HT; + ret |= dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val)); + + return ret; +} + +static const struct rtc_ops m41t62_rtc_ops = { + .get = m41t62_rtc_get, + .set = m41t62_rtc_set, + .reset = m41t62_rtc_reset, +}; + +static const struct udevice_id m41t62_rtc_ids[] = { + { .compatible = "st,m41t62" }, + { .compatible = "microcrystal,rv4162" }, + { } +}; + +U_BOOT_DRIVER(rtc_m41t62) = { + .name = "rtc-m41t62", + .id = UCLASS_RTC, + .of_match = m41t62_rtc_ids, + .ops = &m41t62_rtc_ops, +}; + +#else /* NON DM RTC code - will be removed */ +int rtc_get(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + m41t62_update_rtc_time(tm, buf); + + return 0; +} + +int rtc_set(struct rtc_time *tm) +{ + u8 buf[M41T62_DATETIME_REG_SIZE]; + + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + m41t62_set_rtc_buf(tm, buf); - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) { + if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, + M41T62_DATETIME_REG_SIZE)) { printf("I2C write failed in %s()\n", __func__); return -1; } @@ -128,3 +213,4 @@ void rtc_reset(void) val &= ~M41T80_ALHOUR_HT; i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); } +#endif /* CONFIG_DM_RTC */ diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index c499601f00..09365ba6a1 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -119,7 +119,6 @@ U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); serial_initfunc(atmel_serial_initialize); serial_initfunc(mcf_serial_initialize); serial_initfunc(mpc85xx_serial_initialize); -serial_initfunc(mpc8xx_serial_initialize); serial_initfunc(mxc_serial_initialize); serial_initfunc(ns16550_serial_initialize); serial_initfunc(pl01x_serial_initialize); @@ -173,7 +172,6 @@ void serial_initialize(void) atmel_serial_initialize(); mcf_serial_initialize(); mpc85xx_serial_initialize(); - mpc8xx_serial_initialize(); mxc_serial_initialize(); ns16550_serial_initialize(); pl01x_serial_initialize(); diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c index 292912b7ee..50d6e70f17 100644 --- a/drivers/serial/serial_mpc8xx.c +++ b/drivers/serial/serial_mpc8xx.c @@ -6,6 +6,7 @@ #include <common.h> #include <command.h> +#include <dm.h> #include <serial.h> #include <watchdog.h> #include <asm/cpm_8xx.h> @@ -35,9 +36,9 @@ struct serialbuffer { uchar txbuf; /* tx buffers */ }; -static void serial_setdivisor(cpm8xx_t __iomem *cp) +static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate) { - int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate; + int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate; if (divisor / 16 > 0x1000) { /* bad divisor, assume 50MHz clock and 9600 baud */ @@ -58,7 +59,7 @@ static void serial_setdivisor(cpm8xx_t __iomem *cp) * as serial console interface. */ -static void smc_setbrg(void) +static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cp = &(im->im_cpm); @@ -71,10 +72,12 @@ static void smc_setbrg(void) out_be32(&cp->cp_simode, 0); - serial_setdivisor(cp); + serial_setdivisor(cp, baudrate); + + return 0; } -static int smc_init(void) +static int serial_mpc8xx_probe(struct udevice *dev) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; smc_t __iomem *sp; @@ -139,7 +142,7 @@ static int smc_init(void) out_8(&sp->smc_smce, 0xff); /* Set up the baud rate generator */ - smc_setbrg(); + serial_mpc8xx_setbrg(dev, gd->baudrate); /* Make the first buffer the only buffer. */ setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP); @@ -166,14 +169,14 @@ static int smc_init(void) return 0; } -static void smc_putc(const char c) +static int serial_mpc8xx_putc(struct udevice *dev, const char c) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cpmp = &(im->im_cpm); struct serialbuffer __iomem *rtx; if (c == '\n') - smc_putc('\r'); + serial_mpc8xx_putc(dev, '\r'); rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; @@ -184,15 +187,11 @@ static void smc_putc(const char c) while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY) WATCHDOG_RESET(); -} -static void smc_puts(const char *s) -{ - while (*s) - smc_putc(*s++); + return 0; } -static int smc_getc(void) +static int serial_mpc8xx_getc(struct udevice *dev) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cpmp = &(im->im_cpm); @@ -222,34 +221,37 @@ static int smc_getc(void) return c; } -static int smc_tstc(void) +static int serial_mpc8xx_pending(struct udevice *dev, bool input) { immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cpmp = &(im->im_cpm); struct serialbuffer __iomem *rtx; + if (!input) + return 0; + rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY); } -struct serial_device serial_smc_device = { - .name = "serial_smc", - .start = smc_init, - .stop = NULL, - .setbrg = smc_setbrg, - .getc = smc_getc, - .tstc = smc_tstc, - .putc = smc_putc, - .puts = smc_puts, +static const struct dm_serial_ops serial_mpc8xx_ops = { + .putc = serial_mpc8xx_putc, + .pending = serial_mpc8xx_pending, + .getc = serial_mpc8xx_getc, + .setbrg = serial_mpc8xx_setbrg, }; -__weak struct serial_device *default_serial_console(void) -{ - return &serial_smc_device; -} +static const struct udevice_id serial_mpc8xx_ids[] = { + { .compatible = "fsl,pq1-smc" }, + { } +}; -void mpc8xx_serial_initialize(void) -{ - serial_register(&serial_smc_device); -} +U_BOOT_DRIVER(serial_mpc8xx) = { + .name = "serial_mpc8xx", + .id = UCLASS_SERIAL, + .of_match = serial_mpc8xx_ids, + .probe = serial_mpc8xx_probe, + .ops = &serial_mpc8xx_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c index 285fd4d2cc..b020ce2b9d 100644 --- a/drivers/spi/mpc8xx_spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -17,64 +17,19 @@ */ #include <common.h> +#include <dm.h> #include <mpc8xx.h> +#include <spi.h> + #include <asm/cpm_8xx.h> -#include <linux/ctype.h> -#include <malloc.h> -#include <post.h> -#include <serial.h> - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0xb00 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 -#endif +#include <asm/io.h> #define CPM_SPI_BASE_RX CPM_SPI_BASE #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t)) -/* ------------------- - * Function prototypes - * ------------------- */ -ssize_t spi_xfer(size_t); - -/* ------------------- - * Variables - * ------------------- */ - #define MAX_BUFFER 0x104 -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f(void) +static int mpc8xx_spi_probe(struct udevice *dev) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cp = &immr->im_cpm; @@ -180,117 +135,24 @@ void spi_init_f(void) clrbits_be16(&tbdf->cbd_sc, BD_SC_READY); clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY); - /* Set the bd's rx and tx buffer address pointers */ - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - /* 10 + 11 */ out_8(&cp->cp_spim, 0); /* Mask all SPI events */ out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - return; + return 0; } -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r(void) +static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *)malloc(MAX_BUFFER); - txbuf = (uchar *)malloc(MAX_BUFFER); - - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) - break; - udelay(1000); - } - if (i >= 1000) - printf("*** spi_write: Time out while writing!\n"); - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer(size_t count) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; cbd_t __iomem *tbdf, *rbdf; int tm; + size_t count = (bitlen + 7) / 8; - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); + if (count > MAX_BUFFER) + return -EINVAL; tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; @@ -299,10 +161,12 @@ ssize_t spi_xfer(size_t count) clrbits_be32(&cp->cp_pbdat, 0x0001); /* Setting tx bd status and data length */ + out_be32(&tbdf->cbd_bufaddr, (ulong)dout); out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); out_be16(&tbdf->cbd_datlen, count); /* Setting rx bd status and data length */ + out_be32(&rbdf->cbd_bufaddr, (ulong)din); out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */ @@ -333,3 +197,20 @@ ssize_t spi_xfer(size_t count) return count; } + +static const struct dm_spi_ops mpc8xx_spi_ops = { + .xfer = mpc8xx_spi_xfer, +}; + +static const struct udevice_id mpc8xx_spi_ids[] = { + { .compatible = "fsl,mpc8xx-spi" }, + { } +}; + +U_BOOT_DRIVER(mpc8xx_spi) = { + .name = "mpc8xx_spi", + .id = UCLASS_SPI, + .of_match = mpc8xx_spi_ids, + .ops = &mpc8xx_spi_ops, + .probe = mpc8xx_spi_probe, +}; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 4a9ebb6e26..b6974ad619 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -144,4 +144,11 @@ config WDT_MT7621 Select this to enable Ralink / Mediatek watchdog timer, which can be found on some MediaTek chips. +config WDT_MPC8xx + bool "MPC8xx watchdog timer support" + depends on WDT && MPC8xx + select CONFIG_MPC8xx_WATCHDOG + help + Select this to enable mpc8xx watchdog timer + endmenu diff --git a/drivers/watchdog/mpc8xx_wdt.c b/drivers/watchdog/mpc8xx_wdt.c index ccb06ac425..c24c2a9da6 100644 --- a/drivers/watchdog/mpc8xx_wdt.c +++ b/drivers/watchdog/mpc8xx_wdt.c @@ -4,6 +4,8 @@ */ #include <common.h> +#include <dm.h> +#include <wdt.h> #include <mpc8xx.h> #include <asm/cpm_8xx.h> #include <asm/io.h> @@ -16,3 +18,52 @@ void hw_watchdog_reset(void) out_be16(&immap->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */ } +#ifdef CONFIG_WDT_MPC8xx +static int mpc8xx_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + + out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR); + + if (!(in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE)) + return -EBUSY; + return 0; + +} + +static int mpc8xx_wdt_stop(struct udevice *dev) +{ + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; + + out_be32(&immap->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE); + + if (in_be32(&immap->im_siu_conf.sc_sypcr) & SYPCR_SWE) + return -EBUSY; + return 0; +} + +static int mpc8xx_wdt_reset(struct udevice *dev) +{ + hw_watchdog_reset(); + + return 0; +} + +static const struct wdt_ops mpc8xx_wdt_ops = { + .start = mpc8xx_wdt_start, + .reset = mpc8xx_wdt_reset, + .stop = mpc8xx_wdt_stop, +}; + +static const struct udevice_id mpc8xx_wdt_ids[] = { + { .compatible = "fsl,pq1-wdt" }, + {} +}; + +U_BOOT_DRIVER(wdt_mpc8xx) = { + .name = "wdt_mpc8xx", + .id = UCLASS_WDT, + .of_match = mpc8xx_wdt_ids, + .ops = &mpc8xx_wdt_ops, +}; +#endif /* CONFIG_WDT_MPC8xx */ diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 006b049d09..ccbdc0a335 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -34,15 +34,8 @@ /* FIT support */ #define CONFIG_SYS_BOOTM_LEN SZ_64M -/* UBI Support */ - -/* I2C configuration */ - #ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00080000 -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif + #define NANDARGS \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ @@ -264,10 +257,6 @@ #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_OTG -/* Network. */ -#define CONFIG_PHY_SMSC -#define CONFIG_PHY_ATHEROS - /* NAND support */ #ifdef CONFIG_NAND #define GPMC_NAND_ECC_LP_x8_LAYOUT 1 diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index 385d59e338..9a205edc7c 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -11,7 +11,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_SDRAM_BASE 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_8M +#define CONFIG_SYS_SDRAM_SIZE SZ_16M #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M) diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 94214b135d..3fca28da6b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -110,7 +110,6 @@ * RTC */ #ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_M41T62 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 #endif diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 9997795434..e125a38e7d 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -58,7 +58,6 @@ #define CONFIG_SYS_I2C_MXC /* RTC (actually an RV-4162 but M41T62-compatible) */ -#define CONFIG_RTC_M41T62 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_RTC_BUS_NUM 2 diff --git a/include/configs/x600.h b/include/configs/x600.h index a6835ebbd5..639da8012c 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -75,7 +75,6 @@ #define CONFIG_SYS_I2C_SLAVE 0x02 #define CONFIG_I2C_CHIPADDRESS 0x50 -#define CONFIG_RTC_M41T62 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* FPGA config options */ diff --git a/include/image.h b/include/image.h index f67502e333..83a2d412c9 100644 --- a/include/image.h +++ b/include/image.h @@ -30,6 +30,7 @@ struct fdt_region; #define IMAGE_ENABLE_FIT 1 #define IMAGE_ENABLE_OF_LIBFDT 1 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT 1 #define CONFIG_FIT_ENABLE_SHA256_SUPPORT #define CONFIG_SHA1 #define CONFIG_SHA256 @@ -1101,6 +1102,7 @@ struct image_sign_info { int node_offset; /* Offset of signature node */ const char *name; /* Algorithm name */ struct checksum_algo *checksum; /* Checksum algorithm information */ + struct padding_algo *padding; /* Padding algorithm information */ struct crypto_algo *crypto; /* Crypto algorithm information */ const void *fdt_blob; /* FDT containing public keys */ int required_keynode; /* Node offset of key to use: -1=any */ @@ -1186,6 +1188,13 @@ struct crypto_algo { uint8_t *sig, uint sig_len); }; +struct padding_algo { + const char *name; + int (*verify)(struct image_sign_info *info, + uint8_t *pad, int pad_len, + const uint8_t *hash, int hash_len); +}; + /** * image_get_checksum_algo() - Look up a checksum algorithm * @@ -1203,6 +1212,14 @@ struct checksum_algo *image_get_checksum_algo(const char *full_name); struct crypto_algo *image_get_crypto_algo(const char *full_name); /** + * image_get_padding_algo() - Look up a padding algorithm + * + * @param name Name of padding algorithm + * @return pointer to algorithm information, or NULL if not found + */ +struct padding_algo *image_get_padding_algo(const char *name); + +/** * fit_image_verify_required_sigs() - Verify signatures marked as 'required' * * @fit: FIT to check diff --git a/include/serial.h b/include/serial.h index ec25db6e60..9133d07fd5 100644 --- a/include/serial.h +++ b/include/serial.h @@ -224,7 +224,6 @@ struct serial_dev_priv { void atmel_serial_initialize(void); void mcf_serial_initialize(void); void mpc85xx_serial_initialize(void); -void mpc8xx_serial_initialize(void); void mxc_serial_initialize(void); void ns16550_serial_initialize(void); void pl01x_serial_initialize(void); diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h index 68bcb14c74..2d3024d8b7 100644 --- a/include/u-boot/rsa.h +++ b/include/u-boot/rsa.h @@ -97,6 +97,16 @@ static inline int rsa_add_verify_data(struct image_sign_info *info, int rsa_verify(struct image_sign_info *info, const struct image_region region[], int region_count, uint8_t *sig, uint sig_len); + +int padding_pkcs_15_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len); + +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT +int padding_pss_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len); +#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */ #else static inline int rsa_verify(struct image_sign_info *info, const struct image_region region[], int region_count, @@ -104,8 +114,26 @@ static inline int rsa_verify(struct image_sign_info *info, { return -ENXIO; } + +static inline int padding_pkcs_15_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len) +{ + return -ENXIO; +} + +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT +static inline int padding_pss_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len) +{ + return -ENXIO; +} +#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */ #endif +#define RSA_DEFAULT_PADDING_NAME "pkcs-1.5" + #define RSA2048_BYTES (2048 / 8) #define RSA4096_BYTES (4096 / 8) diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 05ac67b822..fb5e07b56d 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -387,13 +387,16 @@ static void rsa_engine_remove(ENGINE *e) } } -static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, +static int rsa_sign_with_key(RSA *rsa, struct padding_algo *padding_algo, + struct checksum_algo *checksum_algo, const struct image_region region[], int region_count, uint8_t **sigp, uint *sig_size) { EVP_PKEY *key; + EVP_PKEY_CTX *ckey; EVP_MD_CTX *context; - int size, ret = 0; + int ret = 0; + size_t size; uint8_t *sig; int i; @@ -409,7 +412,7 @@ static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, size = EVP_PKEY_size(key); sig = malloc(size); if (!sig) { - fprintf(stderr, "Out of memory for signature (%d bytes)\n", + fprintf(stderr, "Out of memory for signature (%zu bytes)\n", size); ret = -ENOMEM; goto err_alloc; @@ -421,22 +424,43 @@ static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, goto err_create; } EVP_MD_CTX_init(context); - if (!EVP_SignInit(context, checksum_algo->calculate_sign())) { + + ckey = EVP_PKEY_CTX_new(key, NULL); + if (!ckey) { + ret = rsa_err("EVP key context creation failed"); + goto err_create; + } + + if (EVP_DigestSignInit(context, &ckey, + checksum_algo->calculate_sign(), + NULL, key) <= 0) { ret = rsa_err("Signer setup failed"); goto err_sign; } +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT + if (padding_algo && !strcmp(padding_algo->name, "pss")) { + if (EVP_PKEY_CTX_set_rsa_padding(ckey, + RSA_PKCS1_PSS_PADDING) <= 0) { + ret = rsa_err("Signer padding setup failed"); + goto err_sign; + } + } +#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */ + for (i = 0; i < region_count; i++) { - if (!EVP_SignUpdate(context, region[i].data, region[i].size)) { + if (!EVP_DigestSignUpdate(context, region[i].data, + region[i].size)) { ret = rsa_err("Signing data failed"); goto err_sign; } } - if (!EVP_SignFinal(context, sig, sig_size, key)) { + if (!EVP_DigestSignFinal(context, sig, &size)) { ret = rsa_err("Could not obtain signature"); goto err_sign; } + #if OPENSSL_VERSION_NUMBER < 0x10100000L || \ (defined(LIBRESSL_VERSION_NUMBER) && LIBRESSL_VERSION_NUMBER < 0x02070000fL) EVP_MD_CTX_cleanup(context); @@ -446,7 +470,7 @@ static int rsa_sign_with_key(RSA *rsa, struct checksum_algo *checksum_algo, EVP_MD_CTX_destroy(context); EVP_PKEY_free(key); - debug("Got signature: %d bytes, expected %d\n", *sig_size, size); + debug("Got signature: %d bytes, expected %zu\n", *sig_size, size); *sigp = sig; *sig_size = size; @@ -483,7 +507,7 @@ int rsa_sign(struct image_sign_info *info, ret = rsa_get_priv_key(info->keydir, info->keyname, e, &rsa); if (ret) goto err_priv; - ret = rsa_sign_with_key(rsa, info->checksum, region, + ret = rsa_sign_with_key(rsa, info->padding, info->checksum, region, region_count, sigp, sig_len); if (ret) goto err_sign; diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index bc83354378..9734f6d3bd 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -57,31 +57,247 @@ static int rsa_verify_padding(const uint8_t *msg, const int pad_len, return ret; } +int padding_pkcs_15_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len) +{ + struct checksum_algo *checksum = info->checksum; + int ret, pad_len = msg_len - checksum->checksum_len; + + /* Check pkcs1.5 padding bytes. */ + ret = rsa_verify_padding(msg, pad_len, checksum); + if (ret) { + debug("In RSAVerify(): Padding check failed!\n"); + return -EINVAL; + } + + /* Check hash. */ + if (memcmp((uint8_t *)msg + pad_len, hash, msg_len - pad_len)) { + debug("In RSAVerify(): Hash check failed!\n"); + return -EACCES; + } + + return 0; +} + +#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT +static void u32_i2osp(uint32_t val, uint8_t *buf) +{ + buf[0] = (uint8_t)((val >> 24) & 0xff); + buf[1] = (uint8_t)((val >> 16) & 0xff); + buf[2] = (uint8_t)((val >> 8) & 0xff); + buf[3] = (uint8_t)((val >> 0) & 0xff); +} + +/** + * mask_generation_function1() - generate an octet string + * + * Generate an octet string used to check rsa signature. + * It use an input octet string and a hash function. + * + * @checksum: A Hash function + * @seed: Specifies an input variable octet string + * @seed_len: Size of the input octet string + * @output: Specifies the output octet string + * @output_len: Size of the output octet string + * @return 0 if the octet string was correctly generated, others on error + */ +static int mask_generation_function1(struct checksum_algo *checksum, + uint8_t *seed, int seed_len, + uint8_t *output, int output_len) +{ + struct image_region region[2]; + int ret = 0, i, i_output = 0, region_count = 2; + uint32_t counter = 0; + uint8_t buf_counter[4], *tmp; + int hash_len = checksum->checksum_len; + + memset(output, 0, output_len); + + region[0].data = seed; + region[0].size = seed_len; + region[1].data = &buf_counter[0]; + region[1].size = 4; + + tmp = malloc(hash_len); + if (!tmp) { + debug("%s: can't allocate array tmp\n", __func__); + ret = -ENOMEM; + goto out; + } + + while (i_output < output_len) { + u32_i2osp(counter, &buf_counter[0]); + + ret = checksum->calculate(checksum->name, + region, region_count, + tmp); + if (ret < 0) { + debug("%s: Error in checksum calculation\n", __func__); + goto out; + } + + i = 0; + while ((i_output < output_len) && (i < hash_len)) { + output[i_output] = tmp[i]; + i_output++; + i++; + } + + counter++; + } + +out: + free(tmp); + + return ret; +} + +static int compute_hash_prime(struct checksum_algo *checksum, + uint8_t *pad, int pad_len, + uint8_t *hash, int hash_len, + uint8_t *salt, int salt_len, + uint8_t *hprime) +{ + struct image_region region[3]; + int ret, region_count = 3; + + region[0].data = pad; + region[0].size = pad_len; + region[1].data = hash; + region[1].size = hash_len; + region[2].data = salt; + region[2].size = salt_len; + + ret = checksum->calculate(checksum->name, region, region_count, hprime); + if (ret < 0) { + debug("%s: Error in checksum calculation\n", __func__); + goto out; + } + +out: + return ret; +} + +int padding_pss_verify(struct image_sign_info *info, + uint8_t *msg, int msg_len, + const uint8_t *hash, int hash_len) +{ + uint8_t *masked_db = NULL; + int masked_db_len = msg_len - hash_len - 1; + uint8_t *h = NULL, *hprime = NULL; + int h_len = hash_len; + uint8_t *db_mask = NULL; + int db_mask_len = masked_db_len; + uint8_t *db = NULL, *salt = NULL; + int db_len = masked_db_len, salt_len = msg_len - hash_len - 2; + uint8_t pad_zero[8] = { 0 }; + int ret, i, leftmost_bits = 1; + uint8_t leftmost_mask; + struct checksum_algo *checksum = info->checksum; + + /* first, allocate everything */ + masked_db = malloc(masked_db_len); + h = malloc(h_len); + db_mask = malloc(db_mask_len); + db = malloc(db_len); + salt = malloc(salt_len); + hprime = malloc(hash_len); + if (!masked_db || !h || !db_mask || !db || !salt || !hprime) { + printf("%s: can't allocate some buffer\n", __func__); + ret = -ENOMEM; + goto out; + } + + /* step 4: check if the last byte is 0xbc */ + if (msg[msg_len - 1] != 0xbc) { + printf("%s: invalid pss padding (0xbc is missing)\n", __func__); + ret = -EINVAL; + goto out; + } + + /* step 5 */ + memcpy(masked_db, msg, masked_db_len); + memcpy(h, msg + masked_db_len, h_len); + + /* step 6 */ + leftmost_mask = (0xff >> (8 - leftmost_bits)) << (8 - leftmost_bits); + if (masked_db[0] & leftmost_mask) { + printf("%s: invalid pss padding ", __func__); + printf("(leftmost bit of maskedDB not zero)\n"); + ret = -EINVAL; + goto out; + } + + /* step 7 */ + mask_generation_function1(checksum, h, h_len, db_mask, db_mask_len); + + /* step 8 */ + for (i = 0; i < db_len; i++) + db[i] = masked_db[i] ^ db_mask[i]; + + /* step 9 */ + db[0] &= 0xff >> leftmost_bits; + + /* step 10 */ + if (db[0] != 0x01) { + printf("%s: invalid pss padding ", __func__); + printf("(leftmost byte of db isn't 0x01)\n"); + ret = EINVAL; + goto out; + } + + /* step 11 */ + memcpy(salt, &db[1], salt_len); + + /* step 12 & 13 */ + compute_hash_prime(checksum, pad_zero, 8, + (uint8_t *)hash, hash_len, + salt, salt_len, hprime); + + /* step 14 */ + ret = memcmp(h, hprime, hash_len); + +out: + free(hprime); + free(salt); + free(db); + free(db_mask); + free(h); + free(masked_db); + + return ret; +} +#endif + /** * rsa_verify_key() - Verify a signature against some data using RSA Key * * Verify a RSA PKCS1.5 signature against an expected hash using * the RSA Key properties in prop structure. * + * @info: Specifies key and FIT information * @prop: Specifies key * @sig: Signature * @sig_len: Number of bytes in signature * @hash: Pointer to the expected hash * @key_len: Number of bytes in rsa key - * @algo: Checksum algo structure having information on DER encoding etc. * @return 0 if verified, -ve on error */ -static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, +static int rsa_verify_key(struct image_sign_info *info, + struct key_prop *prop, const uint8_t *sig, const uint32_t sig_len, const uint8_t *hash, - const uint32_t key_len, struct checksum_algo *algo) + const uint32_t key_len) { - int pad_len; int ret; #if !defined(USE_HOSTCC) struct udevice *mod_exp_dev; #endif + struct checksum_algo *checksum = info->checksum; + struct padding_algo *padding = info->padding; + int hash_len = checksum->checksum_len; - if (!prop || !sig || !hash || !algo) + if (!prop || !sig || !hash || !checksum) return -EIO; if (sig_len != (prop->num_bits / 8)) { @@ -89,7 +305,7 @@ static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, return -EINVAL; } - debug("Checksum algorithm: %s", algo->name); + debug("Checksum algorithm: %s", checksum->name); /* Sanity check for stack size */ if (sig_len > RSA_MAX_SIG_BITS / 8) { @@ -116,19 +332,10 @@ static int rsa_verify_key(struct key_prop *prop, const uint8_t *sig, return ret; } - pad_len = key_len - algo->checksum_len; - - /* Check pkcs1.5 padding bytes. */ - ret = rsa_verify_padding(buf, pad_len, algo); + ret = padding->verify(info, buf, key_len, hash, hash_len); if (ret) { - debug("In RSAVerify(): Padding check failed!\n"); - return -EINVAL; - } - - /* Check hash. */ - if (memcmp((uint8_t *)buf + pad_len, hash, sig_len - pad_len)) { - debug("In RSAVerify(): Hash check failed!\n"); - return -EACCES; + debug("In RSAVerify(): padding check failed!\n"); + return ret; } return 0; @@ -182,8 +389,8 @@ static int rsa_verify_with_keynode(struct image_sign_info *info, return -EFAULT; } - ret = rsa_verify_key(&prop, sig, sig_len, hash, - info->crypto->key_len, info->checksum); + ret = rsa_verify_key(info, &prop, sig, sig_len, hash, + info->crypto->key_len); return ret; } diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b3f525fc02..bd14fe22c6 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1661,7 +1661,6 @@ CONFIG_RTC_DS3231 CONFIG_RTC_FTRTC010 CONFIG_RTC_IMXDI CONFIG_RTC_M41T11 -CONFIG_RTC_M41T62 CONFIG_RTC_MC13XXX CONFIG_RTC_MCFRRTC CONFIG_RTC_MCP79411 diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py index 92144d4c1e..4627ceb026 100644 --- a/test/py/tests/test_vboot.py +++ b/test/py/tests/test_vboot.py @@ -126,7 +126,7 @@ def test_vboot(u_boot_console): handle.write(struct.pack(">I", size)) return struct.unpack(">I", total_size)[0] - def test_with_algo(sha_algo): + def test_with_algo(sha_algo, padding): """Test verified boot with the given hash algorithm. This is the main part of the test code. The same procedure is followed @@ -144,7 +144,7 @@ def test_vboot(u_boot_console): # Build the FIT, but don't sign anything yet cons.log.action('%s: Test FIT with signed images' % sha_algo) - make_fit('sign-images-%s.its' % sha_algo) + make_fit('sign-images-%s%s.its' % (sha_algo , padding)) run_bootm(sha_algo, 'unsigned images', 'dev-', True) # Sign images with our dev keys @@ -155,7 +155,7 @@ def test_vboot(u_boot_console): dtc('sandbox-u-boot.dts') cons.log.action('%s: Test FIT with signed configuration' % sha_algo) - make_fit('sign-configs-%s.its' % sha_algo) + make_fit('sign-configs-%s%s.its' % (sha_algo , padding)) run_bootm(sha_algo, 'unsigned config', '%s+ OK' % sha_algo, True) # Sign images with our dev keys @@ -204,7 +204,7 @@ def test_vboot(u_boot_console): fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign' dtc_args = '-I dts -O dtb -i %s' % tmpdir dtb = '%ssandbox-u-boot.dtb' % tmpdir - sig_node = '/configurations/conf@1/signature@1' + sig_node = '/configurations/conf-1/signature' # Create an RSA key pair public_exponent = 65537 @@ -226,8 +226,10 @@ def test_vboot(u_boot_console): # afterwards. old_dtb = cons.config.dtb cons.config.dtb = dtb - test_with_algo('sha1') - test_with_algo('sha256') + test_with_algo('sha1','') + test_with_algo('sha1','-pss') + test_with_algo('sha256','') + test_with_algo('sha256','-pss') finally: # Go back to the original U-Boot with the correct dtb. cons.config.dtb = old_dtb diff --git a/test/py/tests/vboot/sign-configs-sha1-pss.its b/test/py/tests/vboot/sign-configs-sha1-pss.its new file mode 100644 index 0000000000..72a5637e3a --- /dev/null +++ b/test/py/tests/vboot/sign-configs-sha1-pss.its @@ -0,0 +1,46 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + hash-1 { + algo = "sha1"; + }; + }; + fdt-1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + hash-1 { + algo = "sha1"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + signature { + algo = "sha1,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + sign-images = "fdt", "kernel"; + }; + }; + }; +}; diff --git a/test/py/tests/vboot/sign-configs-sha1.its b/test/py/tests/vboot/sign-configs-sha1.its index db2ed79355..d8bc1fa091 100644 --- a/test/py/tests/vboot/sign-configs-sha1.its +++ b/test/py/tests/vboot/sign-configs-sha1.its @@ -5,7 +5,7 @@ #address-cells = <1>; images { - kernel@1 { + kernel { data = /incbin/("test-kernel.bin"); type = "kernel_noload"; arch = "sandbox"; @@ -14,28 +14,28 @@ load = <0x4>; entry = <0x8>; kernel-version = <1>; - hash@1 { + hash-1 { algo = "sha1"; }; }; - fdt@1 { + fdt-1 { description = "snow"; data = /incbin/("sandbox-kernel.dtb"); type = "flat_dt"; arch = "sandbox"; compression = "none"; fdt-version = <1>; - hash@1 { + hash-1 { algo = "sha1"; }; }; }; configurations { - default = "conf@1"; - conf@1 { - kernel = "kernel@1"; - fdt = "fdt@1"; - signature@1 { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + signature { algo = "sha1,rsa2048"; key-name-hint = "dev"; sign-images = "fdt", "kernel"; diff --git a/test/py/tests/vboot/sign-configs-sha256-pss.its b/test/py/tests/vboot/sign-configs-sha256-pss.its new file mode 100644 index 0000000000..7bdcc7e286 --- /dev/null +++ b/test/py/tests/vboot/sign-configs-sha256-pss.its @@ -0,0 +1,46 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + hash-1 { + algo = "sha256"; + }; + }; + fdt-1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + hash-1 { + algo = "sha256"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + signature { + algo = "sha256,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + sign-images = "fdt", "kernel"; + }; + }; + }; +}; diff --git a/test/py/tests/vboot/sign-configs-sha256.its b/test/py/tests/vboot/sign-configs-sha256.its index 1b3432ec14..f5591aad30 100644 --- a/test/py/tests/vboot/sign-configs-sha256.its +++ b/test/py/tests/vboot/sign-configs-sha256.its @@ -5,7 +5,7 @@ #address-cells = <1>; images { - kernel@1 { + kernel { data = /incbin/("test-kernel.bin"); type = "kernel_noload"; arch = "sandbox"; @@ -14,28 +14,28 @@ load = <0x4>; entry = <0x8>; kernel-version = <1>; - hash@1 { + hash-1 { algo = "sha256"; }; }; - fdt@1 { + fdt-1 { description = "snow"; data = /incbin/("sandbox-kernel.dtb"); type = "flat_dt"; arch = "sandbox"; compression = "none"; fdt-version = <1>; - hash@1 { + hash-1 { algo = "sha256"; }; }; }; configurations { - default = "conf@1"; - conf@1 { - kernel = "kernel@1"; - fdt = "fdt@1"; - signature@1 { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + signature { algo = "sha256,rsa2048"; key-name-hint = "dev"; sign-images = "fdt", "kernel"; diff --git a/test/py/tests/vboot/sign-images-sha1-pss.its b/test/py/tests/vboot/sign-images-sha1-pss.its new file mode 100644 index 0000000000..ded7ae4f55 --- /dev/null +++ b/test/py/tests/vboot/sign-images-sha1-pss.its @@ -0,0 +1,44 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + signature { + algo = "sha1,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + }; + }; + fdt-1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + signature { + algo = "sha1,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + }; + }; +}; diff --git a/test/py/tests/vboot/sign-images-sha1.its b/test/py/tests/vboot/sign-images-sha1.its index f69326a39b..18c759e9e6 100644 --- a/test/py/tests/vboot/sign-images-sha1.its +++ b/test/py/tests/vboot/sign-images-sha1.its @@ -5,7 +5,7 @@ #address-cells = <1>; images { - kernel@1 { + kernel { data = /incbin/("test-kernel.bin"); type = "kernel_noload"; arch = "sandbox"; @@ -14,29 +14,29 @@ load = <0x4>; entry = <0x8>; kernel-version = <1>; - signature@1 { + signature { algo = "sha1,rsa2048"; key-name-hint = "dev"; }; }; - fdt@1 { + fdt-1 { description = "snow"; data = /incbin/("sandbox-kernel.dtb"); type = "flat_dt"; arch = "sandbox"; compression = "none"; fdt-version = <1>; - signature@1 { + signature { algo = "sha1,rsa2048"; key-name-hint = "dev"; }; }; }; configurations { - default = "conf@1"; - conf@1 { - kernel = "kernel@1"; - fdt = "fdt@1"; + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; }; }; }; diff --git a/test/py/tests/vboot/sign-images-sha256-pss.its b/test/py/tests/vboot/sign-images-sha256-pss.its new file mode 100644 index 0000000000..34850cc6c5 --- /dev/null +++ b/test/py/tests/vboot/sign-images-sha256-pss.its @@ -0,0 +1,44 @@ +/dts-v1/; + +/ { + description = "Chrome OS kernel image with one or more FDT blobs"; + #address-cells = <1>; + + images { + kernel { + data = /incbin/("test-kernel.bin"); + type = "kernel_noload"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x4>; + entry = <0x8>; + kernel-version = <1>; + signature { + algo = "sha256,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + }; + }; + fdt-1 { + description = "snow"; + data = /incbin/("sandbox-kernel.dtb"); + type = "flat_dt"; + arch = "sandbox"; + compression = "none"; + fdt-version = <1>; + signature { + algo = "sha256,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + }; + }; + }; + configurations { + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; + }; + }; +}; diff --git a/test/py/tests/vboot/sign-images-sha256.its b/test/py/tests/vboot/sign-images-sha256.its index e6aa9fc409..bb0f8ee8a6 100644 --- a/test/py/tests/vboot/sign-images-sha256.its +++ b/test/py/tests/vboot/sign-images-sha256.its @@ -5,7 +5,7 @@ #address-cells = <1>; images { - kernel@1 { + kernel { data = /incbin/("test-kernel.bin"); type = "kernel_noload"; arch = "sandbox"; @@ -14,29 +14,29 @@ load = <0x4>; entry = <0x8>; kernel-version = <1>; - signature@1 { + signature { algo = "sha256,rsa2048"; key-name-hint = "dev"; }; }; - fdt@1 { + fdt-1 { description = "snow"; data = /incbin/("sandbox-kernel.dtb"); type = "flat_dt"; arch = "sandbox"; compression = "none"; fdt-version = <1>; - signature@1 { + signature { algo = "sha256,rsa2048"; key-name-hint = "dev"; }; }; }; configurations { - default = "conf@1"; - conf@1 { - kernel = "kernel@1"; - fdt = "fdt@1"; + default = "conf-1"; + conf-1 { + kernel = "kernel"; + fdt = "fdt-1"; }; }; }; diff --git a/tools/image-host.c b/tools/image-host.c index 09e4f47e5a..88b329502c 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -157,6 +157,7 @@ static int fit_image_setup_sig(struct image_sign_info *info, { const char *node_name; char *algo_name; + const char *padding_name; node_name = fit_get_name(fit, noffset, NULL); if (fit_image_hash_get_algo(fit, noffset, &algo_name)) { @@ -165,6 +166,8 @@ static int fit_image_setup_sig(struct image_sign_info *info, return -1; } + padding_name = fdt_getprop(fit, noffset, "padding", NULL); + memset(info, '\0', sizeof(*info)); info->keydir = keydir; info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL); @@ -173,6 +176,7 @@ static int fit_image_setup_sig(struct image_sign_info *info, info->name = strdup(algo_name); info->checksum = image_get_checksum_algo(algo_name); info->crypto = image_get_crypto_algo(algo_name); + info->padding = image_get_padding_algo(padding_name); info->require_keys = require_keys; info->engine_id = engine_id; if (!info->checksum || !info->crypto) { |