diff options
89 files changed, 718 insertions, 211 deletions
@@ -60,6 +60,14 @@ usage() exit ${ret} } +deprecation() { + echo "** Note: MAKEALL is deprecated - please use buildman instead" + echo "** See tools/buildman/README for details" + echo +} + +deprecation + SHORT_OPTS="ha:c:v:s:b:lmMCnr" LONG_OPTS="help,arch:,cpu:,vendor:,soc:,board:,list,maintainers,mails,check,continue,rebuild-errors" @@ -827,6 +835,8 @@ print_stats() { kill_children fi + deprecation + exit $RC } @@ -1,7 +1,7 @@ VERSION = 2015 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = NAME = # *DOCUMENTATION* @@ -565,6 +565,7 @@ KBUILD_CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' endif KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector) +KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks) KBUILD_CFLAGS += -g # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format> diff --git a/arch/Kconfig b/arch/Kconfig index 96db5c5088..afa1d6c2d7 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -18,7 +18,7 @@ config ARC config ARM bool "ARM architecture" - select HAVE_PRIVATE_LIBGCC + select HAVE_PRIVATE_LIBGCC if !ARM64 select HAVE_GENERIC_BOARD select SUPPORT_OF_CONTROL diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0d2a808fe2..506463c12c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -592,10 +592,6 @@ config TARGET_TBS2910 bool "Support tbs2910" select CPU_V7 -config TARGET_TQMA6 - bool "TQ Systems TQMa6 board" - select CPU_V7 - config TARGET_OT1200 bool "Bachmann OT1200" select CPU_V7 @@ -979,7 +975,6 @@ source "board/ti/ti816x/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/toradex/colibri_vf/Kconfig" -source "board/tqc/tqma6/Kconfig" source "board/trizepsiv/Kconfig" source "board/ttcontrol/vision2/Kconfig" source "board/udoo/Kconfig" diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 1282be3418..10908c4c4a 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -33,11 +33,16 @@ config TARGET_SECOMX6 bool "Support secomx6 boards" select CPU_V7 +config TARGET_TQMA6 + bool "TQ Systems TQMa6 board" + select CPU_V7 + endchoice config SYS_SOC default "mx6" source "board/seco/Kconfig" +source "board/tqc/tqma6/Kconfig" endif diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index b21bd03a8a..29de6243dc 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -62,6 +62,7 @@ u32 get_cpu_rev(void) struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 reg = readl(&anatop->digprog_sololite); u32 type = ((reg >> 16) & 0xff); + u32 major; if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); @@ -79,8 +80,9 @@ u32 get_cpu_rev(void) } } + major = ((reg >> 8) & 0xff); reg &= 0xff; /* mx6 silicon revision */ - return (type << 12) | (reg + 0x10); + return (type << 12) | (reg + (0x10 * (major + 1))); } /* diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5ed0f45a26..1c7e6f01f9 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -22,10 +22,9 @@ * * Startup Code (reset vector) * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack + * Do important init only if we don't start from memory! + * Setup memory and board specific bits prior to relocation. + * Relocate armboot to ram. Setup stack. * *************************************************************************/ diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 03443629bc..5f39aa07cf 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -45,11 +45,11 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); #endif #if defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); #else - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); #endif sunxi_gpio_set_pull(SUNXI_GPF(4), 1); #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) @@ -64,6 +64,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c index f115a9cac4..6fd11f1529 100644 --- a/arch/arm/cpu/armv7/sunxi/rsb.c +++ b/arch/arm/cpu/armv7/sunxi/rsb.c @@ -60,11 +60,12 @@ int rsb_init(void) struct sunxi_rsb_reg * const rsb = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - rsb_cfg_io(); - /* Enable RSB and PIO clk, and de-assert their resets */ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); + /* Setup external pins */ + rsb_cfg_io(); + writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); rsb_set_clk(); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c735c672a..19e1de67a0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -128,7 +128,8 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-sinlinx-sina33.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index faea94e45e..7abd0ae314 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -366,6 +366,16 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "mmc2"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + i2c0_pins_a: i2c0@0 { allwinner,pins = "PH2", "PH3"; allwinner,function = "i2c0"; diff --git a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts index 97771495c2..97771495c2 100644 --- a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts +++ b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts new file mode 100644 index 0000000000..5788c29cb5 --- /dev/null +++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts @@ -0,0 +1,129 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Sinlinx SinA33"; + compatible = "sinlinx,sina33", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <191011>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <391304>; + }; + + button@600 { + label = "Home"; + linux,code = <KEY_HOME>; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v0>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* eMMC is missing pull-ups */ + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&pio { + mmc0_cd_pin_sina33: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi index 9b43bc6e79..85ee08098b 100644 --- a/arch/arm/dts/sun8i-a33.dtsi +++ b/arch/arm/dts/sun8i-a33.dtsi @@ -86,4 +86,12 @@ compatible = "allwinner,sun8i-a33-pinctrl"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + + uart0_pins_b: uart0@1 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index e522990453..c12556addf 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -44,8 +44,8 @@ static inline int gpt_has_clk_source_osc(void) { #if defined(CONFIG_MX6) if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && - (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX)) + (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) || + is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX)) return 1; return 0; diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f664..5f0e1e6346 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@ #define ARCH_MXC +#define CONFIG_SYS_CACHELINE_SIZE 64 + #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 0d38d450da..35a324cd53 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -312,6 +312,7 @@ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_5 0x15 +#define CHIP_REV_2_0 0x20 #ifndef CONFIG_MX6SX #define IRAM_SIZE 0x00040000 #else diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index c5832912b4..28c77a498e 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -12,7 +12,7 @@ #include "../arch-imx/cpu.h" #define soc_rev() (get_cpu_rev() & 0xFF) -#define is_soc_rev(rev) (soc_rev() - rev) +#define is_soc_rev(rev) (soc_rev() == rev) u32 get_nr_cpus(void); u32 get_cpu_rev(void); @@ -20,7 +20,7 @@ u32 get_cpu_speed_grade_hz(void); u32 get_cpu_temp_grade(int *minc, int *maxc); /* returns MXC_CPU_ value */ -#define cpu_type(rev) (((rev) >> 12)&0xff) +#define cpu_type(rev) (((rev) >> 12) & 0xff) /* both macros return/take MXC_CPU_ constants */ #define get_cpu_type() (cpu_type(get_cpu_rev())) @@ -30,6 +30,10 @@ const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); void set_chipselect_size(int const); +#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_2_0)) + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 496295d357..8e67b3bcb8 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -156,6 +156,7 @@ enum sunxi_gpio_number { #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 +#define SUN8I_A33_GPB_UART0 3 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index ae4c21bf36..43cc494683 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -49,8 +49,4 @@ typedef struct bd_info { #define IH_ARCH_DEFAULT IH_ARCH_ARM64 #endif -#if defined(CONFIG_USE_PRIVATE_LIBGCC) && defined(CONFIG_SYS_THUMB_BUILD) -#error Thumb build does not work with private libgcc. -#endif - #endif /* _U_BOOT_H_ */ diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/_ashldi3.S index 2c26f84ac7..9c34c212cb 100644 --- a/arch/arm/lib/_ashldi3.S +++ b/arch/arm/lib/_ashldi3.S @@ -4,6 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/linkage.h> + #ifdef __ARMEB__ #define al r1 #define ah r0 @@ -13,9 +15,8 @@ #endif .globl __ashldi3 -.globl __aeabi_llsl __ashldi3: -__aeabi_llsl: +ENTRY(__aeabi_llsl) subs r3, r2, #32 rsb ip, r2, #32 @@ -24,3 +25,4 @@ __aeabi_llsl: orrmi ah, ah, al, lsr ip mov al, al, lsl r2 mov pc, lr +ENDPROC(__aeabi_llsl) diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/_ashrdi3.S index 4d93c8a5e6..c74fd64499 100644 --- a/arch/arm/lib/_ashrdi3.S +++ b/arch/arm/lib/_ashrdi3.S @@ -4,6 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/linkage.h> + #ifdef __ARMEB__ #define al r1 #define ah r0 @@ -13,9 +15,8 @@ #endif .globl __ashrdi3 -.globl __aeabi_lasr __ashrdi3: -__aeabi_lasr: +ENTRY(__aeabi_lasr) subs r3, r2, #32 rsb ip, r2, #32 @@ -24,3 +25,4 @@ __aeabi_lasr: orrmi al, al, ah, lsl ip mov ah, ah, asr r2 mov pc, lr +ENDPROC(__aeabi_lasr) diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S index 601549304e..c463c68f85 100644 --- a/arch/arm/lib/_divsi3.S +++ b/arch/arm/lib/_divsi3.S @@ -1,3 +1,5 @@ +#include <linux/linkage.h> + .macro ARM_DIV_BODY dividend, divisor, result, curbit #if __LINUX_ARM_ARCH__ >= 5 @@ -95,9 +97,8 @@ .align 5 .globl __divsi3 -.globl __aeabi_idiv __divsi3: -__aeabi_idiv: +ENTRY(__aeabi_idiv) cmp r1, #0 eor ip, r0, r1 @ save the sign of the result. beq Ldiv0 @@ -139,3 +140,4 @@ Ldiv0: bl __div0 mov r0, #0 @ About as wrong as it could be. ldr pc, [sp], #4 +ENDPROC(__aeabi_idiv) diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/_lshrdi3.S index 33296a0a93..1f9b916464 100644 --- a/arch/arm/lib/_lshrdi3.S +++ b/arch/arm/lib/_lshrdi3.S @@ -4,6 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/linkage.h> + #ifdef __ARMEB__ #define al r1 #define ah r0 @@ -13,9 +15,8 @@ #endif .globl __lshrdi3 -.globl __aeabi_llsr __lshrdi3: -__aeabi_llsr: +ENTRY(__aeabi_llsr) subs r3, r2, #32 rsb ip, r2, #32 @@ -24,3 +25,4 @@ __aeabi_llsr: orrmi al, al, ah, lsl ip mov ah, ah, lsr r2 mov pc, lr +ENDPROC(__aeabi_llsr) diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S index 3d31a559f8..c5e1c229df 100644 --- a/arch/arm/lib/_modsi3.S +++ b/arch/arm/lib/_modsi3.S @@ -1,3 +1,5 @@ +#include <linux/linkage.h> + .macro ARM_MOD_BODY dividend, divisor, order, spare #if __LINUX_ARM_ARCH__ >= 5 @@ -69,8 +71,7 @@ .endm .align 5 -.globl __modsi3 -__modsi3: +ENTRY(__modsi3) cmp r1, #0 beq Ldiv0 rsbmi r1, r1, #0 @ loops below use unsigned. @@ -88,7 +89,7 @@ __modsi3: 10: cmp ip, #0 rsbmi r0, r0, #0 mov pc, lr - +ENDPROC(__modsi3) Ldiv0: diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/_udivsi3.S index 1309802610..3b653bed99 100644 --- a/arch/arm/lib/_udivsi3.S +++ b/arch/arm/lib/_udivsi3.S @@ -1,3 +1,5 @@ +#include <linux/linkage.h> + /* # 1 "libgcc1.S" */ @ libgcc1 routines for ARM cpu. @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) @@ -72,8 +74,7 @@ Ldiv0: ldmia sp!, {pc} .size __udivsi3 , . - __udivsi3 -.globl __aeabi_uidivmod -__aeabi_uidivmod: +ENTRY(__aeabi_uidivmod) stmfd sp!, {r0, r1, ip, lr} bl __aeabi_uidiv @@ -81,9 +82,9 @@ __aeabi_uidivmod: mul r3, r0, r2 sub r1, r1, r3 mov pc, lr +ENDPROC(__aeabi_uidivmod) -.globl __aeabi_idivmod -__aeabi_idivmod: +ENTRY(__aeabi_idivmod) stmfd sp!, {r0, r1, ip, lr} bl __aeabi_idiv @@ -91,3 +92,4 @@ __aeabi_idivmod: mul r3, r0, r2 sub r1, r1, r3 mov pc, lr +ENDPROC(__aeabi_idivmod) diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/_umodsi3.S index 8465ef09d2..b1667376c5 100644 --- a/arch/arm/lib/_umodsi3.S +++ b/arch/arm/lib/_umodsi3.S @@ -1,3 +1,5 @@ +#include <linux/linkage.h> + /* # 1 "libgcc1.S" */ @ libgcc1 routines for ARM cpu. @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) @@ -11,10 +13,9 @@ curbit .req r3 /* lr .req r14 */ /* pc .req r15 */ .text - .globl __umodsi3 .type __umodsi3 ,function .align 0 - __umodsi3 : + ENTRY(__umodsi3) cmp divisor, #0 beq Ldiv0 mov curbit, #1 @@ -86,3 +87,4 @@ Ldiv0: /* # 456 "libgcc1.S" */ /* # 500 "libgcc1.S" */ /* # 580 "libgcc1.S" */ +ENDPROC(__umodsi3) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 0121db8bb5..9bc9f002d8 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -6,10 +6,13 @@ #include <common.h> #include <netdev.h> +#include <ahci.h> +#include <linux/mbus.h> #include <asm/io.h> #include <asm/pl310.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> +#include <sdhci.h> #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) @@ -245,6 +248,69 @@ int cpu_eth_init(bd_t *bis) } #endif +#ifdef CONFIG_MV_SDHCI +int board_mmc_init(bd_t *bis) +{ + mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, + SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD); + + return 0; +} +#endif + +#ifdef CONFIG_SCSI_AHCI_PLAT +#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 +#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 + +#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4)) +#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) +#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) + +static void ahci_mvebu_mbus_config(void __iomem *base) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + for (i = 0; i < 4; i++) { + writel(0, base + AHCI_WINDOW_CTRL(i)); + writel(0, base + AHCI_WINDOW_BASE(i)); + writel(0, base + AHCI_WINDOW_SIZE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + writel((cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + base + AHCI_WINDOW_CTRL(i)); + writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i)); + writel(((cs->size - 1) & 0xffff0000), + base + AHCI_WINDOW_SIZE(i)); + } +} + +static void ahci_mvebu_regret_option(void __iomem *base) +{ + /* + * Enable the regret bit to allow the SATA unit to regret a + * request that didn't receive an acknowlegde and avoid a + * deadlock + */ + writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR); + writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); +} + +void scsi_init(void) +{ + printf("MVEBU SATA INIT\n"); + ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); + ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); + ahci_init((void __iomem *)MVEBU_SATA0_BASE); +} +#endif + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 3b48460a0b..4bdb6331e1 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -114,6 +114,8 @@ void mvebu_sdram_size_adjust(enum memory_bank bank); int mvebu_mbus_probe(struct mbus_win windows[], int count); int mvebu_soc_family(void); +int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); + /* * Highspeed SERDES PHY config init, ported from bin_hdr * to mainline U-Boot diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h new file mode 100644 index 0000000000..09e3c503dd --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/gpio.h @@ -0,0 +1,10 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_MVEBU_GPIO_H +#define __MACH_MVEBU_GPIO_H + +/* Empty file - sdhci requires this. */ + +#endif diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 0a9307c8ce..1aaea672ee 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -49,8 +49,11 @@ #define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) #define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) +#define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) +#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) +#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) #define SDRAM_MAX_CS 4 #define SDRAM_ADDR_MASK 0xFF000000 diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 75ec380980..af2adc701e 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -18,7 +18,7 @@ static inline void mips_cache(int op, const volatile void *addr) #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE __builtin_mips_cache(op, addr); #else - __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr)) + __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr)); #endif } diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 3fa37f5dd2..a7ab087c0d 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -117,7 +117,7 @@ static inline void set_io_port_base(unsigned long base) * Change virtual addresses to physical addresses and vv. * These are trivial on the 1:1 Linux/MIPS mapping */ -extern inline phys_addr_t virt_to_phys(volatile void * address) +static inline phys_addr_t virt_to_phys(volatile void * address) { #ifndef CONFIG_64BIT return CPHYSADDR(address); @@ -126,7 +126,7 @@ extern inline phys_addr_t virt_to_phys(volatile void * address) #endif } -extern inline void * phys_to_virt(unsigned long address) +static inline void * phys_to_virt(unsigned long address) { #ifndef CONFIG_64BIT return (void *)KSEG0ADDR(address); @@ -138,7 +138,7 @@ extern inline void * phys_to_virt(unsigned long address) /* * IO bus memory addresses are also 1:1 with the physical address */ -extern inline unsigned long virt_to_bus(volatile void * address) +static inline unsigned long virt_to_bus(volatile void * address) { #ifndef CONFIG_64BIT return CPHYSADDR(address); @@ -147,7 +147,7 @@ extern inline unsigned long virt_to_bus(volatile void * address) #endif } -extern inline void * bus_to_virt(unsigned long address) +static inline void * bus_to_virt(unsigned long address) { #ifndef CONFIG_64BIT return (void *)KSEG0ADDR(address); @@ -165,12 +165,12 @@ extern unsigned long isa_slot_offset; extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); #if 0 -extern inline void *ioremap(unsigned long offset, unsigned long size) +static inline void *ioremap(unsigned long offset, unsigned long size) { return __ioremap(offset, size, _CACHE_UNCACHED); } -extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) +static inline void *ioremap_nocache(unsigned long offset, unsigned long size) { return __ioremap(offset, size, _CACHE_UNCACHED); } diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index 7a2895284e..d56f73b8b8 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -22,7 +22,7 @@ #include <linux/kernel.h> #endif -extern __inline__ void +static __inline__ void __sti(void) { __asm__ __volatile__( @@ -46,7 +46,7 @@ __sti(void) * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs * no nops at all. */ -extern __inline__ void +static __inline__ void __cli(void) { __asm__ __volatile__( @@ -207,7 +207,7 @@ do { \ * For 32 and 64 bit operands we can take advantage of ll and sc. * FIXME: This doesn't work for R3000 machines. */ -extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) +static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) { #ifdef CONFIG_CPU_HAS_LLSC unsigned long dummy; diff --git a/board/Marvell/db-88f6820-gp/MAINTAINERS b/board/Marvell/db-88f6820-gp/MAINTAINERS new file mode 100644 index 0000000000..f5649400ec --- /dev/null +++ b/board/Marvell/db-88f6820-gp/MAINTAINERS @@ -0,0 +1,6 @@ +DB_88F6820_GP BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/Marvell/db-88f6820-gp/ +F: include/configs/db-88f6820-gp.h +F: configs/db-88f6820-gp_defconfig diff --git a/board/quipos/cairo/MAINTAINERS b/board/quipos/cairo/MAINTAINERS new file mode 100644 index 0000000000..01332da5ab --- /dev/null +++ b/board/quipos/cairo/MAINTAINERS @@ -0,0 +1,6 @@ +CAIRO BOARD +M: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> +S: Maintained +F: board/quipos/cairo/ +F: include/configs/omap3_cairo.h +F: configs/cairo_defconfig diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index a26ea689f2..0361657ede 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -14,3 +14,4 @@ M: Przemyslaw Marczak <p.marczak@samsung.com> S: Maintained F: board/samsung/smdk5420/ F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index d15c726a01..9b1ecf0457 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -536,7 +536,7 @@ static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = { .p0_mpdgctrl0 = 0x023C0224, .p0_mpdgctrl1 = 0x02000220, .p1_mpdgctrl0 = 0x02200220, - .p1_mpdgctrl1 = 0x02000220, + .p1_mpdgctrl1 = 0x02040208, .p0_mprddlctl = 0x44444846, .p1_mprddlctl = 0x4042463C, .p0_mpwrdlctl = 0x32343032, @@ -627,7 +627,7 @@ static void spl_dram_init(int width) else if (is_cpu_type(MXC_CPU_MX6Q)) mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g); else if (is_cpu_type(MXC_CPU_MX6DL)) - mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g); + mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g); else if (is_cpu_type(MXC_CPU_MX6SOLO)) mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g); } diff --git a/board/st/stm32f429-discovery/MAINTAINERS b/board/st/stm32f429-discovery/MAINTAINERS index 78b0d28790..641f26a037 100644 --- a/board/st/stm32f429-discovery/MAINTAINERS +++ b/board/st/stm32f429-discovery/MAINTAINERS @@ -1,3 +1,4 @@ +STM32F429-DISCOVERY BOARD M: Kamil Lulko <rev13@wp.pl> S: Maintained F: board/st/stm32f429-discovery/ diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 7a42055559..1f12a646e4 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -162,6 +162,12 @@ M: Siarhei Siamashka <siarhei.siamashka@gmail.com> S: Maintained F: configs/MSI_Primo81_defconfig +SINLINX SINA33 BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Sinlinx_SinA33_defconfig +W: http://linux-sunxi.org/Sinlinx_SinA33 + TZX-Q8-713B7 BOARD M: Paul Kocialkowski <contact@paulk.fr> S: Maintained diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS index d375278bed..3d40b171d2 100644 --- a/board/ti/am43xx/MAINTAINERS +++ b/board/ti/am43xx/MAINTAINERS @@ -5,3 +5,5 @@ F: board/ti/am43xx/ F: include/configs/am43xx_evm.h F: configs/am43xx_evm_defconfig F: configs/am43xx_evm_qspiboot_defconfig +F: configs/am43xx_evm_ethboot_defconfig +F: configs/am43xx_evm_usbhost_boot_defconfig diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h index 09d3650983..23f22a02be 100644 --- a/board/ti/beagle_x15/mux_data.h +++ b/board/ti/beagle_x15/mux_data.h @@ -244,8 +244,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */ {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */ {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */ - {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ - {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */ + {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ + {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */ {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */ {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */ diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index c9301a51c0..ea8ee9fb3a 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -156,30 +156,31 @@ const struct pad_conf_entry early_padconf[] = { #ifdef CONFIG_IODELAY_RECALIBRATION const struct iodelay_cfg_entry iodelay_cfg_array[] = { - {0x6F0, 480, 0}, /* RGMMI0_RXC_IN */ - {0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */ - {0x708, 272, 1116}, /* RGMMI0_RXD0_IN */ - {0x714, 243, 1260}, /* RGMMI0_RXD1_IN */ - {0x720, 0, 1614}, /* RGMMI0_RXD2_IN */ - {0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */ - {0x740, 531, 120}, /* RGMMI0_TXC_OUT */ - {0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */ - {0x758, 7, 120}, /* RGMMI0_TXD0_OUT */ - {0x764, 0, 0}, /* RGMMI0_TXD1_OUT */ - {0x770, 276, 120}, /* RGMMI0_TXD2_OUT */ - {0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */ - {0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */ - {0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */ - {0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ - {0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ - {0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ - {0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ - {0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */ - {0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */ - {0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */ - {0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */ - {0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ - {0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */ + {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */ + {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */ + {0x714, 196, 1522}, /* RGMMI0_RXD1_IN */ + {0x720, 40, 1860}, /* RGMMI0_RXD2_IN */ + {0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */ + {0x740, 0, 220}, /* RGMMI0_TXC_OUT */ + {0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */ + {0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */ + {0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */ + {0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */ + {0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */ + /* These values are for using RGMII1 configuration on VIN2a_x pins. */ + {0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */ + {0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */ + {0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */ + {0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */ + {0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */ + {0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */ + {0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */ + {0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */ + {0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */ + {0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */ + {0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */ + {0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */ }; #endif @@ -358,7 +359,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */ - {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */ {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ @@ -370,7 +371,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */ {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */ {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */ - {WAKEUP0, (M1 | PIN_OUTPUT)}, /* Wakeup0.dcan1_rx */ + {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */ {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */ }; diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig index f8b3d1fd40..b56237d187 100644 --- a/board/tqc/tqma6/Kconfig +++ b/board/tqc/tqma6/Kconfig @@ -12,4 +12,62 @@ config SYS_SOC config SYS_CONFIG_NAME default "tqma6" +choice + prompt "TQMa6 SoC variant" + default TQMA6Q + help + select the TQMa6 module variant. The variants differing in the used + i.MX6 CPU type and DRAM + +config TQMA6Q + bool "TQMa6Q / TQMa6D" + select MX6Q + help + select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM + +config TQMA6S + bool "TQMa6S" + select MX6S + help + select TQMa6S with i.MX6S and 512 MiB DRAM + +endchoice + +choice + prompt "TQMa6 boot configuration" + default TQMA6X_MMC_BOOT + help + Configure boot device. This is also used to implement environment + location. + +config TQMA6X_MMC_BOOT + bool "MMC / SD Boot" + help + Boot from eMMC / SD Card + +config TQMA6X_SPI_BOOT + bool "SPI NOR Boot" + help + Boot from on board SPI NOR flash + +endchoice + +choice + prompt "TQMa6 base board variant" + default MBA6 + help + Select base board for TQMa6 + +config MBA6 + bool "TQMa6 on MBa6 Starterkit" + help + Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card + etc. + +endchoice + +config IMX_CONFIG + default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q + default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S + endif diff --git a/board/vscom/baltos/MAINTAINERS b/board/vscom/baltos/MAINTAINERS new file mode 100644 index 0000000000..e82acfed16 --- /dev/null +++ b/board/vscom/baltos/MAINTAINERS @@ -0,0 +1,6 @@ +BALTOS BOARD +M: Yegor Yefremov <yegorslists@googlemail.com> +S: Maintained +F: board/vscom/baltos/ +F: include/configs/baltos.h +F: configs/am335x_baltos_defconfig diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index 99ca60e2ac..09bc8c682a 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -184,6 +184,8 @@ void am33xx_spl_board_init(void) */ i2c_set_bus_num(1); + printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED); + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { puts("i2c: cannot access TPS65910\n"); return; diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index aaca3e8a2a..31c43195e4 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -368,7 +368,7 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt, { lbaint_t start, blks; uintptr_t buf_addr; - unsigned short smallblks; + unsigned short smallblks = 0; ccb* pccb=(ccb *)&tempccb; device&=0xff; /* Setup device @@ -391,7 +391,7 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt, scsi_setup_read16(pccb, start, blocks); start += blocks; blks -= blocks; - } else + } else #endif if (blks > SCSI_MAX_READ_BLK) { pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK; diff --git a/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig b/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig index 63910c2b18..8e26f37598 100644 --- a/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig +++ b/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig @@ -12,7 +12,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_USB_MUSB_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2-lcd1024x600" +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig new file mode 100644 index 0000000000..e9e62da101 --- /dev/null +++ b/configs/Sinlinx_SinA33_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=15291 +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_DM_ETH=y +CONFIG_DM_SERIAL=y +CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index bf73919c06..8e8a897ef8 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -3,9 +3,9 @@ CONFIG_TARGET_AM335X_BALTOS=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="NAND" -CONFIG_CONS_INDEX=1 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig index 154dc26909..4956078e61 100644 --- a/configs/bf533-stamp_defconfig +++ b/configs/bf533-stamp_defconfig @@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF533_STAMP=y # CONFIG_CMD_SETEXPR is not set CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +# CONFIG_REGEX is not set CONFIG_LIB_RAND=y diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig index 6cb6c6bf31..668f9cb85d 100644 --- a/configs/bf538f-ezkit_defconfig +++ b/configs/bf538f-ezkit_defconfig @@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF538F_EZKIT=y # CONFIG_CMD_SETEXPR is not set CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +# CONFIG_REGEX is not set CONFIG_LIB_RAND=y diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig index 949612d053..49d59dd07d 100644 --- a/configs/cm-bf548_defconfig +++ b/configs/cm-bf548_defconfig @@ -2,4 +2,5 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_CM_BF548=y # CONFIG_CMD_SETEXPR is not set CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +# CONFIG_REGEX is not set CONFIG_LIB_RAND=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index bb14026597..f0e5106e8c 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -3,3 +3,5 @@ CONFIG_TARGET_TBS2910=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index ceb3386ac5..c590354aa8 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_TQMA6=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_MMC_BOOT" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index e413ef4b10..7de3f99528 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_TQMA6=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6q.cfg,MX6Q,MBA6,TQMA6X_SPI_BOOT" +CONFIG_TQMA6X_SPI_BOOT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index 6c37b4f0b1..7bf15d174e 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_TQMA6=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_MMC_BOOT" +CONFIG_TQMA6S=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index af7853ff86..ff38d0b914 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_TQMA6=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,MBA6,TQMA6X_SPI_BOOT" +CONFIG_TQMA6S=y +CONFIG_TQMA6X_SPI_BOOT=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y diff --git a/doc/README.distro b/doc/README.distro index 0308a4c73a..9e4722a86e 100644 --- a/doc/README.distro +++ b/doc/README.distro @@ -28,7 +28,7 @@ decoupling distro install/boot logic from any knowledge of the bootloader. This model assumes that boards will load boot configuration files from a regular storage mechanism (eMMC, SD card, USB Disk, SATA disk, etc.) with -a standard partitioning scheme (MBR, GPT). Boards that cannnot support this +a standard partitioning scheme (MBR, GPT). Boards that cannot support this storage model are outside the scope of this document, and may still need board-specific installer/boot-configuration support in a distro. @@ -37,9 +37,9 @@ that contains U-Boot, and that the user has somehow installed U-Boot to this flash before running the distro installer. Even on boards that do not conform to this aspect of the model, the extent of the board-specific support in the distro installer logic would be to install a board-specific U-Boot package to -the boot partition partition during installation. This distro-supplied U-Boot -can still implement the same features as on any other board, and hence the -distro's boot configuration file generation logic can still be board-agnostic. +the boot partition during installation. This distro-supplied U-Boot can still +implement the same features as on any other board, and hence the distro's boot +configuration file generation logic can still be board-agnostic. Locating Bootable Disks ----------------------- @@ -61,7 +61,7 @@ any other bootloader) will find those boot files and execute them. This is conceptually identical to creating a grub2 configuration file on a desktop PC. -Note that in the absense of any partition that is explicitly marked bootable, +Note that in the absence of any partition that is explicitly marked bootable, U-Boot falls back to searching the first valid partition of a disk for boot configuration files. Other bootloaders are recommended to do the same, since I believe that partition table bootable flags aren't so commonly used outside @@ -238,7 +238,7 @@ kernel_addr_r: The kernel should be located within the first 128M of RAM in order for the kernel CONFIG_AUTO_ZRELADDR option to work, which is likely enabled on any distro kernel. Since the kernel will decompress itself to 0x8000 after the - start of RAM, kernel_addr_rshould not overlap that area, or the kernel will + start of RAM, kernel_addr_r should not overlap that area, or the kernel will have to copy itself somewhere else first before decompression. A size of 16MB for the kernel is likely adequate. diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 4fb846ad37..0d19dd25a3 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -43,13 +43,13 @@ u16 *ataid[AHCI_MAX_PORTS]; #define WAIT_MS_FLUSH 5000 #define WAIT_MS_LINKUP 200 -static inline u32 ahci_port_base(u32 base, u32 port) +static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) { return base + 0x100 + (port * 0x80); } -static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, +static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base, unsigned int port_idx) { base = ahci_port_base(base, port_idx); @@ -61,7 +61,7 @@ static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, #define msleep(a) udelay(a * 1000) -static void ahci_dcache_flush_range(unsigned begin, unsigned len) +static void ahci_dcache_flush_range(unsigned long begin, unsigned long len) { const unsigned long start = begin; const unsigned long end = start + len; @@ -75,7 +75,7 @@ static void ahci_dcache_flush_range(unsigned begin, unsigned len) * controller is invalidated from dcache; next access comes from * physical RAM. */ -static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) +static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len) { const unsigned long start = begin; const unsigned long end = start + len; @@ -94,7 +94,7 @@ static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) AHCI_PORT_PRIV_DMA_SZ); } -static int waiting_for_cmd_completed(volatile u8 *offset, +static int waiting_for_cmd_completed(void __iomem *offset, int timeout_msec, u32 sign) { @@ -111,7 +111,7 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) { u32 tmp; int j = 0; - u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; + void __iomem *port_mmio = probe_ent->port[port].port_mmio; /* * Bring up SATA link. @@ -131,7 +131,7 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) #ifdef CONFIG_SUNXI_AHCI /* The sunxi AHCI controller requires this undocumented setup */ -static void sunxi_dma_init(volatile u8 *port_mmio) +static void sunxi_dma_init(void __iomem *port_mmio) { clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); } @@ -171,10 +171,10 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) u16 tmp16; unsigned short vendor; #endif - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + void __iomem *mmio = probe_ent->mmio_base; u32 tmp, cap_save, cmd; int i, j, ret; - volatile u8 *port_mmio; + void __iomem *port_mmio; u32 port_map; debug("ahci_host_init: start\n"); @@ -215,9 +215,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) for (i = 0; i < probe_ent->n_ports; i++) { if (!(port_map & (1 << i))) continue; - probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); + probe_ent->port[i].port_mmio = ahci_port_base(mmio, i); port_mmio = (u8 *) probe_ent->port[i].port_mmio; - ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); + ahci_setup_port(&probe_ent->port[i], mmio, i); /* make sure port is not active */ tmp = readl(port_mmio + PORT_CMD); @@ -299,9 +299,6 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) writel(1 << i, mmio + HOST_IRQ_STAT); - /* set irq mask (enables interrupts) */ - writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); - /* register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); debug("SATA port %d status: 0x%x\n", i, tmp); @@ -329,7 +326,7 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) pci_dev_t pdev = probe_ent->dev; u16 cc; #endif - volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; + void __iomem *mmio = probe_ent->mmio_base; u32 vers, cap, cap2, impl, speed; const char *speed_s; const char *scc_s; @@ -462,7 +459,7 @@ static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) for (i = 0; i < sg_count; i++) { ahci_sg->addr = - cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); + cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); ahci_sg->addr_hi = 0; ahci_sg->flags_size = cpu_to_le32(0x3fffff & (buf_len < MAX_DATA_BYTE_COUNT @@ -480,8 +477,11 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) { pp->cmd_slot->opts = cpu_to_le32(opts); pp->cmd_slot->status = 0; - pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); - pp->cmd_slot->tbl_addr_hi = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); +#ifdef CONFIG_PHYS_64BIT + pp->cmd_slot->tbl_addr_hi = + cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); +#endif } @@ -489,7 +489,7 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) static void ahci_set_feature(u8 port) { struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 cmd_fis_len = 5; /* five dwords */ u8 fis[20]; @@ -514,7 +514,7 @@ static void ahci_set_feature(u8 port) } #endif -static int wait_spinup(volatile u8 *port_mmio) +static int wait_spinup(void __iomem *port_mmio) { ulong start; u32 tf_data; @@ -532,9 +532,9 @@ static int wait_spinup(volatile u8 *port_mmio) static int ahci_port_start(u8 port) { struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 port_status; - u32 mem; + void __iomem *mem; debug("Enter start port: %d\n", port); port_status = readl(port_mmio + PORT_SCR_STAT); @@ -544,15 +544,16 @@ static int ahci_port_start(u8 port) return -1; } - mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); + mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); if (!mem) { free(pp); printf("%s: No mem for table!\n", __func__); return -ENOMEM; } - mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ - memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); + /* Aligned to 2048-bytes */ + mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ); + memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); /* * First item in chunk of DMA memory: 32-slot command table, @@ -560,7 +561,7 @@ static int ahci_port_start(u8 port) */ pp->cmd_slot = (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); - debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); + debug("cmd_slot = %p\n", pp->cmd_slot); mem += (AHCI_CMD_SLOT_SZ + 224); /* @@ -574,13 +575,14 @@ static int ahci_port_start(u8 port) * and its scatter-gather table */ pp->cmd_tbl = virt_to_phys((void *)mem); - debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl); mem += AHCI_CMD_TBL_HDR; pp->cmd_tbl_sg = (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); + writel_with_flush((unsigned long)pp->cmd_slot, + port_mmio + PORT_LST_ADDR); writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); @@ -607,7 +609,7 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, { struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 opts; u32 port_status; int sg_count; @@ -632,7 +634,7 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, ahci_fill_cmd_slot(pp, opts); ahci_dcache_flush_sata_cmd(pp); - ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); + ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len); writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); @@ -642,7 +644,8 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, return -1; } - ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); + ahci_dcache_invalidate_range((unsigned long)buf, + (unsigned long)buf_len); debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); return 0; @@ -1026,7 +1029,7 @@ static int ata_io_flush(u8 port) { u8 fis[20]; struct ahci_ioports *pp = &(probe_ent->port[port]); - volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + void __iomem *port_mmio = pp->port_mmio; u32 cmd_fis_len = 5; /* five dwords */ /* Preset the FIS */ diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index cf3ef6be62..bc072f335f 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -80,7 +80,7 @@ struct sata_host_regs { static int is_ready; -static inline u32 ahci_port_base(u32 base, u32 port) +static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) { return base + 0x100 + (port * 0x80); } @@ -167,7 +167,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) for (i = 0; i < probe_ent->n_ports; i++) { probe_ent->port[i].port_mmio = - ahci_port_base((u32)host_mmio, i); + ahci_port_base(host_mmio, i); port_mmio = (struct sata_port_regs *)probe_ent->port[i].port_mmio; @@ -399,8 +399,11 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); cmd_hdr->opts = cpu_to_le32(opts); cmd_hdr->status = 0; - cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); - cmd_hdr->tbl_addr_hi = 0; + pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); +#ifdef CONFIG_PHYS_64BIT + pp->cmd_slot->tbl_addr_hi = + cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); +#endif } #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) @@ -520,7 +523,7 @@ static int ahci_port_start(struct ahci_probe_ent *probe_ent, * and its scatter-gather table */ pp->cmd_tbl = mem; - debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); + debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); mem += AHCI_CMD_TBL_HDR; diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c index 96b312592b..8a9826e6eb 100644 --- a/drivers/gpio/lpc32xx_gpio.c +++ b/drivers/gpio/lpc32xx_gpio.c @@ -37,7 +37,7 @@ #define LPC32XX_GPIOS 128 -struct lpc32xx_gpio_platdata { +struct lpc32xx_gpio_priv { struct gpio_regs *regs; /* GPIO FUNCTION: SEE WARNING #2 */ signed char function[LPC32XX_GPIOS]; @@ -60,8 +60,8 @@ struct lpc32xx_gpio_platdata { static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset) { int port, mask; - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); - struct gpio_regs *regs = gpio_platdata->regs; + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev); + struct gpio_regs *regs = gpio_priv->regs; port = GPIO_TO_PORT(offset); mask = GPIO_TO_MASK(offset); @@ -83,7 +83,7 @@ static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset) } /* GPIO FUNCTION: SEE WARNING #2 */ - gpio_platdata->function[offset] = GPIOF_INPUT; + gpio_priv->function[offset] = GPIOF_INPUT; return 0; } @@ -95,8 +95,8 @@ static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset) static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset) { int port, rank, mask, value; - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); - struct gpio_regs *regs = gpio_platdata->regs; + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev); + struct gpio_regs *regs = gpio_priv->regs; port = GPIO_TO_PORT(offset); @@ -130,8 +130,8 @@ static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset) static int gpio_set(struct udevice *dev, unsigned gpio) { int port, mask; - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); - struct gpio_regs *regs = gpio_platdata->regs; + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev); + struct gpio_regs *regs = gpio_priv->regs; port = GPIO_TO_PORT(gpio); mask = GPIO_TO_MASK(gpio); @@ -162,8 +162,8 @@ static int gpio_set(struct udevice *dev, unsigned gpio) static int gpio_clr(struct udevice *dev, unsigned gpio) { int port, mask; - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); - struct gpio_regs *regs = gpio_platdata->regs; + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev); + struct gpio_regs *regs = gpio_priv->regs; port = GPIO_TO_PORT(gpio); mask = GPIO_TO_MASK(gpio); @@ -208,8 +208,8 @@ static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset, int value) { int port, mask; - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); - struct gpio_regs *regs = gpio_platdata->regs; + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev); + struct gpio_regs *regs = gpio_priv->regs; port = GPIO_TO_PORT(offset); mask = GPIO_TO_MASK(offset); @@ -231,7 +231,7 @@ static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset, } /* GPIO FUNCTION: SEE WARNING #2 */ - gpio_platdata->function[offset] = GPIOF_OUTPUT; + gpio_priv->function[offset] = GPIOF_OUTPUT; return lpc32xx_gpio_set_value(dev, offset, value); } @@ -251,8 +251,8 @@ static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset, static int lpc32xx_gpio_get_function(struct udevice *dev, unsigned offset) { - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); - return gpio_platdata->function[offset]; + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev); + return gpio_priv->function[offset]; } static const struct dm_gpio_ops gpio_lpc32xx_ops = { @@ -265,7 +265,7 @@ static const struct dm_gpio_ops gpio_lpc32xx_ops = { static int lpc32xx_gpio_probe(struct udevice *dev) { - struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); + struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev); struct gpio_dev_priv *uc_priv = dev->uclass_priv; if (dev->of_offset == -1) { @@ -274,12 +274,11 @@ static int lpc32xx_gpio_probe(struct udevice *dev) } /* set base address for GPIO registers */ - gpio_platdata->regs = (struct gpio_regs *)GPIO_BASE; + gpio_priv->regs = (struct gpio_regs *)GPIO_BASE; /* all GPIO functions are unknown until requested */ /* GPIO FUNCTION: SEE WARNING #2 */ - memset(gpio_platdata->function, GPIOF_UNKNOWN, - sizeof(gpio_platdata->function)); + memset(gpio_priv->function, GPIOF_UNKNOWN, sizeof(gpio_priv->function)); return 0; } @@ -289,5 +288,5 @@ U_BOOT_DRIVER(gpio_lpc32xx) = { .id = UCLASS_GPIO, .ops = &gpio_lpc32xx_ops, .probe = lpc32xx_gpio_probe, - .priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_platdata), + .priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_priv), }; diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index c053e84cdb..9a04e48a0f 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -1035,7 +1035,7 @@ static void process_nodes(const void *blob, int node_list[], int count, CONFIG_SYS_I2C_S3C24X0_SPEED); bus->node = node; bus->bus_num = i; - exynos_pinmux_config(PERIPH_ID_I2C0 + bus->id, flags); + exynos_pinmux_config(bus->id, flags); /* Mark position as used */ node_list[i] = -1; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 75556a332d..d89e302841 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -13,7 +13,11 @@ #include <mmc.h> #include <sdhci.h> +#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) +void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; +#else void *aligned_buffer; +#endif static void sdhci_reset(struct sdhci_host *host, u8 mask) { @@ -133,8 +137,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, int trans_bytes = 0, is_aligned = 1; u32 mask, flags, mode; unsigned int time = 0, start_addr = 0; - unsigned int retry = 10000; int mmc_dev = mmc->block_dev.dev; + unsigned start = get_timer(0); /* Timeout unit - ms */ static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; @@ -205,6 +209,17 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, memcpy(aligned_buffer, data->src, trans_bytes); } +#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) + /* + * Always use this bounce-buffer when + * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined + */ + is_aligned = 0; + start_addr = (unsigned long)aligned_buffer; + if (data->flags != MMC_DATA_READ) + memcpy(aligned_buffer, data->src, trans_bytes); +#endif + sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); mode |= SDHCI_TRNS_DMA; #endif @@ -222,15 +237,15 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, flush_cache(start_addr, trans_bytes); #endif sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); + start = get_timer(0); do { stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) break; - if (--retry == 0) - break; - } while ((stat & mask) != mask); + } while (((stat & mask) != mask) && + (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT)); - if (retry == 0) { + if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) { if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) return 0; else { diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index 7197007d41..c517b9c65d 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -43,7 +43,7 @@ static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size, } int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, - loff_t *maxsize, int devtype, int chipsize) + loff_t *maxsize, int devtype, uint64_t chipsize) { if (!str2off(arg, off)) return get_part(arg, idx, off, size, maxsize, devtype); @@ -59,7 +59,8 @@ int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, } int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, - loff_t *size, loff_t *maxsize, int devtype, int chipsize) + loff_t *size, loff_t *maxsize, int devtype, + uint64_t chipsize) { int ret; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index ae51cf3781..645ca6427c 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -243,6 +243,12 @@ static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) mdelay(100); }; + /* + * Soft reset above clears HW address registers. + * So we have to set it here once again. + */ + _dw_write_hwaddr(priv, enetaddr); + rx_descs_init(priv); tx_descs_init(priv); diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index e77773740f..df7eb05e82 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -61,6 +61,22 @@ #define status_dcc(x) \ __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x)) +#elif defined(CONFIG_CPU_ARMV8) +/* + * ARMV8 + */ +#define DCC_RBIT (1 << 30) +#define DCC_WBIT (1 << 29) + +#define write_dcc(x) \ + __asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x)) + +#define read_dcc(x) \ + __asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x)) + +#define status_dcc(x) \ + __asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x)) + #else #define DCC_RBIT (1 << 0) #define DCC_WBIT (1 << 1) diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 1a5fd6eefc..03c489c014 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <usb.h> #include "ehci.h" +#include <linux/mbus.h> #include <asm/arch/cpu.h> #if defined(CONFIG_KIRKWOOD) @@ -30,6 +31,40 @@ DECLARE_GLOBAL_DATA_PTR; /* * USB 2.0 Bridge Address Decoding registers setup */ +#ifdef CONFIG_ARMADA_XP + +#define MVUSB0_BASE MVEBU_USB20_BASE + +/* + * Once all the older Marvell SoC's (Orion, Kirkwood) are converted + * to the common mvebu archticture including the mbus setup, this + * will be the only function needed to configure the access windows + */ +static void usb_brg_adrdec_setup(void) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + for (i = 0; i < 4; i++) { + wrl(USB_WINDOW_CTRL(i), 0); + wrl(USB_WINDOW_BASE(i), 0); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + /* Write size, attributes and target id to control register */ + wrl(USB_WINDOW_CTRL(i), + ((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1); + + /* Write base address to base register */ + wrl(USB_WINDOW_BASE(i), cs->base); + } +} +#else static void usb_brg_adrdec_setup(void) { int i; @@ -69,6 +104,7 @@ static void usb_brg_adrdec_setup(void) wrl(USB_WINDOW_BASE(i), base); } } +#endif /* * Create the appropriate control structures to manage diff --git a/include/ahci.h b/include/ahci.h index 6d917121c6..0bdedac187 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -135,12 +135,12 @@ struct ahci_sg { }; struct ahci_ioports { - u32 cmd_addr; - u32 scr_addr; - u32 port_mmio; + void __iomem *cmd_addr; + void __iomem *scr_addr; + void __iomem *port_mmio; struct ahci_cmd_hdr *cmd_slot; struct ahci_sg *cmd_tbl_sg; - u32 cmd_tbl; + ulong cmd_tbl; u32 rx_fis; }; diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 2f4117db29..6a0240b903 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -19,6 +19,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index e5b462174e..b90a60db0f 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -19,6 +19,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_454179 #define CONFIG_ARM_ERRATA_430973 diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 68bfee5e8c..cce5e4f285 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -16,6 +16,7 @@ #ifndef __CONFIG_BALTOS_H #define __CONFIG_BALTOS_H +#include <linux/sizes.h> #include <configs/ti_am335x_common.h> #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ @@ -39,8 +40,7 @@ #define CONFIG_CMD_PART /* FIT support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ +#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_OF_BOARD_SETUP /* UBI Support */ @@ -54,10 +54,11 @@ /* I2C configuration */ #undef CONFIG_SYS_OMAP24_I2C_SPEED -#define CONFIG_SYS_OMAP24_I2C_SPEED 10000 +#define CONFIG_SYS_OMAP24_I2C_SPEED 1000 +#undef CONFIG_SPL_OS_BOOT #ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00080000 #ifdef CONFIG_SPL_OS_BOOT #define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ @@ -80,7 +81,9 @@ "ubifsmount ubi0:kernel; " \ "ubifsload $loadaddr kernel-fit.itb;" \ "ubifsumount; " \ - "bootm ${loadaddr}#conf${board_name}\0" + "bootm ${loadaddr}#conf${board_name}; " \ + "if test $? -ne 0; then echo Using default FIT config; " \ + "bootm ${loadaddr}; fi;\0" #else #define NANDARGS "" #endif @@ -236,6 +239,7 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_GPMC_PREFETCH #define CONFIG_NAND_OMAP_ELM #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ @@ -278,9 +282,9 @@ #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_MUSB_HOST #define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB0_MODE MUSB_HOST #define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST +#define CONFIG_AM335X_USB1_MODE MUSB_OTG #ifdef CONFIG_MUSB_HOST #define CONFIG_CMD_USB diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index aff2810a05..f2f8e2ee4d 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -179,7 +179,7 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_PROMPT "Colibri VFxx # " #undef CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 24dbf6bf71..a429107a9a 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -29,12 +29,19 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC #define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC #define CONFIG_CMD_PING +#define CONFIG_CMD_SCSI #define CONFIG_CMD_SF #define CONFIG_CMD_SPI #define CONFIG_CMD_TFTPPUT #define CONFIG_CMD_TIME +#define CONFIG_CMD_USB /* I2C */ #define CONFIG_SYS_I2C @@ -48,6 +55,40 @@ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 #define CONFIG_SPI_FLASH_STMICRO +/* + * SDIO/MMC Card Configuration + */ +#define CONFIG_MMC +#define CONFIG_MMC_SDMA +#define CONFIG_GENERIC_MMC +#define CONFIG_SDHCI +#define CONFIG_MV_SDHCI +#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* Partition support */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* Additional FS support/configuration */ +#define CONFIG_SUPPORT_VFAT + +/* USB/EHCI configuration */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_MARVELL +#define CONFIG_EHCI_IS_TDI + /* Environment in SPI NOR flash */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index d83e07e242..a28ceb7064 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -20,7 +20,7 @@ #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ "addr_mon=0x0c140000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ "name_fdt=uImage-k2e-evm.dtb\0" \ "name_mon=skern-k2e-evm.bin\0" \ "name_ubi=k2e-evm-ubifs.ubi\0" \ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index ffddf1391c..eae7721783 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -20,7 +20,7 @@ #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ "addr_mon=0x0c5f0000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ "name_fdt=uImage-k2hk-evm.dtb\0" \ "name_mon=skern-k2hk-evm.bin\0" \ "name_ubi=k2hk-evm-ubifs.ubi\0" \ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 805164a679..57da057925 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -20,7 +20,7 @@ #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ "addr_mon=0x0c140000\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0" \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0" \ "name_fdt=uImage-k2l-evm.dtb\0" \ "name_mon=skern-k2l-evm.bin\0" \ "name_ubi=k2l-evm-ubifs.ubi\0" \ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 2ef3201de1..86d7b16777 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -86,7 +86,7 @@ #define CONFIG_CMD_FAT /* Miscellaneous configurable options */ -#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER #define CONFIG_CMDLINE_EDITING diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 3f99512bce..3d5bba75d3 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -186,14 +186,6 @@ "fi; " \ "else run netboot; fi" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_CMDLINE_EDITING - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR diff --git a/include/configs/novena.h b/include/configs/novena.h index 1dc9d83c2c..d9b7250cad 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -24,6 +24,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C +#define CONFIG_FAT_WRITE #define CONFIG_CMD_FUSE #define CONFIG_CMD_MII #define CONFIG_CMD_PCI diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 0f325944b5..e5fd147f0d 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -480,7 +480,7 @@ /* * Variant 2 partition layout - * chip-size = 256MiB + * chip-size = 256MiB or 512 MiB *| name | size | address area | *------------------------------------------------------- *| spl | 128.000 KiB | 0x 0..0x 1ffff | @@ -490,23 +490,23 @@ *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | *| uboot.env0 | 512.000 KiB | 0x 260000..0x 2Dffff | *| uboot.env1 | 512.000 KiB | 0x 2E0000..0x 35ffff | - *| rootfs | 148.000 MiB | 0x 360000..0x 975ffff | - *| mtdoops | 512.000 KiB | 0x 9760000..0x 98Dffff | - *|configuration | 104.125 MiB | 0x 97E0000..0x fffffff | + *| mtdoops | 512.000 KiB | 0x 360000..0x 3dffff | + *| (256) rootfs | 252.125 MiB | 0x 3E0000..0x fffffff | + *| (512) rootfs | 508.125 MiB | 0x 3E0000..0x1fffffff | *------------------------------------------------------- */ #define MTDPARTS_DEFAULT_V2 "mtdparts=" MTDIDS_NAME_STR ":" \ - "128k(spl)," \ - "128k(spl.backup1)," \ - "128k(spl.backup2)," \ - "128k(spl.backup3)," \ - "1920k(u-boot)," \ - "512k(u-boot.env0)," \ - "512k(u-boot.env1)," \ - "148m(rootfs)," \ - "512k(mtdoops)," \ - "-(configuration)" + "128k(spl)," \ + "128k(spl.backup1)," \ + "128k(spl.backup2)," \ + "128k(spl.backup3)," \ + "1920k(u-boot)," \ + "512k(u-boot.env0)," \ + "512k(u-boot.env1)," \ + "512k(mtdoops)," \ + "-(rootfs)" + #define DFU_ALT_INFO_NAND_V2 \ "spl part 0 1;" \ @@ -516,8 +516,7 @@ "u-boot part 0 5;" \ "u-boot.env0 part 0 6;" \ "u-boot.env1 part 0 7;" \ - "rootfs partubi 0 8;" \ - "configuration partubi 0 10" + "rootfs partubi 0 9" \ #define CONFIG_ENV_SETTINGS_NAND_V2 \ "nand_active_ubi_vol=rootfs_a\0" \ @@ -534,7 +533,7 @@ "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ "fi;" \ "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ - "ubi.mtd=7,2048 ubi.mtd=9,2048;" \ + "ubi.mtd=rootfs,2048;" \ "setenv bootargs ${bootargs} " \ "root=${nand_root} noinitrd ${mtdparts} " \ "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 46869dd47f..1b4fd213cf 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -52,10 +52,10 @@ #define CONFIG_STM32_SERIAL /* * Configuration of the USART - * 1: TX:PA9 PX:PA10 + * 1: TX:PA9 RX:PA10 * 2: TX:PD5 RX:PD6 * 3: TX:PC10 RX:PC11 - * 6: TX:PC6 RX:PC7 + * 6: TX:PG14 RX:PG9 */ #define CONFIG_STM32_USART 1 diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index e1c993783b..42e5821807 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -21,6 +21,8 @@ #define CONFIG_SYS_PROMPT "Matrix U-Boot> " #define CONFIG_SYS_HZ 1000 +#define CONFIG_IMX6_THERMAL + /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR @@ -49,6 +51,10 @@ #define CONFIG_CONSOLE_MUX #define CONFIG_CONS_INDEX 1 +#define CONFIG_PRE_CONSOLE_BUFFER +#define CONFIG_PRE_CON_BUF_SZ 4096 +#define CONFIG_PRE_CON_BUF_ADDR 0x7C000000 + /* *** Command definition *** */ #define CONFIG_CMD_BMODE #define CONFIG_CMD_MEMTEST diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 78a8e399c6..e0c4ada711 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -9,6 +9,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <linux/kconfig.h> /* SPL */ /* #if defined(CONFIG_SPL_BUILD) */ diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index edbd250809..1dd7636a69 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h @@ -3,6 +3,8 @@ * * Copyright (C) 2009 Nokia * Copyright (C) 2009-2010 Texas Instruments + * + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _DT_BINDINGS_PINCTRL_OMAP_H diff --git a/include/env_callback.h b/include/env_callback.h index ab5d42dd81..90b95b5e66 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -33,8 +33,10 @@ #ifdef CONFIG_REGEX #define ENV_DOT_ESCAPE "\\" +#define ETHADDR_WILDCARD "\\d?" #else #define ENV_DOT_ESCAPE +#define ETHADDR_WILDCARD #endif #ifdef CONFIG_CMD_DNS @@ -53,7 +55,7 @@ "nvlan:nvlan," \ "vlan:vlan," \ DNS_CALLBACK \ - "eth\\d?addr:ethaddr," + "eth" ETHADDR_WILDCARD "addr:ethaddr," #else #define NET_CALLBACKS #endif diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 33669da4ed..552d4d623f 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -484,8 +484,9 @@ int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); int del_mtd_partitions(struct mtd_info *); int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, - loff_t *maxsize, int devtype, int chipsize); + loff_t *maxsize, int devtype, uint64_t chipsize); int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, - loff_t *size, loff_t *maxsize, int devtype, int chipsize); + loff_t *size, loff_t *maxsize, int devtype, + uint64_t chipsize); #endif #endif /* __MTD_MTD_H__ */ diff --git a/lib/Kconfig b/lib/Kconfig index 7ec8c98da2..c98d3997b7 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -38,6 +38,7 @@ config SYS_VSNPRINTF config REGEX bool "Enable regular expression support" + default y if NET help If this variable is defined, U-Boot is linked against the SLRE (Super Light Regular Expression) library, which adds diff --git a/net/Kconfig b/net/Kconfig index 9a9846e187..915371df91 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -4,7 +4,6 @@ menuconfig NET bool "Networking support" - select REGEX if NET |