diff options
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/display.h | 12 | ||||
| -rw-r--r-- | drivers/video/sunxi_display.c | 11 |
3 files changed, 27 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index a7e25f46c8..b397809da2 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -287,6 +287,11 @@ struct sunxi_ccm_reg { #define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) #define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) #define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) +#ifdef CONFIG_MACH_SUN5I +#define CCM_LCD_CH0_CTRL_TVE_RST (0x1 << 29) +#else +#define CCM_LCD_CH0_CTRL_TVE_RST 0 /* No separate tve-rst on sun4i/7i */ +#endif #define CCM_LCD_CH0_CTRL_RST (0x1 << 30) #define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 2cc3916a01..b64f310b8b 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -196,7 +196,9 @@ struct sunxi_lcdc_reg { u8 res3[0x44]; /* 0xac */ u32 tcon1_io_polarity; /* 0xf0 */ u32 tcon1_io_tristate; /* 0xf4 */ - u8 res4[0x128]; /* 0xf8 */ + u8 res4[0x108]; /* 0xf8 */ + u32 mux_ctrl; /* 0x200 */ + u8 res5[0x1c]; /* 0x204 */ u32 lvds_ana0; /* 0x220 */ u32 lvds_ana1; /* 0x224 */ }; @@ -385,6 +387,10 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) +#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) +#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) +#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) +#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) #ifdef CONFIG_SUNXI_GEN_SUN6I #define SUNXI_LCDC_LVDS_ANA0 0x40040320 #define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) @@ -506,7 +512,11 @@ struct sunxi_tve_reg { #define SUNXI_TVE_CFG0_PAL 0x07030001 #define SUNXI_TVE_CFG0_NTSC 0x07030000 #define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7 +#ifdef CONFIG_MACH_SUN5I +#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009 +#else #define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008 +#endif #define SUNXI_TVE_FILTER_COMPOSITE 0x00000120 #define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3 #define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446 diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 7c1ea8f2f6..f5deca35ab 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -485,7 +485,9 @@ static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode, setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE); if (mode->vmode == FB_VMODE_INTERLACED) setbits_le32(&de_be->mode, +#ifndef CONFIG_MACH_SUN5I SUNXI_DE_BE_MODE_DEFLICKER_ENABLE | +#endif SUNXI_DE_BE_MODE_INTERLACE_ENABLE); if (sunxi_is_composite()) { @@ -874,6 +876,13 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode, SUNXI_LCDC_TCON_VSYNC_MASK | SUNXI_LCDC_TCON_HSYNC_MASK); } + +#ifdef CONFIG_MACH_SUN5I + if (sunxi_is_composite()) + clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK, + SUNXI_LCDC_MUX_CTRL_SRC0(1)); +#endif + sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double); } #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */ @@ -999,6 +1008,8 @@ static void sunxi_tvencoder_mode_set(void) struct sunxi_tve_reg * const tve = (struct sunxi_tve_reg *)SUNXI_TVE0_BASE; + /* Reset off */ + setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST); /* Clock on */ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0); |