diff options
57 files changed, 1468 insertions, 201 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 44eeefa635..9f653a0137 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -55,7 +55,9 @@ Maintainers List (try to look for most precise areas first) ----------------------------------- ARC M: Alexey Brodkin <alexey.brodkin@synopsys.com> +M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> S: Maintained +L: uboot-snps-arc@synopsys.com T: git git://git.denx.de/u-boot-arc.git F: arch/arc/ diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c index 435fe96ef4..822318ff43 100644 --- a/arch/arc/lib/init_helpers.c +++ b/arch/arc/lib/init_helpers.c @@ -7,8 +7,6 @@ #include <asm/cache.h> #include <common.h> -DECLARE_GLOBAL_DATA_PTR; - int init_cache_f_r(void) { sync_n_cleanup_cache_all(); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 62fbf32a62..ac7667b1e8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -193,6 +193,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ + socfpga_stratix10_socdk.dtb \ socfpga_cyclone5_vining_fpga.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ diff --git a/arch/arm/dts/r8a7791-koelsch-u-boot.dts b/arch/arm/dts/r8a7791-koelsch-u-boot.dts index 9de45bb52d..58e15a4044 100644 --- a/arch/arm/dts/r8a7791-koelsch-u-boot.dts +++ b/arch/arm/dts/r8a7791-koelsch-u-boot.dts @@ -8,3 +8,7 @@ #include "r8a7791-koelsch.dts" #include "r8a7791-u-boot.dtsi" + +&scif0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index f7dc147317..31df1f62aa 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -1525,6 +1525,14 @@ dma-channels = <2>; }; + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a7795", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7795"; reg = <0 0xee100000 0 0x2000>; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index 83faabe040..7cb14bb65f 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -1350,6 +1350,14 @@ status = "disabled"; }; + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a7796", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7796"; reg = <0 0xee100000 0 0x2000>; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index 7eb4e65ea4..3630b52a92 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -748,6 +748,14 @@ status = "disabled"; }; + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77965", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a77965"; reg = <0 0xee100000 0 0x2000>; diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts index cb76c89b57..c051cddb25 100644 --- a/arch/arm/dts/r8a77970-eagle.dts +++ b/arch/arm/dts/r8a77970-eagle.dts @@ -17,6 +17,7 @@ aliases { serial0 = &scif0; ethernet0 = &avb; + spi0 = &rpc; }; chosen { @@ -59,6 +60,25 @@ }; }; +&rpc { + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi index 78e6f89e30..42c5c72bf2 100644 --- a/arch/arm/dts/r8a77970.dtsi +++ b/arch/arm/dts/r8a77970.dtsi @@ -381,5 +381,13 @@ #address-cells = <1>; #size-cells = <0>; }; + + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77970", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi index d1a03cf811..733b6afc89 100644 --- a/arch/arm/dts/r8a77995.dtsi +++ b/arch/arm/dts/r8a77995.dtsi @@ -400,5 +400,13 @@ #phy-cells = <0>; status = "disabled"; }; + + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77995", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 7557aa01e5..ead0560f47 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -14,6 +14,10 @@ aliases { ethernet0 = &gmac0; ethernet1 = &gmac1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; serial0 = &uart0; serial1 = &uart1; timer0 = &timer0; @@ -505,6 +509,8 @@ compatible = "snps,designware-i2c"; reg = <0xffc04000 0x1000>; clocks = <&l4_sp_clk>; + resets = <&rst I2C0_RESET>; + reset-names = "i2c"; interrupts = <0 158 0x4>; status = "disabled"; }; @@ -515,6 +521,8 @@ compatible = "snps,designware-i2c"; reg = <0xffc05000 0x1000>; clocks = <&l4_sp_clk>; + resets = <&rst I2C1_RESET>; + reset-names = "i2c"; interrupts = <0 159 0x4>; status = "disabled"; }; @@ -525,6 +533,8 @@ compatible = "snps,designware-i2c"; reg = <0xffc06000 0x1000>; clocks = <&l4_sp_clk>; + resets = <&rst I2C2_RESET>; + reset-names = "i2c"; interrupts = <0 160 0x4>; status = "disabled"; }; @@ -535,6 +545,8 @@ compatible = "snps,designware-i2c"; reg = <0xffc07000 0x1000>; clocks = <&l4_sp_clk>; + resets = <&rst I2C3_RESET>; + reset-names = "i2c"; interrupts = <0 161 0x4>; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts index dc09bed901..5e7fe2aa5f 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -56,6 +56,18 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + + dxl345: adxl345@0 { + compatible = "adi,adxl345"; + reg = <0x53>; + + interrupt-parent = <&portc>; + interrupts = <3 2>; + }; +}; + &mmc0 { status = "okay"; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi new file mode 100644 index 0000000000..ddf8032b60 --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -0,0 +1,381 @@ +/* + * Copyright (C) 2018 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "altr,socfpga-stratix10"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 120 8>, + <0 121 8>, + <0 122 8>, + <0 123 8>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + interrupt-parent = <&intc>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: intc@fffc1000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0xfffc1000 0x0 0x1000>, + <0x0 0xfffc2000 0x0 0x2000>, + <0x0 0xfffc4000 0x0 0x2000>, + <0x0 0xfffc6000 0x0 0x2000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + + clkmgr@ffd1000 { + compatible = "altr,clk-mgr"; + reg = <0xffd10000 0x1000>; + }; + + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff800000 0x2000>; + interrupts = <0 90 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@ff802000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff802000 0x2000>; + interrupts = <0 91 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gmac2: ethernet@ff804000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff804000 0x2000>; + interrupts = <0 92 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gpio0: gpio@ffc03200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03200 0x100>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 110 4>; + }; + }; + + gpio1: gpio@ffc03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03300 0x100>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 111 4>; + }; + }; + + i2c0: i2c@ffc02800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02800 0x100>; + interrupts = <0 103 4>; + resets = <&rst I2C0_RESET>; + status = "disabled"; + }; + + i2c1: i2c@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02900 0x100>; + interrupts = <0 104 4>; + resets = <&rst I2C1_RESET>; + status = "disabled"; + }; + + i2c2: i2c@ffc02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02a00 0x100>; + interrupts = <0 105 4>; + resets = <&rst I2C2_RESET>; + status = "disabled"; + }; + + i2c3: i2c@ffc02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02b00 0x100>; + interrupts = <0 106 4>; + resets = <&rst I2C3_RESET>; + status = "disabled"; + }; + + i2c4: i2c@ffc02c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02c00 0x100>; + interrupts = <0 107 4>; + resets = <&rst I2C4_RESET>; + status = "disabled"; + }; + + mmc: dwmmc0@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + interrupts = <0 96 4>; + fifo-depth = <0x400>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; + status = "disabled"; + }; + + ocram: sram@ffe00000 { + compatible = "mmio-sram"; + reg = <0xffe00000 0x100000>; + }; + + rst: rstmgr@ffd11000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd11000 0x1000>; + altr,modrst-offset = <0x20>; + }; + + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x1000>; + interrupts = <0 99 4>; + resets = <&rst SPIM0_RESET>; + reg-io-width = <4>; + num-chipselect = <4>; + bus-num = <0>; + status = "disabled"; + }; + + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x1000>; + interrupts = <0 100 4>; + resets = <&rst SPIM1_RESET>; + reg-io-width = <4>; + num-chipselect = <4>; + bus-num = <0>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd12000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd12000 0x1000>; + }; + + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + timer0: timer0@ffc03000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 113 4>; + reg = <0xffc03000 0x100>; + }; + + timer1: timer1@ffc03100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 114 4>; + reg = <0xffc03100 0x100>; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 4>; + reg = <0xffd00000 0x100>; + }; + + timer3: timer3@ffd00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 4>; + reg = <0xffd00100 0x100>; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x100>; + interrupts = <0 108 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + }; + + uart1: serial1@ffc02100 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02100 0x100>; + interrupts = <0 109 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + status = "disabled"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0x40000>; + interrupts = <0 93 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0x40000>; + interrupts = <0 94 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd00200 { + compatible = "snps,dw-wdt"; + reg = <0xffd00200 0x100>; + interrupts = <0 117 4>; + resets = <&rst WATCHDOG0_RESET>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd00300 { + compatible = "snps,dw-wdt"; + reg = <0xffd00300 0x100>; + interrupts = <0 118 4>; + resets = <&rst WATCHDOG1_RESET>; + status = "disabled"; + }; + + watchdog2: watchdog@ffd00400 { + compatible = "snps,dw-wdt"; + reg = <0xffd00400 0x100>; + interrupts = <0 125 4>; + resets = <&rst WATCHDOG2_RESET>; + status = "disabled"; + }; + + watchdog3: watchdog@ffd00500 { + compatible = "snps,dw-wdt"; + reg = <0xffd00500 0x100>; + interrupts = <0 126 4>; + resets = <&rst WATCHDOG3_RESET>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts new file mode 100644 index 0000000000..5e5ae62aa8 --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2018 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include "socfpga_stratix10.dtsi" + +/ { + model = "SoCFPGA Stratix 10 SoCDK"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <3800>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index bcadb21ba9..fe123f86ef 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -47,6 +47,9 @@ config TARGET_KOELSCH bool "Koelsch board" select DM select DM_SERIAL + select SUPPORT_SPL + select USE_TINY_PRINTF + select SPL_TINY_MEMSET config TARGET_LAGER bool "Lager board" diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file mode 100644 index 0000000000..7052804921 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ +#define _SOCFPGA_S10_BASE_HARDWARE_H_ + +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 +#define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_SMMU_ADDRESS 0xfa000000 +#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000 +#define GICD_BASE 0xfffc1000 +#define GICC_BASE 0xfffc2000 + +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */ diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile index 15f111c504..77cf067406 100644 --- a/board/renesas/koelsch/Makefile +++ b/board/renesas/koelsch/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := koelsch.o qos.o ../rcar-common/common.o +ifdef CONFIG_SPL_BUILD +obj-y := koelsch_spl.o +else +obj-y := koelsch.o qos.o +endif diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index e7b47ae299..4a4007b7a3 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -48,13 +48,7 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF0_MSTP721 (1 << 21) -#define ETHER_MSTP813 (1 << 13) - -#define SDHI0_MSTP314 (1 << 14) -#define SDHI1_MSTP312 (1 << 12) -#define SDHI2_MSTP311 (1 << 11) +#define TMU0_MSTP125 BIT(25) #define SD1CKCR 0xE6150078 #define SD2CKCR 0xE615026C @@ -64,16 +58,6 @@ int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIF0 */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); - - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - - /* SDHI */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, - SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); - /* * SD0 clock is set to 97.5MHz by default. * Set SD1 and SD2 to the 97.5MHz as well. @@ -84,133 +68,40 @@ int board_early_init_f(void) return 0; } -/* LSI pin pull-up control */ -#define PUPR5 0xe6060114 -#define PUPR5_ETH 0x3FFC0000 -#define PUPR5_ETH_MAGIC (1 << 27) +#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */ + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - /* Init PFC controller */ - r8a7791_pinmux_init(); - - /* ETHER Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REFCLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ0, NULL); - - mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); - gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ - mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); - - gpio_direction_output(GPIO_GP_5_22, 0); - mdelay(20); - gpio_set_value(GPIO_GP_5_22, 1); - udelay(1); + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); + mdelay(10); + gpio_direction_output(ETHERNET_PHY_RESET, 1); return 0; } -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) +int dram_init(void) { -#ifdef CONFIG_SH_ETHER - int ret = -ENODEV; - u32 val; - unsigned char enetaddr[6]; - - ret = sh_eth_initialize(bis); - if (!eth_env_get_enetaddr("ethaddr", enetaddr)) - return ret; - - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); - - return ret; -#else return 0; -#endif } -int board_mmc_init(bd_t *bis) +int dram_init_banksize(void) { - int ret = -ENODEV; - -#ifdef CONFIG_SH_SDHI - gpio_request(GPIO_FN_SD0_DATA0, NULL); - gpio_request(GPIO_FN_SD0_DATA1, NULL); - gpio_request(GPIO_FN_SD0_DATA2, NULL); - gpio_request(GPIO_FN_SD0_DATA3, NULL); - gpio_request(GPIO_FN_SD0_CLK, NULL); - gpio_request(GPIO_FN_SD0_CMD, NULL); - gpio_request(GPIO_FN_SD0_CD, NULL); - gpio_request(GPIO_FN_SD2_DATA0, NULL); - gpio_request(GPIO_FN_SD2_DATA1, NULL); - gpio_request(GPIO_FN_SD2_DATA2, NULL); - gpio_request(GPIO_FN_SD2_DATA3, NULL); - gpio_request(GPIO_FN_SD2_CLK, NULL); - gpio_request(GPIO_FN_SD2_CMD, NULL); - gpio_request(GPIO_FN_SD2_CD, NULL); - - /* SDHI 0 */ - gpio_request(GPIO_GP_7_17, NULL); - gpio_request(GPIO_GP_2_12, NULL); - gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ - gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, - SH_SDHI_QUIRK_16BIT_BUF); - if (ret) - return ret; - - /* SDHI 1 */ - gpio_request(GPIO_GP_7_18, NULL); - gpio_request(GPIO_GP_2_13, NULL); - gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ - gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); - if (ret) - return ret; - - /* SDHI 2 */ - gpio_request(GPIO_GP_7_19, NULL); - gpio_request(GPIO_GP_2_26, NULL); - gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ - gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); -#endif - return ret; -} - -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + fdtdec_setup_memory_banksize(); return 0; } -/* koelsch has KSZ8041NL/RNL */ -#define PHY_CONTROL1 0x1E -#define PHY_LED_MODE 0xC0000 +/* Koelsch has KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 #define PHY_LED_MODE_ACK 0x4000 int board_phy_config(struct phy_device *phydev) { @@ -228,22 +119,38 @@ const struct rmobile_sysinfo sysinfo = { void reset_cpu(ulong addr) { - u8 val; + struct udevice *dev; + const u8 pmic_bus = 6; + const u8 pmic_addr = 0x58; + u8 data; + int ret; + + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); + + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); + + data |= BIT(1); - i2c_set_bus_num(2); /* PowerIC connected to ch2 */ - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); } -static const struct sh_serial_platdata serial_platdata = { - .base = SCIF0_BASE, - .type = PORT_SCIF, - .clk = 14745600, - .clk_mode = EXT_CLK, -}; +enum env_location env_get_location(enum env_operation op, int prio) +{ + const u32 load_magic = 0xb33fc0de; -U_BOOT_DEVICE(koelsch_serials) = { - .name = "serial_sh", - .platdata = &serial_platdata, -}; + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; +} diff --git a/board/renesas/koelsch/koelsch_spl.c b/board/renesas/koelsch/koelsch_spl.c new file mode 100644 index 0000000000..de6c1c0567 --- /dev/null +++ b/board/renesas/koelsch/koelsch_spl.c @@ -0,0 +1,410 @@ +/* + * board/renesas/koelsch/koelsch_spl.c + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#include <spl.h> + +#define TMU0_MSTP125 BIT(25) +#define SCIF0_MSTP721 BIT(21) +#define QSPI_MSTP917 BIT(17) + +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + +struct reg_config { + u16 off; + u32 val; +}; + +static void dbsc_wait(u16 reg) +{ + static const u32 dbsc3_0_base = DBSC3_0_BASE; + static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; + + while (!(readl(dbsc3_0_base + reg) & BIT(0))) + ; + + while (!(readl(dbsc3_1_base + reg) & BIT(0))) + ; +} + +static void spl_init_sys(void) +{ + u32 r0 = 0; + + writel(0xa5a5a500, 0xe6020004); + writel(0xa5a5a500, 0xe6030004); + + asm volatile( + /* ICIALLU - Invalidate I$ to PoU */ + "mcr 15, 0, %0, cr7, cr5, 0 \n" + /* BPIALL - Invalidate branch predictors */ + "mcr 15, 0, %0, cr7, cr5, 6 \n" + /* Set SCTLR[IZ] */ + "mrc 15, 0, %0, cr1, cr0, 0 \n" + "orr %0, #0x1800 \n" + "mcr 15, 0, %0, cr1, cr0, 0 \n" + "isb sy \n" + :"=r"(r0)); +} + +static void spl_init_pfc(void) +{ + static const struct reg_config pfc_with_unlock[] = { + { 0x0090, 0x60000000 }, + { 0x0094, 0x60000000 }, + { 0x0098, 0x00800200 }, + { 0x009c, 0x00000000 }, + { 0x0020, 0x00000000 }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x000244c8 }, + { 0x002c, 0x00000000 }, + { 0x0030, 0x00002400 }, + { 0x0034, 0x01520000 }, + { 0x0038, 0x00724003 }, + { 0x003c, 0x00000000 }, + { 0x0040, 0x00000000 }, + { 0x0044, 0x00000000 }, + { 0x0048, 0x00000000 }, + { 0x004c, 0x00000000 }, + { 0x0050, 0x00000000 }, + { 0x0054, 0x00000000 }, + { 0x0058, 0x00000000 }, + { 0x005c, 0x00000000 }, + { 0x0160, 0x00000000 }, + { 0x0004, 0xffffffff }, + { 0x0008, 0x00ec3fff }, + { 0x000c, 0x3bc001e7 }, + { 0x0010, 0x5bffffff }, + { 0x0014, 0x1ffffffb }, + { 0x0018, 0x01bffff0 }, + { 0x001c, 0xcf7fffff }, + { 0x0074, 0x0381fc00 }, + }; + + static const struct reg_config pfc_without_unlock[] = { + { 0x0100, 0xffffffdf }, + { 0x0104, 0xc883c3ff }, + { 0x0108, 0x1201f3c9 }, + { 0x010c, 0x00000000 }, + { 0x0110, 0xffffeb04 }, + { 0x0114, 0xc003ffff }, + { 0x0118, 0x0800000f }, + { 0x011c, 0x001800f0 }, + }; + + static const u32 pfc_base = 0xe6060000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { + writel(~pfc_with_unlock[i].val, pfc_base); + writel(pfc_with_unlock[i].val, + pfc_base | pfc_with_unlock[i].off); + } + + for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) + writel(pfc_without_unlock[i].val, + pfc_base | pfc_without_unlock[i].off); +} + +static void spl_init_gpio(void) +{ + static const u16 gpio_offs[] = { + 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800 + }; + + static const struct reg_config gpio_set[] = { + { 0x2000, 0x04381000 }, + { 0x5000, 0x00000000 }, + { 0x5800, 0x000e0000 }, + + }; + + static const struct reg_config gpio_clr[] = { + { 0x1000, 0x00000000 }, + { 0x2000, 0x04381010 }, + { 0x3000, 0x00000000 }, + { 0x4000, 0x00000000 }, + { 0x5000, 0x00400000 }, + { 0x5400, 0x00000000 }, + { 0x5800, 0x000e0380 }, + }; + + static const u32 gpio_base = 0xe6050000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x20 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x00 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_set); i++) + writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); + + for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) + writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); +} + +static void spl_init_lbsc(void) +{ + static const struct reg_config lbsc_config[] = { + { 0x00, 0x00000020 }, + { 0x08, 0x00002020 }, + { 0x30, 0x2a103320 }, + { 0x38, 0xff70ff70 }, + }; + + static const u16 lbsc_offs[] = { + 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 + }; + + static const u32 lbsc_base = 0xfec00200; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { + writel(lbsc_config[i].val, + lbsc_base | lbsc_config[i].off); + writel(lbsc_config[i].val, + lbsc_base | (lbsc_config[i].off + 4)); + } + + for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) + writel(0, lbsc_base | lbsc_offs[i]); +} + +static void spl_init_dbsc(void) +{ + static const struct reg_config dbsc_config1[] = { + { 0x0018, 0x21000000 }, + { 0x0018, 0x11000000 }, + { 0x0018, 0x10000000 }, + { 0x0280, 0x0000a55a }, + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf004649b }, + { 0x0020, 0x00000007 }, + { 0x0024, 0x0f030a02 }, + { 0x0030, 0x00000001 }, + { 0x00b0, 0x00000000 }, + { 0x0040, 0x0000000b }, + { 0x0044, 0x00000008 }, + { 0x0048, 0x00000000 }, + { 0x0050, 0x0000000b }, + { 0x0054, 0x000c000b }, + { 0x0058, 0x00000027 }, + { 0x005c, 0x0000001c }, + { 0x0060, 0x00000006 }, + { 0x0064, 0x00000020 }, + { 0x0068, 0x00000008 }, + { 0x006c, 0x0000000c }, + { 0x0070, 0x00000009 }, + { 0x0074, 0x00000012 }, + { 0x0078, 0x000000d0 }, + { 0x007c, 0x00140005 }, + { 0x0080, 0x00050004 }, + { 0x0084, 0x70233005 }, + { 0x0088, 0x000c0000 }, + { 0x008c, 0x00000300 }, + { 0x0090, 0x00000040 }, + { 0x0100, 0x00000001 }, + { 0x00c0, 0x00020001 }, + { 0x00c8, 0x20082008 }, + { 0x0380, 0x00020002 }, + { 0x0390, 0x0000001f }, + }; + + static const struct reg_config dbsc_config5[] = { + { 0x0244, 0x00000011 }, + { 0x0290, 0x00000006 }, + { 0x02a0, 0x0005c000 }, + { 0x0290, 0x00000003 }, + { 0x02a0, 0x0300c481 }, + { 0x0290, 0x00000023 }, + { 0x02a0, 0x00fdb6c0 }, + { 0x0290, 0x00000011 }, + { 0x02a0, 0x1000040b }, + { 0x0290, 0x00000012 }, + { 0x02a0, 0x9d9cbb66 }, + { 0x0290, 0x00000013 }, + { 0x02a0, 0x1a868400 }, + { 0x0290, 0x00000014 }, + { 0x02a0, 0x300214d8 }, + { 0x0290, 0x00000015 }, + { 0x02a0, 0x00000d70 }, + { 0x0290, 0x00000016 }, + { 0x02a0, 0x00000006 }, + { 0x0290, 0x00000017 }, + { 0x02a0, 0x00000018 }, + { 0x0290, 0x0000001a }, + { 0x02a0, 0x910035c7 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config6[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000181 }, + { 0x0018, 0x11000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config7[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x0000fe01 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config8[] = { + { 0x0304, 0x00000000 }, + { 0x00f4, 0x01004c20 }, + { 0x00f8, 0x014000aa }, + { 0x00e0, 0x00000140 }, + { 0x00e4, 0x00081860 }, + { 0x00e8, 0x00010000 }, + { 0x0014, 0x00000001 }, + { 0x0010, 0x00000001 }, + { 0x0280, 0x00000000 }, + }; + + static const u32 dbsc3_0_base = DBSC3_0_BASE; + static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) { + writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); + writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off); + } + + dbsc_wait(0x240); + + for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) { + writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); + writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) { + writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); + writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) { + writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); + writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) { + writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); + writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off); + } + +} + +static void spl_init_qspi(void) +{ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); + + static const u32 qspi_base = 0xe6b10000; + + writeb(0x08, qspi_base + 0x00); + writeb(0x00, qspi_base + 0x01); + writeb(0x06, qspi_base + 0x02); + writeb(0x01, qspi_base + 0x0a); + writeb(0x00, qspi_base + 0x0b); + writeb(0x00, qspi_base + 0x0c); + writeb(0x00, qspi_base + 0x0d); + writeb(0x00, qspi_base + 0x0e); + + writew(0xe080, qspi_base + 0x10); + + writeb(0xc0, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x08); + writeb(0x48, qspi_base + 0x00); +} + +void board_init_f(ulong dummy) +{ + int i; + + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD2CKCR); + + spl_init_sys(); + spl_init_pfc(); + spl_init_gpio(); + spl_init_lbsc(); + + /* Unknown, likely ES1.0-specific delay */ + for (i = 0; i < 100000; i++) + asm volatile("nop"); + + spl_init_dbsc(); + spl_init_qspi(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +void board_boot_order(u32 *spl_boot_list) +{ + const u32 jtag_magic = 0x1337c0de; + const u32 load_magic = 0xb33fc0de; + + /* + * If JTAG probe sets special word at 0xe6300020, then it must + * put U-Boot into RAM and SPL will start it from RAM. + */ + if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { + printf("JTAG boot detected!\n"); + + while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) + ; + + spl_boot_list[0] = BOOT_DEVICE_RAM; + spl_boot_list[1] = BOOT_DEVICE_NONE; + + return; + } + + /* Boot from SPI NOR with YMODEM UART fallback. */ + spl_boot_list[0] = BOOT_DEVICE_SPI; + spl_boot_list[1] = BOOT_DEVICE_UART; + spl_boot_list[2] = BOOT_DEVICE_NONE; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c index acd4f91d59..eb66bc903e 100644 --- a/board/renesas/porter/porter.c +++ b/board/renesas/porter/porter.c @@ -11,6 +11,7 @@ #include <malloc.h> #include <dm.h> #include <dm/platform_data/serial_sh.h> +#include <environment.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -136,3 +137,18 @@ void reset_cpu(ulong addr) if (ret) hang(); } + +enum env_location env_get_location(enum env_operation op, int prio) +{ + const u32 load_magic = 0xb33fc0de; + + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; +} diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c index d7e81292a0..192ee66a38 100644 --- a/board/renesas/stout/stout.c +++ b/board/renesas/stout/stout.c @@ -128,3 +128,18 @@ int board_phy_config(struct phy_device *phydev) const struct rmobile_sysinfo sysinfo = { CONFIG_ARCH_RMOBILE_BOARD_STRING }; + +enum env_location env_get_location(enum env_operation op, int prio) +{ + const u32 load_magic = 0xb33fc0de; + + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; +} diff --git a/common/bootm.c b/common/bootm.c index adb12137c7..36162917a1 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -434,6 +434,8 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, ulong blob_end = os.end; ulong image_start = os.image_start; ulong image_len = os.image_len; + ulong flush_start = ALIGN_DOWN(load, ARCH_DMA_MINALIGN); + ulong flush_len = *load_end - load; bool no_overlap; void *load_buf, *image_buf; int err; @@ -447,7 +449,11 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); return err; } - flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN)); + + if (flush_start < load) + flush_len += load - flush_start; + + flush_cache(flush_start, ALIGN(flush_len, ARCH_DMA_MINALIGN)); debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end); bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED); diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 174b80aeed..25b10888ce 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 9530061568..b9d387b88a 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index 37f61902d3..844decad2d 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -2,7 +2,7 @@ CONFIG_ARC=y CONFIG_ISA_ARCV2=y CONFIG_TARGET_HSDK=y CONFIG_SYS_TEXT_BASE=0x81000000 -CONFIG_SYS_CLK_FREQ=1000000000 +CONFIG_SYS_CLK_FREQ=500000000 CONFIG_DEFAULT_DEVICE_TREE="hsdk" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 1246dde599..8875b59a7f 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -1,17 +1,37 @@ CONFIG_ARM=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0xE6304000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_R8A7791=y CONFIG_TARGET_KOELSCH=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_SDRAM=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -19,21 +39,42 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DM_GPIO=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_RENESAS_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y -CONFIG_NETDEVICES=y +CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -CONFIG_BAUDRATE=38400 +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_RCAR_GEN2=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_PFC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SH_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index 6b5f109870..fdfa41c395 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -6,6 +6,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_SALVATOR_X=y CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index 4b2afb8874..5b15e74d0c 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -6,6 +6,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_ULCB=y CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig index 1bfd91f1c7..986c076d51 100644 --- a/configs/r8a77965_salvator-x_defconfig +++ b/configs/r8a77965_salvator-x_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A7796=y CONFIG_TARGET_SALVATOR_X=y CONFIG_DEFAULT_DEVICE_TREE="r8a77965-salvator-x-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index 3abd82ccd4..fefc719d1d 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A7796=y CONFIG_TARGET_SALVATOR_X=y CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index fedb82f6d5..3fee38d641 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A7796=y CONFIG_TARGET_ULCB=y CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index eb8666abca..f2861924f6 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A77970=y CONFIG_TARGET_EAGLE=y CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" @@ -17,7 +18,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -28,19 +30,21 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_BLK=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y -CONFIG_DM_MMC=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_RENESAS_SDHI=y +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y @@ -52,6 +56,8 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index ce92fbae56..d3cccec8fc 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A77995=y CONFIG_TARGET_DRAAK=y CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index e5984f2bd1..0717a84b68 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 742473f672..0d6d80c51b 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -42,6 +44,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -54,6 +57,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index a68707425d..d85f3d056a 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -42,6 +44,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -55,6 +58,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index e96299641e..faafebf2c5 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -24,6 +24,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -45,12 +47,14 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 93e43d2a07..efb13748b6 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -24,6 +24,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -42,6 +44,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -49,6 +52,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 240216b3e9..08b0b92615 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -38,6 +40,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -45,6 +48,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 1e6eb86005..a2a8a7491b 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -24,6 +24,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -38,6 +40,7 @@ CONFIG_SPL_DM=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -45,6 +48,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 37d28216f3..6d5c27e8ee 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -22,6 +22,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_SF=y @@ -40,6 +42,7 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y @@ -49,5 +52,6 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 12e22939e1..1f8871b6ed 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -24,6 +24,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -42,12 +44,14 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 077d5c9d57..49d9db8df7 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -42,6 +44,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -55,6 +58,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index a4289e348f..b69c982a92 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -43,6 +45,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -55,6 +58,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 05c903a511..062afe16bc 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -25,6 +25,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -44,6 +46,7 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -54,6 +57,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 7ba289faf0..15ac595bae 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -26,6 +26,8 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -71,6 +73,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 6e99b3b15d..53f418bfdd 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -111,8 +111,8 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) bulk->count = 0; count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); - if (!count) - return 0; + if (count < 1) + return count; bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL); if (!bulk->clks) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 8cfed2194c..419d021a31 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -9,6 +9,7 @@ #include <dm.h> #include <i2c.h> #include <pci.h> +#include <reset.h> #include <asm/io.h> #include "designware_i2c.h" @@ -34,6 +35,7 @@ static struct dw_scl_sda_cfg byt_config = { struct dw_i2c { struct i2c_regs *regs; struct dw_scl_sda_cfg *scl_sda_cfg; + struct reset_ctl reset_ctl; }; #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED @@ -534,6 +536,7 @@ static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, static int designware_i2c_probe(struct udevice *bus) { struct dw_i2c *priv = dev_get_priv(bus); + int ret; if (device_is_on_pci_bus(bus)) { #ifdef CONFIG_DM_PCI @@ -549,6 +552,13 @@ static int designware_i2c_probe(struct udevice *bus) priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus); } + ret = reset_get_by_name(bus, "i2c", &priv->reset_ctl); + if (ret) + pr_info("reset_get_by_name() failed: %d\n", ret); + + if (&priv->reset_ctl) + reset_deassert(&priv->reset_ctl); + __dw_i2c_init(priv->regs, 0, 0); return 0; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index ccfdac7823..33c39b7fb6 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -91,4 +91,11 @@ config RESET_MESON help Support for reset controller on Amlogic Meson SoC. +config RESET_SOCFPGA + bool "Reset controller driver for SoCFPGA" + depends on DM_RESET && ARCH_SOCFPGA + default y + help + Support for reset controller on SoCFPGA platform. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index d1d5146825..ad08be4c8c 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o obj-$(CONFIG_RESET_MESON) += reset-meson.o +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c new file mode 100644 index 0000000000..466455d073 --- /dev/null +++ b/drivers/reset/reset-socfpga.c @@ -0,0 +1,105 @@ +/* + * Socfpga Reset Controller Driver + * + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * based on + * Allwinner SoCs Reset Controller driver + * + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/of_access.h> +#include <reset-uclass.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define BANK_INCREMENT 4 +#define NR_BANKS 8 + +struct socfpga_reset_data { + void __iomem *membase; +}; + +static int socfpga_reset_assert(struct reset_ctl *reset_ctl) +{ + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); + int id = reset_ctl->id; + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + + setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); + return 0; +} + +static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); + int id = reset_ctl->id; + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + + clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); + return 0; +} + +static int socfpga_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int socfpga_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static const struct reset_ops socfpga_reset_ops = { + .request = socfpga_reset_request, + .free = socfpga_reset_free, + .rst_assert = socfpga_reset_assert, + .rst_deassert = socfpga_reset_deassert, +}; + +static int socfpga_reset_probe(struct udevice *dev) +{ + struct socfpga_reset_data *data = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + u32 modrst_offset; + + data->membase = devfdt_get_addr_ptr(dev); + + modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10); + data->membase += modrst_offset; + + return 0; +} + +static const struct udevice_id socfpga_reset_match[] = { + { .compatible = "altr,rst-mgr" }, + { /* sentinel */ }, +}; + +U_BOOT_DRIVER(socfpga_reset) = { + .name = "socfpga-reset", + .id = UCLASS_RESET, + .of_match = socfpga_reset_match, + .probe = socfpga_reset_probe, + .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), + .ops = &socfpga_reset_ops, +}; diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index 9a5c9c91b9..fa4f6538ed 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -88,8 +88,8 @@ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk) bulk->count = 0; count = dev_count_phandle_with_args(dev, "resets", "#reset-cells"); - if (!count) - return 0; + if (count < 1) + return count; bulk->resets = devm_kcalloc(dev, count, sizeof(struct reset_ctl), GFP_KERNEL); diff --git a/include/configs/eagle.h b/include/configs/eagle.h index 2ef0c7a777..d2edd56130 100644 --- a/include/configs/eagle.h +++ b/include/configs/eagle.h @@ -19,6 +19,12 @@ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI +/* Environment compatibility */ +#undef CONFIG_ENV_SIZE_REDUND +#undef CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_OFFSET 0x700000 + /* Board Clock */ /* XTAL_CLK : 33.33MHz */ #define CONFIG_SYS_CLK_FREQ 33333333u diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 4d093ded35..6b2af7a858 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -14,15 +14,9 @@ #include "rcar-gen2-common.h" -/* STACK */ -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) -#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC -#else -#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC -#endif - -#define STACK_AREA_SIZE 0xC000 -#define LOW_LEVEL_MERAM_STACK \ +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ @@ -41,45 +35,29 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_SYS_TMU_CLK_DIV 4 - -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_SPEED2 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ - -/* USB */ -#define CONFIG_USB_EHCI_RMOBILE -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* Module stop status bits */ -/* INTC-RT */ -#define CONFIG_SMSTP0_ENA 0x00400000 -/* MSIF*/ -#define CONFIG_SMSTP2_ENA 0x00002000 -/* INTC-SYS, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 -/* SCIF0 */ -#define CONFIG_SMSTP7_ENA 0x00200000 +#define CONFIG_SYS_TMU_CLK_DIV 4 -/* SD */ -#define CONFIG_SH_SDHI_FREQ 97500000 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" + +/* SPL support */ +#define CONFIG_SPL_TEXT_BASE 0xe6300000 +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif #endif /* __KOELSCH_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index cf1f2b1886..025c7de2d1 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -137,6 +137,7 @@ /* * I2C support */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS @@ -157,6 +158,7 @@ unsigned int cm_get_l4_sp_clk_hz(void); #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) #endif +#endif /* CONFIG_DM_I2C */ /* * QSPI support diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h new file mode 100644 index 0000000000..e3cae08e0e --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2016-2018 Intel Corporation. All rights reserved + * Copyright (C) 2016 Altera Corporation. All rights reserved + * + * SPDX-License-Identifier: GPL-2.0 + * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define CPU2_RESET 2 +#define CPU3_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define EMAC2_RESET 34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +/* 38 is empty */ +#define SDMMC_RESET 39 +#define EMAC0_OCP_RESET 40 +#define EMAC1_OCP_RESET 41 +#define EMAC2_OCP_RESET 42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +/* 46 is empty */ +#define SDMMC_OCP_RESET 47 +#define DMA_RESET 48 +#define SPIM0_RESET 49 +#define SPIM1_RESET 50 +#define SPIS0_RESET 51 +#define SPIS1_RESET 52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define WATCHDOG0_RESET 64 +#define WATCHDOG1_RESET 65 +#define WATCHDOG2_RESET 66 +#define WATCHDOG3_RESET 67 +#define L4SYSTIMER0_RESET 68 +#define L4SYSTIMER1_RESET 69 +#define SPTIMER0_RESET 70 +#define SPTIMER1_RESET 71 +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is empty */ +#define UART0_RESET 80 +#define UART1_RESET 81 +/* 82-87 is empty */ +#define GPIO0_RESET 88 +#define GPIO1_RESET 89 + +/* BRGMODRST */ +#define SOC2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2SOC_RESET 98 +#define F2SSDRAM0_RESET 99 +#define F2SSDRAM1_RESET 100 +#define F2SSDRAM2_RESET 101 +#define DDRSCH_RESET 102 + +/* COLDMODRST */ +#define CPUPO0_RESET 160 +#define CPUPO1_RESET 161 +#define CPUPO2_RESET 162 +#define CPUPO3_RESET 163 +/* 164-167 is empty */ +#define L2_RESET 168 + +/* DBGMODRST */ +#define DBG_RESET 224 +#define CSDAP_RESET 225 + +/* TAPMODRST */ +#define TAP_RESET 256 + +#endif diff --git a/include/reset.h b/include/reset.h index d38f1765ec..ae247ceb4f 100644 --- a/include/reset.h +++ b/include/reset.h @@ -243,7 +243,8 @@ static inline int reset_get_by_index(struct udevice *dev, int index, return -ENOTSUPP; } -static inline int reset_get_bulk(struct udevice *dev, struct clk_bulk *bulk) +static inline int reset_get_bulk(struct udevice *dev, + struct reset_ctl_bulk *bulk) { return -ENOTSUPP; } @@ -284,7 +285,7 @@ static inline int reset_release_all(struct reset_ctl *reset_ctl, int count) return 0; } -static inline int reset_release_bulk(struct clk_bulk *bulk) +static inline int reset_release_bulk(struct reset_ctl_bulk *bulk) { return 0; } |