diff options
546 files changed, 8193 insertions, 2020 deletions
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index f59dc40f3e..0759561ce9 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found at: # https://gitlab.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:xenial-20190720-29Jul2019 +image: trini/u-boot-gitlab-ci-runner:xenial-20190720-02Aug2019 # We run some tests in different order, to catch some failures quicker. stages: @@ -252,7 +252,6 @@ qemu_mips test.py: TEST_PY_BD: "qemu_mips" TEST_PY_TEST_SPEC: "not sleep" BUILDMAN: "^qemu_mips$" - TOOLCHAIN: "mips" <<: *buildman_and_testpy_dfn qemu_mipsel test.py: @@ -261,7 +260,6 @@ qemu_mipsel test.py: TEST_PY_BD: "qemu_mipsel" TEST_PY_TEST_SPEC: "not sleep" BUILDMAN: "^qemu_mipsel$" - TOOLCHAIN: "mips" <<: *buildman_and_testpy_dfn qemu_mips64 test.py: @@ -270,7 +268,6 @@ qemu_mips64 test.py: TEST_PY_BD: "qemu_mips64" TEST_PY_TEST_SPEC: "not sleep" BUILDMAN: "^qemu_mips64$" - TOOLCHAIN: "mips" <<: *buildman_and_testpy_dfn qemu_mips64el test.py: @@ -279,7 +276,6 @@ qemu_mips64el test.py: TEST_PY_BD: "qemu_mips64el" TEST_PY_TEST_SPEC: "not sleep" BUILDMAN: "^qemu_mips64el$" - TOOLCHAIN: "mips" <<: *buildman_and_testpy_dfn qemu-ppce500 test.py: @@ -288,7 +284,14 @@ qemu-ppce500 test.py: TEST_PY_BD: "qemu-ppce500" TEST_PY_TEST_SPEC: "not sleep" BUILDMAN: "^qemu-ppce500$" - TOOLCHAIN: "powerpc" + <<: *buildman_and_testpy_dfn + +qemu-riscv64 test.py: + tags: [ 'all' ] + variables: + TEST_PY_BD: "qemu-riscv64" + TEST_PY_TEST_SPEC: "not sleep" + BUILDMAN: "^qemu-riscv64$" <<: *buildman_and_testpy_dfn qemu-x86 test.py: @@ -297,7 +300,6 @@ qemu-x86 test.py: TEST_PY_BD: "qemu-x86" TEST_PY_TEST_SPEC: "not sleep" BUILDMAN: "^qemu-x86$" - TOOLCHAIN: "i386" <<: *buildman_and_testpy_dfn qemu-x86_64 test.py: @@ -306,7 +308,6 @@ qemu-x86_64 test.py: TEST_PY_BD: "qemu-x86_64" TEST_PY_TEST_SPEC: "not sleep" BUILDMAN: "^qemu-x86_64$" - TOOLCHAIN: "i386" <<: *buildman_and_testpy_dfn zynq_zc702 test.py: @@ -334,5 +335,4 @@ xtfpga test.py: TEST_PY_TEST_SPEC: "not sleep" TEST_PY_ID: "--id qemu" BUILDMAN: "^xtfpga$" - TOOLCHAIN: "xtensa-dc233c-elf" <<: *buildman_and_testpy_dfn diff --git a/.travis.yml b/.travis.yml index 38fc10318e..d330dda5b1 100644 --- a/.travis.yml +++ b/.travis.yml @@ -459,6 +459,13 @@ matrix: QEMU_TARGET="ppc-softmmu" BUILDMAN="^qemu-ppce500$" TOOLCHAIN="powerpc" + - name: "test/py qemu-riscv64" + env: + - TEST_PY_BD="qemu-riscv64" + TEST_PY_TEST_SPEC="not sleep" + QEMU_TARGET="riscv64-softmmu" + BUILDMAN="^qemu-riscv64$" + TOOLCHAIN="riscv" - name: "test/py qemu-x86" env: - TEST_PY_BD="qemu-x86" @@ -2134,171 +2134,6 @@ The following options need to be configured: A better solution is to properly configure the firewall, but sometimes that is not allowed. -- Show boot progress: - CONFIG_SHOW_BOOT_PROGRESS - - Defining this option allows to add some board- - specific code (calling a user-provided function - "show_boot_progress(int)") that enables you to show - the system's boot progress on some display (for - example, some LED's) on your board. At the moment, - the following checkpoints are implemented: - - -Legacy uImage format: - - Arg Where When - 1 common/cmd_bootm.c before attempting to boot an image - -1 common/cmd_bootm.c Image header has bad magic number - 2 common/cmd_bootm.c Image header has correct magic number - -2 common/cmd_bootm.c Image header has bad checksum - 3 common/cmd_bootm.c Image header has correct checksum - -3 common/cmd_bootm.c Image data has bad checksum - 4 common/cmd_bootm.c Image data has correct checksum - -4 common/cmd_bootm.c Image is for unsupported architecture - 5 common/cmd_bootm.c Architecture check OK - -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi) - 6 common/cmd_bootm.c Image Type check OK - -6 common/cmd_bootm.c gunzip uncompression error - -7 common/cmd_bootm.c Unimplemented compression type - 7 common/cmd_bootm.c Uncompression OK - 8 common/cmd_bootm.c No uncompress/copy overwrite error - -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX) - - 9 common/image.c Start initial ramdisk verification - -10 common/image.c Ramdisk header has bad magic number - -11 common/image.c Ramdisk header has bad checksum - 10 common/image.c Ramdisk header is OK - -12 common/image.c Ramdisk data has bad checksum - 11 common/image.c Ramdisk data has correct checksum - 12 common/image.c Ramdisk verification complete, start loading - -13 common/image.c Wrong Image Type (not PPC Linux ramdisk) - 13 common/image.c Start multifile image verification - 14 common/image.c No initial ramdisk, no multifile, continue. - - 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS - - -30 arch/powerpc/lib/board.c Fatal error, hang the system - -31 post/post.c POST test failed, detected by post_output_backlog() - -32 post/post.c POST test failed, detected by post_run_single() - - 34 common/cmd_doc.c before loading a Image from a DOC device - -35 common/cmd_doc.c Bad usage of "doc" command - 35 common/cmd_doc.c correct usage of "doc" command - -36 common/cmd_doc.c No boot device - 36 common/cmd_doc.c correct boot device - -37 common/cmd_doc.c Unknown Chip ID on boot device - 37 common/cmd_doc.c correct chip ID found, device available - -38 common/cmd_doc.c Read Error on boot device - 38 common/cmd_doc.c reading Image header from DOC device OK - -39 common/cmd_doc.c Image header has bad magic number - 39 common/cmd_doc.c Image header has correct magic number - -40 common/cmd_doc.c Error reading Image from DOC device - 40 common/cmd_doc.c Image header has correct magic number - 41 common/cmd_ide.c before loading a Image from a IDE device - -42 common/cmd_ide.c Bad usage of "ide" command - 42 common/cmd_ide.c correct usage of "ide" command - -43 common/cmd_ide.c No boot device - 43 common/cmd_ide.c boot device found - -44 common/cmd_ide.c Device not available - 44 common/cmd_ide.c Device available - -45 common/cmd_ide.c wrong partition selected - 45 common/cmd_ide.c partition selected - -46 common/cmd_ide.c Unknown partition table - 46 common/cmd_ide.c valid partition table found - -47 common/cmd_ide.c Invalid partition type - 47 common/cmd_ide.c correct partition type - -48 common/cmd_ide.c Error reading Image Header on boot device - 48 common/cmd_ide.c reading Image Header from IDE device OK - -49 common/cmd_ide.c Image header has bad magic number - 49 common/cmd_ide.c Image header has correct magic number - -50 common/cmd_ide.c Image header has bad checksum - 50 common/cmd_ide.c Image header has correct checksum - -51 common/cmd_ide.c Error reading Image from IDE device - 51 common/cmd_ide.c reading Image from IDE device OK - 52 common/cmd_nand.c before loading a Image from a NAND device - -53 common/cmd_nand.c Bad usage of "nand" command - 53 common/cmd_nand.c correct usage of "nand" command - -54 common/cmd_nand.c No boot device - 54 common/cmd_nand.c boot device found - -55 common/cmd_nand.c Unknown Chip ID on boot device - 55 common/cmd_nand.c correct chip ID found, device available - -56 common/cmd_nand.c Error reading Image Header on boot device - 56 common/cmd_nand.c reading Image Header from NAND device OK - -57 common/cmd_nand.c Image header has bad magic number - 57 common/cmd_nand.c Image header has correct magic number - -58 common/cmd_nand.c Error reading Image from NAND device - 58 common/cmd_nand.c reading Image from NAND device OK - - -60 common/env_common.c Environment has a bad CRC, using default - - 64 net/eth.c starting with Ethernet configuration. - -64 net/eth.c no Ethernet found. - 65 net/eth.c Ethernet found. - - -80 common/cmd_net.c usage wrong - 80 common/cmd_net.c before calling net_loop() - -81 common/cmd_net.c some error in net_loop() occurred - 81 common/cmd_net.c net_loop() back without error - -82 common/cmd_net.c size == 0 (File with size 0 loaded) - 82 common/cmd_net.c trying automatic boot - 83 common/cmd_net.c running "source" command - -83 common/cmd_net.c some error in automatic boot or "source" command - 84 common/cmd_net.c end without errors - -FIT uImage format: - - Arg Where When - 100 common/cmd_bootm.c Kernel FIT Image has correct format - -100 common/cmd_bootm.c Kernel FIT Image has incorrect format - 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration - -101 common/cmd_bootm.c Can't get configuration for kernel subimage - 102 common/cmd_bootm.c Kernel unit name specified - -103 common/cmd_bootm.c Can't get kernel subimage node offset - 103 common/cmd_bootm.c Found configuration node - 104 common/cmd_bootm.c Got kernel subimage node offset - -104 common/cmd_bootm.c Kernel subimage hash verification failed - 105 common/cmd_bootm.c Kernel subimage hash verification OK - -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture - 106 common/cmd_bootm.c Architecture check OK - -106 common/cmd_bootm.c Kernel subimage has wrong type - 107 common/cmd_bootm.c Kernel subimage type OK - -107 common/cmd_bootm.c Can't get kernel subimage data/size - 108 common/cmd_bootm.c Got kernel subimage data/size - -108 common/cmd_bootm.c Wrong image type (not legacy, FIT) - -109 common/cmd_bootm.c Can't get kernel subimage type - -110 common/cmd_bootm.c Can't get kernel subimage comp - -111 common/cmd_bootm.c Can't get kernel subimage os - -112 common/cmd_bootm.c Can't get kernel subimage load address - -113 common/cmd_bootm.c Image uncompress/copy overwrite error - - 120 common/image.c Start initial ramdisk verification - -120 common/image.c Ramdisk FIT image has incorrect format - 121 common/image.c Ramdisk FIT image has correct format - 122 common/image.c No ramdisk subimage unit name, using configuration - -122 common/image.c Can't get configuration for ramdisk subimage - 123 common/image.c Ramdisk unit name specified - -124 common/image.c Can't get ramdisk subimage node offset - 125 common/image.c Got ramdisk subimage node offset - -125 common/image.c Ramdisk subimage hash verification failed - 126 common/image.c Ramdisk subimage hash verification OK - -126 common/image.c Ramdisk subimage for unsupported architecture - 127 common/image.c Architecture check OK - -127 common/image.c Can't get ramdisk subimage data/size - 128 common/image.c Got ramdisk subimage data/size - 129 common/image.c Can't get ramdisk load address - -129 common/image.c Got ramdisk load address - - -130 common/cmd_doc.c Incorrect FIT image format - 131 common/cmd_doc.c FIT image format OK - - -140 common/cmd_ide.c Incorrect FIT image format - 141 common/cmd_ide.c FIT image format OK - - -150 common/cmd_nand.c Incorrect FIT image format - 151 common/cmd_nand.c FIT image format OK - -- Standalone program support: CONFIG_STANDALONE_LOAD_ADDR This option defines a board specific value for the @@ -3586,6 +3421,8 @@ List of environment variables (most likely not complete): allowed for use by the bootm command. See also "bootm_low" environment variable. + bootstopkeysha256, bootdelaykey, bootstopkey - See README.autoboot + updatefile - Location of the software update file on a TFTP server, used by the automatic software update feature. Please refer to documentation in doc/README.update for more details. diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b437f7500c..ad4d2357bb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -135,7 +135,8 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s905x-khadas-vim.dtb \ meson-gxm-khadas-vim2.dtb \ meson-axg-s400.dtb \ - meson-g12a-u200.dtb + meson-g12a-u200.dtb \ + meson-g12b-odroid-n2.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -240,6 +241,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultra96-rev1.dtb \ + avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ @@ -253,10 +255,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu104-revC.dtb \ zynqmp-zcu106-revA.dtb \ zynqmp-zcu111-revA.dtb \ + zynqmp-zcu1275-revA.dtb \ + zynqmp-zcu1275-revB.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ - zynqmp-zc1275-revA.dtb \ - zynqmp-zc1275-revB.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ zynqmp-zc1751-xm017-dc3.dtb \ diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts new file mode 100644 index 0000000000..ac641ff1a5 --- /dev/null +++ b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 + +/* + * UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM) + * http://ultrazed.org/product/ultrazed-ev-carrier-card + */ + +/dts-v1/; + +#include "avnet-ultrazedev-som-v1.0.dtsi" + +/ { + model = "Avnet UltraZed EV Carrier Card v1.0"; + compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0", + "xlnx,zynqmp"; + chosen { + stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; + }; + aliases { + ethernet0 = &gem3; + serial0 = &uart0; + }; +}; + +&uart0 { + device_type = "serial"; + status = "okay"; +}; + +&i2c_cc { + /* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */ + eeprom: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* IDT Versa Clock 5P49V5935B */ + vc5: clock-generator@6a { + compatible = "idt,5p49v5935"; + reg = <0x6a>; + #clock-cells = <1>; + }; +}; + +/* Ethernet RJ-45 */ +&gem3 { + status = "okay"; +}; + +/* microSD card slot */ +&sdhci1 { + status = "okay"; + xlnx,mio_bank = <1>; + clock-frequency = <199998000>; + max-frequency = <50000000>; + no-1-8-v; + disable-wp; +}; diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi new file mode 100644 index 0000000000..b635db649f --- /dev/null +++ b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 + +/* + * UltraZed-EV SoM v1 + * http://ultrazed.org/product/ultrazed-ev + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "Avnet UltraZed EV SoM v1.0"; + compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp"; + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */ + <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */ + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + i2cswitch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + /* I2C connected to Carrier Card via JX3A1/JX3C1 */ + i2c_cc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */ +&gem3 { + phy-mode = "rgmii-id"; + phy-handle = <&gem3phy>; + gem3phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */ +&sdhci0 { + status = "okay"; + xlnx,mio_bank = <0>; + clock-frequency = <199998000>; +}; diff --git a/arch/arm/dts/da850-evm-u-boot.dtsi b/arch/arm/dts/da850-evm-u-boot.dtsi index d9e8b9926a..aa42d30c72 100644 --- a/arch/arm/dts/da850-evm-u-boot.dtsi +++ b/arch/arm/dts/da850-evm-u-boot.dtsi @@ -16,6 +16,10 @@ }; }; +ð0 { + pinctrl-0 = <&mii_pins>, <&mdio_pins>; +}; + &flash { compatible = "m25p64", "jedec,spi-nor"; }; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 8a9d147ffa..8589f76d23 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -98,7 +98,7 @@ dma-coherent; clocks = <&k3_clks 5 10>; clock-names = "fck"; - power-domains = <&k3_pds 5>; + power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; ti,psil-base = <0x7000>; dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>, diff --git a/arch/arm/dts/meson-g12a-u-boot.dtsi b/arch/arm/dts/meson-g12a-u-boot.dtsi deleted file mode 100644 index 8e0c81f199..0000000000 --- a/arch/arm/dts/meson-g12a-u-boot.dtsi +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/ { - soc { - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.710", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000 - 0x0 0xff634540 0x0 0x8>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; - status = "disabled"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - }; - - sd_emmc_a: sd@ffe03000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe03000 0x0 0x800>; - interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; - }; - - sd_emmc_b: sd@ffe05000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe05000 0x0 0x800>; - interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@ffe07000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe07000 0x0 0x800>; - interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - }; -}; - -&periphs_pinctrl { - emmc_pins: emmc { - mux { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7", - "emmc_clk", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_nand_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - eth_leds_pins: eth-leds { - mux { - groups = "eth_link_led", - "eth_act_led"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_pins: eth-rmii { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_rgmii_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_txen", - "eth_txd0", - "eth_txd1"; - function = "eth"; - bias-disable; - }; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - bias-disable; - }; - }; - - sdcard_c_pins: sdcard_c { - mux { - groups = "sdcard_d0_c", - "sdcard_d1_c", - "sdcard_d2_c", - "sdcard_d3_c", - "sdcard_cmd_c", - "sdcard_clk_c"; - function = "sdcard"; - bias-pull-up; - }; - }; - - sdcard_clk_gate_c_pins: sdcard_clk_gate_c { - mux { - groups = "GPIOC_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdcard_z_pins: sdcard_z { - mux { - groups = "sdcard_d0_z", - "sdcard_d1_z", - "sdcard_d2_z", - "sdcard_d3_z", - "sdcard_cmd_z", - "sdcard_clk_z"; - function = "sdcard"; - bias-pull-up; - }; - }; - - sdcard_clk_gate_z_pins: sdcard_clk_gate_z { - mux { - groups = "GPIOZ_6"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; -}; - -&periphs { - eth_phy: mdio-multiplexer@4c000 { - compatible = "amlogic,g12a-mdio-mux"; - reg = <0x0 0x4c000 0x0 0xa4>; - clocks = <&clkc CLKID_ETH_PHY>, - <&xtal>, - <&clkc CLKID_MPLL_5OM>; - clock-names = "pclk", "clkin0", "clkin1"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - - ext_mdio: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - int_mdio: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - internal_ephy: ethernet_phy@8 { - compatible = "ethernet-phy-id0180.3300", - "ethernet-phy-ieee802.3-c22"; - reg = <8>; - max-speed = <100>; - - /* FIXME: Add irq support */ - }; - }; - }; -}; - - diff --git a/arch/arm/dts/meson-g12a-u200-u-boot.dtsi b/arch/arm/dts/meson-g12a-u200-u-boot.dtsi deleted file mode 100644 index 9486ab0c47..0000000000 --- a/arch/arm/dts/meson-g12a-u200-u-boot.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12a-u-boot.dtsi" - - / { - aliases { - ethernet0 = ðmac; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_leds_pins>; - pinctrl-names = "default"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts index 0e8045b8a9..8551fbd4a4 100644 --- a/arch/arm/dts/meson-g12a-u200.dts +++ b/arch/arm/dts/meson-g12a-u200.dts @@ -15,14 +15,12 @@ aliases { serial0 = &uart_AO; + ethernet0 = ðmac; }; + chosen { stdout-path = "serial0:115200n8"; }; - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; cvbs-connector { compatible = "composite-video-connector"; @@ -34,13 +32,9 @@ }; }; - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; }; hdmi-connector { @@ -54,6 +48,20 @@ }; }; + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + flash_1v8: regulator-flash_1v8 { + compatible = "regulator-fixed"; + regulator-name = "FLASH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + main_12v: regulator-main_12v { compatible = "regulator-fixed"; regulator-name = "12V"; @@ -62,6 +70,17 @@ regulator-always-on; }; + usb_pwr_en: regulator-usb_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + vcc_1v8: regulator-vcc_1v8 { compatible = "regulator-fixed"; regulator-name = "VCC_1V8"; @@ -92,17 +111,6 @@ enable-active-high; }; - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - vddao_1v8: regulator-vddao_1v8 { compatible = "regulator-fixed"; regulator-name = "VDDAO_1V8"; @@ -143,6 +151,12 @@ }; }; +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; @@ -156,6 +170,70 @@ }; }; +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +/* i2c Touch */ +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>; + pinctrl-names = "default"; +}; + +/* i2c CM */ +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>; + pinctrl-names = "default"; +}; + +/* i2c Audio */ +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; + &uart_AO { status = "okay"; pinctrl-0 = <&uart_ao_a_pins>; diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi index 9f72396ba7..f8d43e3dcf 100644 --- a/arch/arm/dts/meson-g12a.dtsi +++ b/arch/arm/dts/meson-g12a.dtsi @@ -5,10 +5,12 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/axg-audio-clkc.h> #include <dt-bindings/clock/g12a-clkc.h> #include <dt-bindings/clock/g12a-aoclkc.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> #include <dt-bindings/reset/amlogic,meson-g12a-reset.h> / { @@ -18,6 +20,39 @@ #address-cells = <2>; #size-cells = <2>; + tdmif_a: audio-controller-0 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_A"; + clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, + <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_b: audio-controller-1 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_B"; + clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, + <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + + tdmif_c: audio-controller-2 { + compatible = "amlogic,axg-tdm-iface"; + #sound-dai-cells = <0>; + sound-name-prefix = "TDM_C"; + clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, + <&clkc_audio AUD_CLKID_MST_C_SCLK>, + <&clkc_audio AUD_CLKID_MST_C_LRCLK>; + clock-names = "mclk", "sclk", "lrclk"; + status = "disabled"; + }; + cpus { #address-cells = <0x2>; #size-cells = <0x0>; @@ -102,6 +137,27 @@ #size-cells = <2>; ranges; + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,meson-axg-dwmac", + "snps,dwmac-3.70a", + "snps,dwmac"; + reg = <0x0 0xff3f0000 0x0 0x10000 + 0x0 0xff634540 0x0 0x8>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + status = "disabled"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + }; + apb: bus@ff600000 { compatible = "simple-bus"; reg = <0x0 0xff600000 0x0 0x200000>; @@ -123,6 +179,7 @@ clock-names = "isfr", "iahb", "venci"; #address-cells = <1>; #size-cells = <0>; + #sound-dai-cells = <0>; status = "disabled"; /* VPU VENC Input */ @@ -140,6 +197,19 @@ }; }; + apb_efuse: bus@30000 { + compatible = "simple-bus"; + reg = <0x0 0x30000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; + + hwrng: rng@218 { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x218 0x0 0x4>; + }; + }; + periphs: bus@34400 { compatible = "simple-bus"; reg = <0x0 0x34400 0x0 0x400>; @@ -185,12 +255,55 @@ }; }; + emmc_pins: emmc { + mux-0 { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "emmc_clk"; + function = "emmc"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_nand_ds"; + function = "emmc"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + hdmitx_ddc_pins: hdmitx_ddc { mux { groups = "hdmitx_sda", "hdmitx_sck"; function = "hdmitx"; bias-disable; + drive-strength-microamp = <4000>; }; }; @@ -202,6 +315,1040 @@ }; }; + + i2c0_sda_c_pins: i2c0-sda-c { + mux { + groups = "i2c0_sda_c"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + + }; + }; + + i2c0_sck_c_pins: i2c0-sck-c { + mux { + groups = "i2c0_sck_c"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sda_z0_pins: i2c0-sda-z0 { + mux { + groups = "i2c0_sda_z0"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sck_z1_pins: i2c0-sck-z1 { + mux { + groups = "i2c0_sck_z1"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sda_z7_pins: i2c0-sda-z7 { + mux { + groups = "i2c0_sda_z7"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c0_sda_z8_pins: i2c0-sda-z8 { + mux { + groups = "i2c0_sda_z8"; + function = "i2c0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sda_x_pins: i2c1-sda-x { + mux { + groups = "i2c1_sda_x"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sck_x_pins: i2c1-sck-x { + mux { + groups = "i2c1_sck_x"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sda_h2_pins: i2c1-sda-h2 { + mux { + groups = "i2c1_sda_h2"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sck_h3_pins: i2c1-sck-h3 { + mux { + groups = "i2c1_sck_h3"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sda_h6_pins: i2c1-sda-h6 { + mux { + groups = "i2c1_sda_h6"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c1_sck_h7_pins: i2c1-sck-h7 { + mux { + groups = "i2c1_sck_h7"; + function = "i2c1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sda_x_pins: i2c2-sda-x { + mux { + groups = "i2c2_sda_x"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sck_x_pins: i2c2-sck-x { + mux { + groups = "i2c2_sck_x"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sda_z_pins: i2c2-sda-z { + mux { + groups = "i2c2_sda_z"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c2_sck_z_pins: i2c2-sck-z { + mux { + groups = "i2c2_sck_z"; + function = "i2c2"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sda_h_pins: i2c3-sda-h { + mux { + groups = "i2c3_sda_h"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sck_h_pins: i2c3-sck-h { + mux { + groups = "i2c3_sck_h"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sda_a_pins: i2c3-sda-a { + mux { + groups = "i2c3_sda_a"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c3_sck_a_pins: i2c3-sck-a { + mux { + groups = "i2c3_sck_a"; + function = "i2c3"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk0_a_pins: mclk0-a { + mux { + groups = "mclk0_a"; + function = "mclk0"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk1_a_pins: mclk1-a { + mux { + groups = "mclk1_a"; + function = "mclk1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk1_x_pins: mclk1-x { + mux { + groups = "mclk1_x"; + function = "mclk1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk1_z_pins: mclk1-z { + mux { + groups = "mclk1_z"; + function = "mclk1"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + pdm_din0_a_pins: pdm-din0-a { + mux { + groups = "pdm_din0_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din0_c_pins: pdm-din0-c { + mux { + groups = "pdm_din0_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din0_x_pins: pdm-din0-x { + mux { + groups = "pdm_din0_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din0_z_pins: pdm-din0-z { + mux { + groups = "pdm_din0_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_a_pins: pdm-din1-a { + mux { + groups = "pdm_din1_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_c_pins: pdm-din1-c { + mux { + groups = "pdm_din1_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_x_pins: pdm-din1-x { + mux { + groups = "pdm_din1_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din1_z_pins: pdm-din1-z { + mux { + groups = "pdm_din1_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_a_pins: pdm-din2-a { + mux { + groups = "pdm_din2_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_c_pins: pdm-din2-c { + mux { + groups = "pdm_din2_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_x_pins: pdm-din2-x { + mux { + groups = "pdm_din2_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din2_z_pins: pdm-din2-z { + mux { + groups = "pdm_din2_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_a_pins: pdm-din3-a { + mux { + groups = "pdm_din3_a"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_c_pins: pdm-din3-c { + mux { + groups = "pdm_din3_c"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_x_pins: pdm-din3-x { + mux { + groups = "pdm_din3_x"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_din3_z_pins: pdm-din3-z { + mux { + groups = "pdm_din3_z"; + function = "pdm"; + bias-disable; + }; + }; + + pdm_dclk_a_pins: pdm-dclk-a { + mux { + groups = "pdm_dclk_a"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pdm_dclk_c_pins: pdm-dclk-c { + mux { + groups = "pdm_dclk_c"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pdm_dclk_x_pins: pdm-dclk-x { + mux { + groups = "pdm_dclk_x"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pdm_dclk_z_pins: pdm-dclk-z { + mux { + groups = "pdm_dclk_z"; + function = "pdm"; + bias-disable; + drive-strength-microamp = <500>; + }; + }; + + pwm_a_pins: pwm-a { + mux { + groups = "pwm_a"; + function = "pwm_a"; + bias-disable; + }; + }; + + pwm_b_x7_pins: pwm-b-x7 { + mux { + groups = "pwm_b_x7"; + function = "pwm_b"; + bias-disable; + }; + }; + + pwm_b_x19_pins: pwm-b-x19 { + mux { + groups = "pwm_b_x19"; + function = "pwm_b"; + bias-disable; + }; + }; + + pwm_c_c_pins: pwm-c-c { + mux { + groups = "pwm_c_c"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_c_x5_pins: pwm-c-x5 { + mux { + groups = "pwm_c_x5"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_c_x8_pins: pwm-c-x8 { + mux { + groups = "pwm_c_x8"; + function = "pwm_c"; + bias-disable; + }; + }; + + pwm_d_x3_pins: pwm-d-x3 { + mux { + groups = "pwm_d_x3"; + function = "pwm_d"; + bias-disable; + }; + }; + + pwm_d_x6_pins: pwm-d-x6 { + mux { + groups = "pwm_d_x6"; + function = "pwm_d"; + bias-disable; + }; + }; + + pwm_e_pins: pwm-e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + bias-disable; + }; + }; + + pwm_f_x_pins: pwm-f-x { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + bias-disable; + }; + }; + + pwm_f_h_pins: pwm-f-h { + mux { + groups = "pwm_f_h"; + function = "pwm_f"; + bias-disable; + }; + }; + + sdcard_c_pins: sdcard_c { + mux-0 { + groups = "sdcard_d0_c", + "sdcard_d1_c", + "sdcard_d2_c", + "sdcard_d3_c", + "sdcard_cmd_c"; + function = "sdcard"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "sdcard_clk_c"; + function = "sdcard"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_clk_gate_c_pins: sdcard_clk_gate_c { + mux { + groups = "GPIOC_4"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_z_pins: sdcard_z { + mux-0 { + groups = "sdcard_d0_z", + "sdcard_d1_z", + "sdcard_d2_z", + "sdcard_d3_z", + "sdcard_cmd_z"; + function = "sdcard"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "sdcard_clk_z"; + function = "sdcard"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + sdcard_clk_gate_z_pins: sdcard_clk_gate_z { + mux { + groups = "GPIOZ_6"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + sdio_pins: sdio { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_clk", + "sdio_cmd"; + function = "sdio"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + spdif_in_a10_pins: spdif-in-a10 { + mux { + groups = "spdif_in_a10"; + function = "spdif_in"; + bias-disable; + }; + }; + + spdif_in_a12_pins: spdif-in-a12 { + mux { + groups = "spdif_in_a12"; + function = "spdif_in"; + bias-disable; + }; + }; + + spdif_in_h_pins: spdif-in-h { + mux { + groups = "spdif_in_h"; + function = "spdif_in"; + bias-disable; + }; + }; + + spdif_out_h_pins: spdif-out-h { + mux { + groups = "spdif_out_h"; + function = "spdif_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + spdif_out_a11_pins: spdif-out-a11 { + mux { + groups = "spdif_out_a11"; + function = "spdif_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + spdif_out_a13_pins: spdif-out-a13 { + mux { + groups = "spdif_out_a13"; + function = "spdif_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + tdm_a_din0_pins: tdm-a-din0 { + mux { + groups = "tdm_a_din0"; + function = "tdm_a"; + bias-disable; + }; + }; + + + tdm_a_din1_pins: tdm-a-din1 { + mux { + groups = "tdm_a_din1"; + function = "tdm_a"; + bias-disable; + }; + }; + + tdm_a_dout0_pins: tdm-a-dout0 { + mux { + groups = "tdm_a_dout0"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_dout1_pins: tdm-a-dout1 { + mux { + groups = "tdm_a_dout1"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_fs_pins: tdm-a-fs { + mux { + groups = "tdm_a_fs"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_sclk_pins: tdm-a-sclk { + mux { + groups = "tdm_a_sclk"; + function = "tdm_a"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_a_slv_fs_pins: tdm-a-slv-fs { + mux { + groups = "tdm_a_slv_fs"; + function = "tdm_a"; + bias-disable; + }; + }; + + + tdm_a_slv_sclk_pins: tdm-a-slv-sclk { + mux { + groups = "tdm_a_slv_sclk"; + function = "tdm_a"; + bias-disable; + }; + }; + + tdm_b_din0_pins: tdm-b-din0 { + mux { + groups = "tdm_b_din0"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din1_pins: tdm-b-din1 { + mux { + groups = "tdm_b_din1"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din2_pins: tdm-b-din2 { + mux { + groups = "tdm_b_din2"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din3_a_pins: tdm-b-din3-a { + mux { + groups = "tdm_b_din3_a"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_din3_h_pins: tdm-b-din3-h { + mux { + groups = "tdm_b_din3_h"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_dout0_pins: tdm-b-dout0 { + mux { + groups = "tdm_b_dout0"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout1_pins: tdm-b-dout1 { + mux { + groups = "tdm_b_dout1"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout2_pins: tdm-b-dout2 { + mux { + groups = "tdm_b_dout2"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout3_a_pins: tdm-b-dout3-a { + mux { + groups = "tdm_b_dout3_a"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_dout3_h_pins: tdm-b-dout3-h { + mux { + groups = "tdm_b_dout3_h"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_fs_pins: tdm-b-fs { + mux { + groups = "tdm_b_fs"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_sclk_pins: tdm-b-sclk { + mux { + groups = "tdm_b_sclk"; + function = "tdm_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_b_slv_fs_pins: tdm-b-slv-fs { + mux { + groups = "tdm_b_slv_fs"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_b_slv_sclk_pins: tdm-b-slv-sclk { + mux { + groups = "tdm_b_slv_sclk"; + function = "tdm_b"; + bias-disable; + }; + }; + + tdm_c_din0_a_pins: tdm-c-din0-a { + mux { + groups = "tdm_c_din0_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din0_z_pins: tdm-c-din0-z { + mux { + groups = "tdm_c_din0_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din1_a_pins: tdm-c-din1-a { + mux { + groups = "tdm_c_din1_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din1_z_pins: tdm-c-din1-z { + mux { + groups = "tdm_c_din1_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din2_a_pins: tdm-c-din2-a { + mux { + groups = "tdm_c_din2_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + eth_leds_pins: eth-leds { + mux { + groups = "eth_link_led", + "eth_act_led"; + function = "eth"; + bias-disable; + }; + }; + + eth_pins: eth { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_txen", + "eth_txd0", + "eth_txd1"; + function = "eth"; + drive-strength-microamp = <4000>; + bias-disable; + }; + }; + + eth_rgmii_pins: eth-rgmii { + mux { + groups = "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength-microamp = <4000>; + bias-disable; + }; + }; + + tdm_c_din2_z_pins: tdm-c-din2-z { + mux { + groups = "tdm_c_din2_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din3_a_pins: tdm-c-din3-a { + mux { + groups = "tdm_c_din3_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_din3_z_pins: tdm-c-din3-z { + mux { + groups = "tdm_c_din3_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_dout0_a_pins: tdm-c-dout0-a { + mux { + groups = "tdm_c_dout0_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout0_z_pins: tdm-c-dout0-z { + mux { + groups = "tdm_c_dout0_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout1_a_pins: tdm-c-dout1-a { + mux { + groups = "tdm_c_dout1_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout1_z_pins: tdm-c-dout1-z { + mux { + groups = "tdm_c_dout1_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout2_a_pins: tdm-c-dout2-a { + mux { + groups = "tdm_c_dout2_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout2_z_pins: tdm-c-dout2-z { + mux { + groups = "tdm_c_dout2_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout3_a_pins: tdm-c-dout3-a { + mux { + groups = "tdm_c_dout3_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_dout3_z_pins: tdm-c-dout3-z { + mux { + groups = "tdm_c_dout3_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_fs_a_pins: tdm-c-fs-a { + mux { + groups = "tdm_c_fs_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_fs_z_pins: tdm-c-fs-z { + mux { + groups = "tdm_c_fs_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_sclk_a_pins: tdm-c-sclk-a { + mux { + groups = "tdm_c_sclk_a"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_sclk_z_pins: tdm-c-sclk-z { + mux { + groups = "tdm_c_sclk_z"; + function = "tdm_c"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { + mux { + groups = "tdm_c_slv_fs_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { + mux { + groups = "tdm_c_slv_fs_z"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { + mux { + groups = "tdm_c_slv_sclk_a"; + function = "tdm_c"; + bias-disable; + }; + }; + + tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { + mux { + groups = "tdm_c_slv_sclk_z"; + function = "tdm_c"; + bias-disable; + }; + }; + uart_a_pins: uart-a { mux { groups = "uart_a_tx", @@ -303,6 +1450,282 @@ }; }; + pdm: audio-controller@40000 { + compatible = "amlogic,g12a-pdm", + "amlogic,axg-pdm"; + reg = <0x0 0x40000 0x0 0x34>; + #sound-dai-cells = <0>; + sound-name-prefix = "PDM"; + clocks = <&clkc_audio AUD_CLKID_PDM>, + <&clkc_audio AUD_CLKID_PDM_DCLK>, + <&clkc_audio AUD_CLKID_PDM_SYSCLK>; + clock-names = "pclk", "dclk", "sysclk"; + status = "disabled"; + }; + + audio: bus@42000 { + compatible = "simple-bus"; + reg = <0x0 0x42000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; + + clkc_audio: clock-controller@0 { + status = "disabled"; + compatible = "amlogic,g12a-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + + resets = <&reset RESET_AUDIO>; + }; + + toddr_a: audio-controller@100 { + compatible = "amlogic,g12a-toddr", + "amlogic,axg-toddr"; + reg = <0x0 0x100 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_A"; + interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_TODDR_A>; + resets = <&arb AXG_ARB_TODDR_A>; + status = "disabled"; + }; + + toddr_b: audio-controller@140 { + compatible = "amlogic,g12a-toddr", + "amlogic,axg-toddr"; + reg = <0x0 0x140 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_B"; + interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_TODDR_B>; + resets = <&arb AXG_ARB_TODDR_B>; + status = "disabled"; + }; + + toddr_c: audio-controller@180 { + compatible = "amlogic,g12a-toddr", + "amlogic,axg-toddr"; + reg = <0x0 0x180 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "TODDR_C"; + interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_TODDR_C>; + resets = <&arb AXG_ARB_TODDR_C>; + status = "disabled"; + }; + + frddr_a: audio-controller@1c0 { + compatible = "amlogic,g12a-frddr", + "amlogic,axg-frddr"; + reg = <0x0 0x1c0 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_A"; + interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; + resets = <&arb AXG_ARB_FRDDR_A>; + status = "disabled"; + }; + + frddr_b: audio-controller@200 { + compatible = "amlogic,g12a-frddr", + "amlogic,axg-frddr"; + reg = <0x0 0x200 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_B"; + interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; + resets = <&arb AXG_ARB_FRDDR_B>; + status = "disabled"; + }; + + frddr_c: audio-controller@240 { + compatible = "amlogic,g12a-frddr", + "amlogic,axg-frddr"; + reg = <0x0 0x240 0x0 0x1c>; + #sound-dai-cells = <0>; + sound-name-prefix = "FRDDR_C"; + interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; + resets = <&arb AXG_ARB_FRDDR_C>; + status = "disabled"; + }; + + arb: reset-controller@280 { + status = "disabled"; + compatible = "amlogic,meson-axg-audio-arb"; + reg = <0x0 0x280 0x0 0x4>; + #reset-cells = <1>; + clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; + }; + + tdmin_a: audio-controller@300 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x300 0x0 0x40>; + sound-name-prefix = "TDMIN_A"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_b: audio-controller@340 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x340 0x0 0x40>; + sound-name-prefix = "TDMIN_B"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_c: audio-controller@380 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x380 0x0 0x40>; + sound-name-prefix = "TDMIN_C"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmin_lb: audio-controller@3c0 { + compatible = "amlogic,g12a-tdmin", + "amlogic,axg-tdmin"; + reg = <0x0 0x3c0 0x0 0x40>; + sound-name-prefix = "TDMIN_LB"; + clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + spdifin: audio-controller@400 { + compatible = "amlogic,g12a-spdifin", + "amlogic,axg-spdifin"; + reg = <0x0 0x400 0x0 0x30>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFIN"; + interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, + <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; + clock-names = "pclk", "refclk"; + status = "disabled"; + }; + + spdifout: audio-controller@480 { + compatible = "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg = <0x0 0x480 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names = "pclk", "mclk"; + status = "disabled"; + }; + + tdmout_a: audio-controller@500 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x0 0x500 0x0 0x40>; + sound-name-prefix = "TDMOUT_A"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_b: audio-controller@540 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x0 0x540 0x0 0x40>; + sound-name-prefix = "TDMOUT_B"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + tdmout_c: audio-controller@580 { + compatible = "amlogic,g12a-tdmout"; + reg = <0x0 0x580 0x0 0x40>; + sound-name-prefix = "TDMOUT_C"; + clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; + clock-names = "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + status = "disabled"; + }; + + spdifout_b: audio-controller@680 { + compatible = "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg = <0x0 0x680 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT_B"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, + <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; + clock-names = "pclk", "mclk"; + status = "disabled"; + }; + + tohdmitx: audio-controller@744 { + compatible = "amlogic,g12a-tohdmitx"; + reg = <0x0 0x744 0x0 0x4>; + #sound-dai-cells = <1>; + sound-name-prefix = "TOHDMITX"; + status = "disabled"; + }; + }; + usb3_pcie_phy: phy@46000 { compatible = "amlogic,g12a-usb3-pcie-phy"; reg = <0x0 0x46000 0x0 0x2000>; @@ -314,6 +1737,38 @@ assigned-clock-rates = <100000000>; #phy-cells = <1>; }; + + eth_phy: mdio-multiplexer@4c000 { + compatible = "amlogic,g12a-mdio-mux"; + reg = <0x0 0x4c000 0x0 0xa4>; + clocks = <&clkc CLKID_ETH_PHY>, + <&xtal>, + <&clkc CLKID_MPLL_50M>; + clock-names = "pclk", "clkin0", "clkin1"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + + ext_mdio: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + int_mdio: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + internal_ephy: ethernet_phy@8 { + compatible = "ethernet-phy-id0180.3301", + "ethernet-phy-ieee802.3-c22"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <8>; + max-speed = <100>; + }; + }; + }; }; aobus: bus@ff800000 { @@ -401,6 +1856,145 @@ gpio-ranges = <&ao_pinctrl 0 0 15>; }; + i2c_ao_sck_pins: i2c_ao_sck_pins { + mux { + groups = "i2c_ao_sck"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c_ao_sda_pins: i2c_ao_sda { + mux { + groups = "i2c_ao_sda"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c_ao_sck_e_pins: i2c_ao_sck_e { + mux { + groups = "i2c_ao_sck_e"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + i2c_ao_sda_e_pins: i2c_ao_sda_e { + mux { + groups = "i2c_ao_sda_e"; + function = "i2c_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + mclk0_ao_pins: mclk0-ao { + mux { + groups = "mclk0_ao"; + function = "mclk0_ao"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_din0_pins: tdm-ao-b-din0 { + mux { + groups = "tdm_ao_b_din0"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + spdif_ao_out_pins: spdif-ao-out { + mux { + groups = "spdif_ao_out"; + function = "spdif_ao_out"; + drive-strength-microamp = <500>; + bias-disable; + }; + }; + + tdm_ao_b_din1_pins: tdm-ao-b-din1 { + mux { + groups = "tdm_ao_b_din1"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + tdm_ao_b_din2_pins: tdm-ao-b-din2 { + mux { + groups = "tdm_ao_b_din2"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { + mux { + groups = "tdm_ao_b_dout0"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { + mux { + groups = "tdm_ao_b_dout1"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { + mux { + groups = "tdm_ao_b_dout2"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_fs_pins: tdm-ao-b-fs { + mux { + groups = "tdm_ao_b_fs"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_sclk_pins: tdm-ao-b-sclk { + mux { + groups = "tdm_ao_b_sclk"; + function = "tdm_ao_b"; + bias-disable; + drive-strength-microamp = <3000>; + }; + }; + + tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { + mux { + groups = "tdm_ao_b_slv_fs"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + + tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { + mux { + groups = "tdm_ao_b_slv_sclk"; + function = "tdm_ao_b"; + bias-disable; + }; + }; + uart_ao_a_pins: uart-a-ao { mux { groups = "uart_ao_a_tx", @@ -418,6 +2012,69 @@ bias-disable; }; }; + + pwm_ao_a_pins: pwm-ao-a { + mux { + groups = "pwm_ao_a"; + function = "pwm_ao_a"; + bias-disable; + }; + }; + + pwm_ao_b_pins: pwm-ao-b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + bias-disable; + }; + }; + + pwm_ao_c_4_pins: pwm-ao-c-4 { + mux { + groups = "pwm_ao_c_4"; + function = "pwm_ao_c"; + bias-disable; + }; + }; + + pwm_ao_c_6_pins: pwm-ao-c-6 { + mux { + groups = "pwm_ao_c_6"; + function = "pwm_ao_c"; + bias-disable; + }; + }; + + pwm_ao_d_5_pins: pwm-ao-d-5 { + mux { + groups = "pwm_ao_d_5"; + function = "pwm_ao_d"; + bias-disable; + }; + }; + + pwm_ao_d_10_pins: pwm-ao-d-10 { + mux { + groups = "pwm_ao_d_10"; + function = "pwm_ao_d"; + bias-disable; + }; + }; + + pwm_ao_d_e_pins: pwm-ao-d-e { + mux { + groups = "pwm_ao_d_e"; + function = "pwm_ao_d"; + }; + }; + + remote_input_ao_pins: remote-input-ao { + mux { + groups = "remote_ao_input"; + function = "remote_ao_input"; + bias-disable; + }; + }; }; }; @@ -445,12 +2102,19 @@ status = "disabled"; }; + pwm_AO_cd: pwm@2000 { + compatible = "amlogic,meson-g12a-ao-pwm-cd"; + reg = <0x0 0x2000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart_AO: serial@3000 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; reg = <0x0 0x3000 0x0 0x18>; interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&xtal>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; @@ -460,11 +2124,35 @@ "amlogic,meson-ao-uart"; reg = <0x0 0x4000 0x0 0x18>; interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&xtal>, <&xtal>; + clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + i2c_AO: i2c@5000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x05000 0x0 0x20>; + interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + pwm_AO_ab: pwm@7000 { + compatible = "amlogic,meson-g12a-ao-pwm-ab"; + reg = <0x0 0x7000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@8000 { + compatible = "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8000 0x0 0x20>; + interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + saradc: adc@9000 { compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; @@ -533,6 +2221,76 @@ #reset-cells = <1>; }; + gpio_intc: interrupt-controller@f080 { + compatible = "amlogic,meson-g12a-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0xf080 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + }; + + pwm_ef: pwm@19000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x19000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@1a000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x1a000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ab: pwm@1b000 { + compatible = "amlogic,meson-g12a-ee-pwm"; + reg = <0x0 0x1b000 0x0 0x20>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2c3: i2c@1c000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1c000 0x0 0x20>; + interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + i2c2: i2c@1d000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1d000 0x0 0x20>; + interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + i2c1: i2c@1e000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1e000 0x0 0x20>; + interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + + i2c0: i2c@1f000 { + compatible = "amlogic,meson-axg-i2c"; + status = "disabled"; + reg = <0x0 0x1f000 0x0 0x20>; + interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + }; + clk_msr: clock-measure@18000 { compatible = "amlogic,meson-g12a-clk-measure"; reg = <0x0 0x18000 0x0 0x10>; @@ -566,6 +2324,43 @@ }; }; + sd_emmc_a: sd@ffe03000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xffe03000 0x0 0x800>; + interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_A>; + amlogic,dram-access-quirk; + }; + + sd_emmc_b: sd@ffe05000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xffe05000 0x0 0x800>; + interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_B>; + }; + + sd_emmc_c: mmc@ffe07000 { + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0xffe07000 0x0 0x800>; + interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_CLK0>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + resets = <&reset RESET_SD_EMMC_C>; + }; + usb: usb@ffe09000 { status = "disabled"; compatible = "amlogic,meson-g12a-usb-ctrl"; diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts new file mode 100644 index 0000000000..81780ffcc7 --- /dev/null +++ b/arch/arm/dts/meson-g12b-odroid-n2.dts @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/dts-v1/; + +#include "meson-g12b.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/meson-g12a-gpio.h> +#include <dt-bindings/sound/meson-g12a-tohdmitx.h> + +/ { + compatible = "hardkernel,odroid-n2", "amlogic,g12b"; + model = "Hardkernel ODROID-N2"; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "n2:blue"; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + tflash_vdd: regulator-tflash_vdd { + compatible = "regulator-fixed"; + + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tf_io: gpio-regulator-tf_io { + compatible = "regulator-gpio"; + + regulator-name = "TF_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0 + 1800000 1>; + }; + + flash_1v8: regulator-flash_1v8 { + compatible = "regulator-fixed"; + regulator-name = "FLASH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + main_12v: regulator-main_12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&main_12v>; + }; + + vcc_1v8: regulator-vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + /* FIXME: actually controlled by VDDCPU_B_EN */ + }; + + hub_5v: regulator-hub_5v { + compatible = "regulator-fixed"; + regulator-name = "HUB_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to the Hub CHIPENABLE, LOW sets low power state */ + gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_pwr_en: regulator-usb_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to the microUSB port power enable */ + gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddao_1v8: regulator-vddao_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_12v>; + regulator-always-on; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "G12A-ODROIDN2"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&clkc_audio { + status = "okay"; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&gpio { + /* + * WARNING: The USB Hub on the Odroid-N2 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&vcc_5v>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&tf_io>; + +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_pwr_en>; +}; + +&usb2_phy0 { + phy-supply = <&vcc_5v>; +}; + +&usb2_phy1 { + /* Enable the hub which is connected to this port */ + phy-supply = <&hub_5v>; +}; diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi new file mode 100644 index 0000000000..9e88e513b2 --- /dev/null +++ b/arch/arm/dts/meson-g12b.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include "meson-g12a.dtsi" + +/ { + compatible = "amlogic,g12b"; + + cpus { + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu100>; + }; + + core1 { + cpu = <&cpu101>; + }; + + core2 { + cpu = <&cpu102>; + }; + + core3 { + cpu = <&cpu103>; + }; + }; + }; + + /delete-node/ cpu@2; + /delete-node/ cpu@3; + + cpu100: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu101: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu102: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x102>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu103: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x103>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; +}; + +&clkc { + compatible = "amlogic,g12b-clkc"; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index abeac30593..097538cc4b 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -462,6 +462,76 @@ reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a7795-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7795-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a7795-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a7795-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -1836,7 +1906,7 @@ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, diff --git a/arch/arm/dts/r8a7796-salvator-x.dts b/arch/arm/dts/r8a7796-salvator-x.dts index b4f9567cb9..2aefa53cb1 100644 --- a/arch/arm/dts/r8a7796-salvator-x.dts +++ b/arch/arm/dts/r8a7796-salvator-x.dts @@ -68,6 +68,7 @@ ports { /* rsnd_port0 is on salvator-common */ rsnd_port1: port@1 { + reg = <1>; rsnd_endpoint1: endpoint { remote-endpoint = <&dw_hdmi0_snd_in>; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index cdf784899c..d5e2f4af83 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -1775,7 +1775,7 @@ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2162,17 +2162,6 @@ dma-names = "rx", "tx"; }; }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - }; - }; }; audma0: dma-controller@ec700000 { diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index 9763d108e1..2554b1742d 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -317,6 +317,76 @@ reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a77965-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a77965-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a77965-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a77965-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77965-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -1461,7 +1531,7 @@ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -1585,56 +1655,267 @@ }; }; + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; + rcar_sound,ssi { ssi0: ssi-0 { interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; }; ssi1: ssi-1 { interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; }; ssi2: ssi-2 { interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; }; ssi3: ssi-3 { interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; }; ssi4: ssi-4 { interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; }; ssi5: ssi-5 { interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; }; ssi6: ssi-6 { interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; }; ssi7: ssi-7 { interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; }; ssi8: ssi-8 { interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; }; ssi9: ssi-9 { interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; }; }; }; @@ -2166,7 +2447,6 @@ du: display@feb00000 { compatible = "renesas,du-r8a77965"; reg = <0 0xfeb00000 0 0x80000>; - reg-names = "du"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index 144c0820cf..c727725899 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the ebisu board * @@ -19,7 +19,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -337,6 +337,15 @@ &i2c0 { status = "okay"; + io_expander: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + }; + hdmi-encoder@39 { compatible = "adi,adv7511w"; reg = <0x39>; @@ -398,7 +407,7 @@ }; port@a { - reg = <0xa>; + reg = <10>; adv7482_txa: endpoint { clock-lanes = <0>; @@ -440,6 +449,28 @@ }; }; +&i2c_dvfs { + status = "okay"; + + clock-frequency = <400000>; + + pmic: pmic@30 { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "rohm,bd9571mwv"; + reg = <0x30>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + rohm,ddr-backup-power = <0x1>; + rohm,rstbmode-level; + }; +}; + &lvds0 { status = "okay"; @@ -458,6 +489,13 @@ }; &lvds1 { + /* + * Even though the LVDS1 output is not connected, the encoder must be + * enabled to supply a pixel clock to the DU for the DPAD output when + * LVDS0 is in use. + */ + status = "okay"; + clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; @@ -495,6 +533,11 @@ function = "du"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + pwm3_pins: pwm3 { groups = "pwm3_b"; function = "pwm3"; @@ -650,6 +693,10 @@ status = "okay"; }; +&vin5 { + status = "okay"; +}; + &xhci0 { pinctrl-0 = <&usb30_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi index d2ad665fe2..56cb566ffa 100644 --- a/arch/arm/dts/r8a77990.dtsi +++ b/arch/arm/dts/r8a77990.dtsi @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the R-Car E3 (R8A77990) SoC * @@ -284,6 +284,76 @@ status = "disabled"; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a77990-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a77990-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a77990-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a77990-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77990-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -1656,7 +1726,7 @@ }; csi40: csi2@feaa0000 { - compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2"; + compatible = "renesas,r8a77990-csi2"; reg = <0 0xfeaa0000 0 0x10000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 716>; diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts index db2bed1751..a7dc11e36f 100644 --- a/arch/arm/dts/r8a77995-draak.dts +++ b/arch/arm/dts/r8a77995-draak.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -168,7 +168,6 @@ pinctrl-names = "default"; renesas,no-ether-link; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; status = "okay"; phy0: ethernet-phy@0 { @@ -179,6 +178,18 @@ }; }; +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &du { pinctrl-0 = <&du_pins>; pinctrl-names = "default"; @@ -356,6 +367,13 @@ }; &lvds1 { + /* + * Even though the LVDS1 output is not connected, the encoder must be + * enabled to supply a pixel clock to the DU for the DPAD output when + * LVDS0 is in use. + */ + status = "okay"; + clocks = <&cpg CPG_MOD 727>, <&x12_clk>, <&extal_clk>; @@ -375,6 +393,16 @@ }; }; + can0_pins: can0 { + groups = "can0_data_a"; + function = "can0"; + }; + + can1_pins: can1 { + groups = "can1_data_a"; + function = "can1"; + }; + du_pins: du { groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; function = "du"; diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index a225c24572..2dba1328ac 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -29,6 +29,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { aliases { @@ -86,6 +87,63 @@ }; }; + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + linux,code = <KEY_1>; + label = "SW4-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-2 { + gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + linux,code = <KEY_2>; + label = "SW4-2"; + wakeup-source; + debounce-interval = <20>; + }; + key-3 { + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + label = "SW4-3"; + wakeup-source; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_4>; + label = "SW4-4"; + wakeup-source; + debounce-interval = <20>; + }; + key-a { + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_A>; + label = "TSW0"; + wakeup-source; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + linux,code = <KEY_B>; + label = "TSW1"; + wakeup-source; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; + linux,code = <KEY_C>; + label = "TSW2"; + wakeup-source; + debounce-interval = <20>; + }; + }; + reg_1p8v: regulator0 { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -572,6 +630,11 @@ function = "intc_ex"; }; + keys_pins: keys { + pins = "GP_5_17", "GP_5_20", "GP_5_22"; + bias-pull-up; + }; + pwm1_pins: pwm1 { groups = "pwm1_a"; function = "pwm1"; @@ -719,6 +782,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif1 { pinctrl-0 = <&scif1_pins>; pinctrl-names = "default"; @@ -857,11 +925,6 @@ status = "okay"; }; -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - &xhci0 { pinctrl-0 = <&usb30_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/zynqmp-zc1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 82c30a3fbe..c22de576a5 100644 --- a/arch/arm/dts/zynqmp-zc1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * dts file for Xilinx ZynqMP ZC1275 + * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017 - 2018, Xilinx, Inc. * @@ -14,8 +14,9 @@ #include "zynqmp-clk-ccf.dtsi" / { - model = "ZynqMP ZC1275 RevA"; - compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + model = "ZynqMP ZCU1275 RevA"; + compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", + "xlnx,zynqmp"; aliases { serial0 = &uart0; diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 0473503afa..34c4becd43 100644 --- a/arch/arm/dts/zynqmp-zc1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP ZC1275 RevB + * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018, Xilinx, Inc. * @@ -14,8 +14,9 @@ #include "zynqmp-clk-ccf.dtsi" / { - model = "ZynqMP ZC1275 RevB"; - compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + model = "ZynqMP ZCU1275 RevB"; + compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", + "xlnx,zynqmp"; aliases { serial0 = &uart0; diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index 1652970fbd..546b9f6039 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -62,21 +62,21 @@ void meson_init_reserved_memory(void *fdt) phys_size_t get_effective_memsize(void) { /* Size is reported in MiB, convert it in bytes */ - return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK) - >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M; + return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK) + >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000); } static struct mm_region g12a_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, - .size = 0x80000000UL, + .size = 0xf5000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .virt = 0xf0000000UL, - .phys = 0xf0000000UL, - .size = 0x10000000UL, + .virt = 0xf5000000UL, + .phys = 0xf5000000UL, + .size = 0x0b000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -129,6 +129,7 @@ void meson_eth_init(phy_interface_t mode, unsigned int flags) G12A_ETH_REG_0_TX_RATIO(4) | G12A_ETH_REG_0_PHY_CLK_EN | G12A_ETH_REG_0_CLK_EN); + g12a_enable_external_mdio(); break; case PHY_INTERFACE_MODE_RMII: diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index edf5edcb68..7d01446940 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -129,12 +129,25 @@ static inline void omap_set_fastboot_userdata_size(void) { } #endif /* CONFIG_FASTBOOT_FLASH_MMC */ + +static void omap_set_fastboot_product(void) +{ + const char *board_name; + + board_name = env_get("board_name"); + if (board_name == NULL) + printf("Warning: fastboot.product: unknown board\n"); + + env_set("fastboot.product", board_name); +} + void omap_set_fastboot_vars(void) { omap_set_fastboot_cpu(); omap_set_fastboot_secure(); omap_set_fastboot_board_rev(); omap_set_fastboot_userdata_size(); + omap_set_fastboot_product(); } #endif /* CONFIG_FASTBOOT_FLASH */ diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index aafeb355ef..52ab891425 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -21,6 +21,7 @@ config RCAR_GEN3 imply CMD_GPT imply CMD_UUID imply CMD_MMC_SWRITE if MMC + imply OF_BOARD_SETUP if PCI imply SUPPORT_EMMC_RPMB if MMC imply SPL imply SPL_BOARD_INIT diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 9bb5a5c202..6cf17eb94e 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -65,6 +65,24 @@ config PMUFW_INIT_FILE Include external PMUFW (Platform Management Unit FirmWare) to a Xilinx bootable image (boot.bin). +config ZYNQMP_SPL_PM_CFG_OBJ_FILE + string "PMU firmware configuration object to load at runtime by SPL" + depends on SPL + help + Path to a binary PMU firmware configuration object to be linked + into U-Boot SPL and loaded at runtime into the PMU firmware. + + The ZynqMP Power Management Unit (PMU) needs a configuration + object for most SoC peripherals to work. To have it loaded by + U-Boot SPL set here the file name (absolute path or relative to + the top source tree) of your configuration, which must be a + binary blob. It will be linked in the SPL binary and loaded + into the PMU firmware by U-Boot SPL during board + initialization. + + Leave this option empty if your PMU firmware has a hard-coded + configuration object or you are loading it by any other means. + config ZYNQMP_USB bool "Configure ZynqMP USB" diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 8a3b074724..f3765e45b1 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -8,3 +8,7 @@ obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o + +ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"") +obj-$(CONFIG_SPL_BUILD) += pmu_ipc.o +endif diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 385c8825f2..915badc6fb 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -72,4 +72,6 @@ int chip_id(unsigned char id); void tcm_init(u8 mode); #endif +void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-zynqmp/pmu_ipc.c b/arch/arm/mach-zynqmp/pmu_ipc.c new file mode 100644 index 0000000000..d8858ea3ff --- /dev/null +++ b/arch/arm/mach-zynqmp/pmu_ipc.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Inter-Processor Communication with the Platform Management Unit (PMU) + * firmware. + * + * (C) Copyright 2019 Luca Ceresoli + * Luca Ceresoli <luca@lucaceresoli.net> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> + +/* IPI bitmasks, register base and register offsets */ +#define IPI_BIT_MASK_APU 0x00001 +#define IPI_BIT_MASK_PMU0 0x10000 +#define IPI_REG_BASE_APU 0xFF300000 +#define IPI_REG_BASE_PMU0 0xFF330000 +#define IPI_REG_OFFSET_TRIG 0x00 +#define IPI_REG_OFFSET_OBR 0x04 + +/* IPI mailbox buffer offsets */ +#define IPI_BUF_BASE_APU 0xFF990400 +#define IPI_BUF_OFFSET_TARGET_PMU 0x1C0 +#define IPI_BUF_OFFSET_REQ 0x00 +#define IPI_BUF_OFFSET_RESP 0x20 + +#define PMUFW_PAYLOAD_ARG_CNT 8 + +/* PMUFW commands */ +#define PMUFW_CMD_SET_CONFIGURATION 2 + +static void pmu_ipc_send_request(const u32 *req, size_t req_len) +{ + u32 *mbx = (u32 *)(IPI_BUF_BASE_APU + + IPI_BUF_OFFSET_TARGET_PMU + + IPI_BUF_OFFSET_REQ); + size_t i; + + for (i = 0; i < req_len; i++) + writel(req[i], &mbx[i]); +} + +static void pmu_ipc_read_response(unsigned int *value, size_t count) +{ + u32 *mbx = (u32 *)(IPI_BUF_BASE_APU + + IPI_BUF_OFFSET_TARGET_PMU + + IPI_BUF_OFFSET_RESP); + size_t i; + + for (i = 0; i < count; i++) + value[i] = readl(&mbx[i]); +} + +/** + * Send request to PMU and get the response. + * + * @req: Request buffer. Byte 0 is the API ID, other bytes are optional + * parameters. + * @req_len: Request length in number of 32-bit words. + * @res: Response buffer. Byte 0 is the error code, other bytes are + * optional parameters. Optional, if @res_maxlen==0 the parameters + * will not be read. + * @res_maxlen: Space allocated for the response in number of 32-bit words. + * + * @return Error code returned by the PMU (i.e. the first word of the response) + */ +static int pmu_ipc_request(const u32 *req, size_t req_len, + u32 *res, size_t res_maxlen) +{ + u32 status; + + if (req_len > PMUFW_PAYLOAD_ARG_CNT || + res_maxlen > PMUFW_PAYLOAD_ARG_CNT) + return -EINVAL; + + pmu_ipc_send_request(req, req_len); + + /* Raise Inter-Processor Interrupt to PMU and wait for response */ + writel(IPI_BIT_MASK_PMU0, IPI_REG_BASE_APU + IPI_REG_OFFSET_TRIG); + do { + status = readl(IPI_REG_BASE_APU + IPI_REG_OFFSET_OBR); + } while (status & IPI_BIT_MASK_PMU0); + + pmu_ipc_read_response(res, res_maxlen); + + return 0; +} + +/** + * Send a configuration object to the PMU firmware. + * + * @cfg_obj: Pointer to the configuration object + * @size: Size of @cfg_obj in bytes + */ +void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) +{ + const u32 request[] = { + PMUFW_CMD_SET_CONFIGURATION, + (u32)((u64)cfg_obj) + }; + u32 response; + int err; + + printf("Loading PMUFW cfg obj (%ld bytes)\n", size); + + err = pmu_ipc_request(request, ARRAY_SIZE(request), &response, 1); + if (err) + panic("Cannot load PMUFW configuration object (%d)\n", err); + if (response != 0) + panic("PMUFW returned 0x%08x status!\n", response); +} diff --git a/board/amlogic/w400/MAINTAINERS b/board/amlogic/w400/MAINTAINERS new file mode 100644 index 0000000000..6e68fa73f7 --- /dev/null +++ b/board/amlogic/w400/MAINTAINERS @@ -0,0 +1,6 @@ +W400 +M: Neil Armstrong <narmstrong@baylibre.com> +S: Maintained +L: u-boot-amlogic@groups.io +F: board/amlogic/w400/ +F: configs/odroid-n2_defconfig diff --git a/board/amlogic/w400/Makefile b/board/amlogic/w400/Makefile new file mode 100644 index 0000000000..fac4a73afa --- /dev/null +++ b/board/amlogic/w400/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2019 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> + +obj-y := w400.o diff --git a/board/amlogic/w400/README.odroid-n2 b/board/amlogic/w400/README.odroid-n2 new file mode 100644 index 0000000000..a8f2c3d7da --- /dev/null +++ b/board/amlogic/w400/README.odroid-n2 @@ -0,0 +1,130 @@ +U-Boot for ODROID-N2 +==================== + +ODROID-N2 is a single board computer manufactured by Hardkernel +Co. Ltd with the following specifications: + + - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC + - 4GB DDR4 SDRAM + - Gigabit Ethernet + - HDMI 2.1 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 3.0 Host, 1 x USB OTG + - eMMC, microSD + - Infrared receiver + +Schematics are available on the manufacturer website. + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - ADC + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make odroid-n2_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + + > DIR=odroid-n2 + > git clone --depth 1 \ + https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \ + $DIR + + > cd odroid-n2 + > make odroidn2_defconfig + > make + > export UBOOTDIR=$PWD + + Go back to mainline U-Boot source tree then : + > mkdir fip + + > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + > cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/ + > cp $UBOOTDIR/fip/g12b/bl2.bin fip/ + > cp $UBOOTDIR/fip/g12b/bl30.bin fip/ + > cp $UBOOTDIR/fip/g12b/bl31.img fip/ + > cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/ + > cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/ + > cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/ + > cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/ + > cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/ + > cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/ + > cp $UBOOTDIR/fip/g12b/piei.fw fip/ + > cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/ + > cp u-boot.bin fip/bl33.bin + + > sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 --compress lz4 + > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --ddrfw8 fip/aml_ddr.fw \ + --level v3 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/README.w400 b/board/amlogic/w400/README.w400 new file mode 100644 index 0000000000..25b786d817 --- /dev/null +++ b/board/amlogic/w400/README.w400 @@ -0,0 +1,130 @@ +U-Boot for Amlogic W400 +======================= + +U200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC + - 2GB DDR4 SDRAM + - 10/100 Ethernet (Internal PHY) + - 1 x USB 3.0 Host + - eMMC + - SDcard + - Infrared receiver + - SDIO WiFi Module + - MIPI DSI Connector + - Audio HAT Connector + - PCI-E M.2 Connector + +Schematics are available from Amlogic on demand. + +Currently the u-boot port supports the following devices: + - serial + - Ethernet + - Regulators + - Clock controller + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make w400_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot + > cd amlogic-u-boot + > make g12b_w400_v1_defconfig + > make + > export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz + > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader + > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 + > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + > cp $UBOOTDIR/build/board/amlogic/g12b_w400_v1/firmware/acs.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12b/bl2.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12b/bl30.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12b/bl31.img fip/ + > cp $FIPDIR/g12b/ddr3_1d.fw fip/ + > cp $FIPDIR/g12b/ddr4_1d.fw fip/ + > cp $FIPDIR/g12b/ddr4_2d.fw fip/ + > cp $FIPDIR/g12b/diag_lpddr4.fw fip/ + > cp $FIPDIR/g12b/lpddr4_1d.fw fip/ + > cp $FIPDIR/g12b/lpddr4_2d.fw fip/ + > cp $FIPDIR/g12b/piei.fw fip/ + > cp $FIPDIR/g12b/aml_ddr.fw fip/ + > cp u-boot.bin fip/bl33.bin + + > sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + > $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + > $FIPDIR/g12b/aml_encrypt_g12b --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --ddrfw8 fip/aml_ddr.fw \ + --level v3 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/w400.c b/board/amlogic/w400/w400.c new file mode 100644 index 0000000000..4737865367 --- /dev/null +++ b/board/amlogic/w400/w400.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <dm.h> +#include <environment.h> +#include <asm/io.h> +#include <asm/arch/eth.h> + +int misc_init_r(void) +{ + meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); + + return 0; +} diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index fcf9334ba9..2d5710076d 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -215,29 +215,21 @@ static const struct pinmux_config gpio_pins[] = { }; const struct pinmux_resource pinmuxes[] = { -#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_DRIVER_TI_EMAC PINMUX_ITEM(emac_pins_mdio), #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII PINMUX_ITEM(emac_pins_rmii), #else PINMUX_ITEM(emac_pins_mii), -#endif /* CONFIG_DRIVER_TI_EMAC */ -#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ -#endif /* CONFIG_SPL_BUILD */ +#endif +#endif #ifdef CONFIG_SPI_FLASH -#if !CONFIG_IS_ENABLED(PINCTRL) PINMUX_ITEM(spi1_pins_base), PINMUX_ITEM(spi1_pins_scs0), #endif -#endif -#if !CONFIG_IS_ENABLED(PINCTRL) PINMUX_ITEM(uart2_pins_txrx), PINMUX_ITEM(uart2_pins_rtscts), -#endif -#if !CONFIG_IS_ENABLED(PINCTRL) PINMUX_ITEM(i2c0_pins), -#endif #ifdef CONFIG_NAND_DAVINCI PINMUX_ITEM(emifa_pins_cs3), PINMUX_ITEM(emifa_pins_cs4), @@ -248,10 +240,8 @@ const struct pinmux_resource pinmuxes[] = { #endif PINMUX_ITEM(gpio_pins), #ifdef CONFIG_MMC_DAVINCI -#if !CONFIG_IS_ENABLED(PINCTRL) PINMUX_ITEM(mmc0_pins), #endif -#endif }; const int pinmuxes_size = ARRAY_SIZE(pinmuxes); @@ -300,9 +290,6 @@ u32 get_board_rev(void) rev = 2; else if (maxcpuclk >= 372000000) rev = 1; -#ifdef CONFIG_DA850_AM18X_EVM - rev |= REV_AM18X_EVM; -#endif return rev; } diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 292867e496..37f8a46d7e 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -8,6 +8,8 @@ */ #include <common.h> +#include <dm.h> +#include <dm/uclass-internal.h> #include <asm/arch/rmobile.h> #ifdef CONFIG_RCAR_GEN3 @@ -46,4 +48,51 @@ int dram_init_banksize(void) return 0; } + +#if CONFIG_IS_ENABLED(OF_BOARD_SETUP) && CONFIG_IS_ENABLED(PCI) +int ft_board_setup(void *blob, bd_t *bd) +{ + struct udevice *dev; + struct uclass *uc; + fdt_addr_t regs_addr; + int i, off, ret; + + ret = uclass_get(UCLASS_PCI, &uc); + if (ret) + return ret; + + uclass_foreach_dev(dev, uc) { + struct pci_controller hose = { 0 }; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (hose.region_count == MAX_PCI_REGIONS) { + printf("maximum number of regions parsed, aborting\n"); + break; + } + + if (bd->bi_dram[i].size) { + pci_set_region(&hose.regions[hose.region_count++], + bd->bi_dram[i].start, + bd->bi_dram[i].start, + bd->bi_dram[i].size, + PCI_REGION_MEM | + PCI_REGION_PREFETCH | + PCI_REGION_SYS_MEMORY); + } + } + + regs_addr = devfdt_get_addr_index(dev, 0); + off = fdt_node_offset_by_compat_reg(blob, + "renesas,pcie-rcar-gen3", regs_addr); + if (off < 0) { + printf("Failed to find PCIe node@%llx\n", regs_addr); + return off; + } + + fdt_pci_dma_ranges(blob, off, &hose); + } + + return 0; +} +#endif #endif diff --git a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c new file mode 100644 index 0000000000..d4f0ee796f --- /dev/null +++ b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) Xilinx, Inc. + */ + +#include <asm/arch/ps7_init_gpl.h> + +static unsigned long ps7_pll_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000002U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000004U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U), + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U), + EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U), + EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U), + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data[] = { + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U), + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU), + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U), + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U), + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U), + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU), + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U), + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U), + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U), + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU), + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U), + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U), + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U), + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU), + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU), + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U), + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU), + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU), + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U), + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U), + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U), + EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0xF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U), + EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U), + EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U), + EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U), + EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U), + EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U), + EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U), + EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U), + EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U), + EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U), + EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U), + EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U), + EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U), + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U), + EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U), + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + return PS7_INIT_SUCCESS; +} diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index efc1d356d6..04fc7f32fe 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -7,3 +7,9 @@ F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp* F: configs/xilinx_zynqmp* F: configs/avnet_ultra96_rev1_defconfig + +ARM ZYNQMP AVNET ULTRAZED EV BOARD +M: Luca Ceresoli <luca@lucaceresoli.net> +S: Maintained +F: arch/arm/dts/avnet-ultrazedev-* +F: configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 80f8ca7e1e..5ace6cc1b4 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -33,6 +33,13 @@ ifneq ($(call ifdef_any_of, CONFIG_ZYNQMP_PSU_INIT_ENABLED CONFIG_SPL_BUILD),) obj-y += $(init-objs) endif +ifdef CONFIG_SPL_BUILD +ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"") +obj-$(CONFIG_SPL_BUILD) += pm_cfg_obj.o +$(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE)) FORCE +endif +endif + obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o ifndef CONFIG_SPL_BUILD diff --git a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c new file mode 100644 index 0000000000..ac3f716392 --- /dev/null +++ b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U); + psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U); + psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U); + psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); + psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U); + psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U); + mask_delay(1); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U); + mask_delay(5); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + Xil_Out32(0xFD080200U, 0x100091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/pm_cfg_obj.S b/board/xilinx/zynqmp/pm_cfg_obj.S new file mode 100644 index 0000000000..c4ca77e396 --- /dev/null +++ b/board/xilinx/zynqmp/pm_cfg_obj.S @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +.section .rodata + +.global zynqmp_pm_cfg_obj +.type zynqmp_pm_cfg_obj, @object +.global zynqmp_pm_cfg_obj_size +.type zynqmp_pm_cfg_obj_size, @object + +zynqmp_pm_cfg_obj: +.align 4 +.incbin CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE + +zynqmp_pm_cfg_obj_end: + +zynqmp_pm_cfg_obj_size: +.int zynqmp_pm_cfg_obj_end - zynqmp_pm_cfg_obj diff --git a/board/xilinx/zynqmp/pm_cfg_obj.h b/board/xilinx/zynqmp/pm_cfg_obj.h new file mode 100644 index 0000000000..86e785490c --- /dev/null +++ b/board/xilinx/zynqmp/pm_cfg_obj.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Luca Ceresoli <luca@lucaceresoli.net> + * + * Declaration of PMU config object binary blob linked in at build time. + */ + +extern const u32 zynqmp_pm_cfg_obj[]; +extern const int zynqmp_pm_cfg_obj_size; diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h index c476c902eb..1c1bf32ada 100644 --- a/board/xilinx/zynqmp/xil_io.h +++ b/board/xilinx/zynqmp/xil_io.h @@ -9,17 +9,17 @@ #define xil_printf(...) -void Xil_Out32(unsigned long addr, unsigned long val) +static void Xil_Out32(unsigned long addr, unsigned long val) { writel(val, addr); } -int Xil_In32(unsigned long addr) +static int Xil_In32(unsigned long addr) { return readl(addr); } -void usleep(u32 sleep) +static void __maybe_unused usleep(u32 sleep) { udelay(sleep); } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index c840e92d9c..057ca1fbf7 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -22,6 +22,8 @@ #include <zynqmppl.h> #include <g_dnl.h> +#include "pm_cfg_obj.h" + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ @@ -327,6 +329,13 @@ int board_early_init_f(void) int board_init(void) { +#if defined(CONFIG_SPL_BUILD) + /* Check *at build time* if the filename is an non-empty string */ + if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) + zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, + zynqmp_pm_cfg_obj_size); +#endif + printf("EL Level:\tEL%d\n", current_el()); #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ diff --git a/cmd/Kconfig b/cmd/Kconfig index 16cb5c2956..22a3737b4e 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -101,7 +101,14 @@ config AUTOBOOT_PROMPT config AUTOBOOT_ENCRYPTION bool "Enable encryption in autoboot stopping" depends on AUTOBOOT_KEYED - default n + help + This option allows a string to be entered into U-Boot to stop the + autoboot. The string itself is hashed and compared against the hash + in the environment variable 'bootstopkeysha256'. If it matches then + boot stops and a command-line prompt is presented. + + This provides a way to ship a secure production device which can also + be accessed at the U-Boot command line. config AUTOBOOT_DELAY_STR string "Delay autobooting via specific input key / string" @@ -146,6 +153,31 @@ config AUTOBOOT_STOP_STR_SHA256 string / password matches a values that is encypted via a SHA256 hash and saved in the environment. +config AUTOBOOT_USE_MENUKEY + bool "Allow a specify key to run a menu from the environment" + depends on !AUTOBOOT_KEYED + help + If a specific key is pressed to stop autoboot, then the commands in + the environment variable 'menucmd' are executed before boot starts. + +config AUTOBOOT_MENUKEY + int "ASCII value of boot key to show a menu" + default 0 + depends on AUTOBOOT_USE_MENUKEY + help + If this key is pressed to stop autoboot, then the commands in the + environment variable 'menucmd' will be executed before boot starts. + For example, 33 means "!" in ASCII, so pressing ! at boot would take + this action. + +config AUTOBOOT_MENU_SHOW + bool "Show a menu on boot" + help + This enables the boot menu, controlled by environment variables + defined by the board. The menu starts after running the 'preboot' + environmnent variable (if enabled) and before handling the boot delay. + See README.bootmenu for more details. + endmenu config BUILD_BIN2C diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index f576e226ee..86c17dc427 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -328,7 +328,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, print_num("reloc off", gd->reloc_off); print_num("irq_sp", gd->irq_sp); /* irq stack pointer */ print_num("sp start ", gd->start_addr_sp); -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) +#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) print_num("FB base ", gd->fb_base); #endif /* diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c index 7f88c1ed63..0ae9d5a681 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c @@ -472,7 +472,7 @@ void menu_display_statusline(struct menu *m) puts(ANSI_CLEAR_LINE); } -#ifdef CONFIG_MENU_SHOW +#ifdef CONFIG_AUTOBOOT_MENU_SHOW int menu_show(int bootdelay) { bootmenu_show(bootdelay); diff --git a/cmd/fpga.c b/cmd/fpga.c index bc48abdd6d..eba989a730 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -458,7 +458,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper, "0-device key, 1-user key, 2-no encryption.\n" "The optional Userkey address specifies from which address key\n" "has to be used for decryption if user key is selected.\n" - "NOTE: the sceure bitstream has to be created using xilinx\n" + "NOTE: the secure bitstream has to be created using Xilinx\n" "bootgen tool only.\n" #endif ); diff --git a/common/Kconfig b/common/Kconfig index b556b59e9f..28d5e9a0cc 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -125,6 +125,168 @@ config BOOTSTAGE_STASH_SIZE This should be large enough to hold the bootstage stash. A value of 4096 (4KiB) is normally plenty. +config SHOW_BOOT_PROGRESS + bool "Show boot progress in a board-specific manner" + help + Defining this option allows to add some board-specific code (calling + a user-provided function show_boot_progress(int) that enables you to + show the system's boot progress on some display (for example, some + LEDs) on your board. At the moment, the following checkpoints are + implemented: + + Legacy uImage format: + + Arg Where When + 1 common/cmd_bootm.c before attempting to boot an image + -1 common/cmd_bootm.c Image header has bad magic number + 2 common/cmd_bootm.c Image header has correct magic number + -2 common/cmd_bootm.c Image header has bad checksum + 3 common/cmd_bootm.c Image header has correct checksum + -3 common/cmd_bootm.c Image data has bad checksum + 4 common/cmd_bootm.c Image data has correct checksum + -4 common/cmd_bootm.c Image is for unsupported architecture + 5 common/cmd_bootm.c Architecture check OK + -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi) + 6 common/cmd_bootm.c Image Type check OK + -6 common/cmd_bootm.c gunzip uncompression error + -7 common/cmd_bootm.c Unimplemented compression type + 7 common/cmd_bootm.c Uncompression OK + 8 common/cmd_bootm.c No uncompress/copy overwrite error + -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX) + + 9 common/image.c Start initial ramdisk verification + -10 common/image.c Ramdisk header has bad magic number + -11 common/image.c Ramdisk header has bad checksum + 10 common/image.c Ramdisk header is OK + -12 common/image.c Ramdisk data has bad checksum + 11 common/image.c Ramdisk data has correct checksum + 12 common/image.c Ramdisk verification complete, start loading + -13 common/image.c Wrong Image Type (not PPC Linux ramdisk) + 13 common/image.c Start multifile image verification + 14 common/image.c No initial ramdisk, no multifile, continue. + + 15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS + + -30 arch/powerpc/lib/board.c Fatal error, hang the system + -31 post/post.c POST test failed, detected by post_output_backlog() + -32 post/post.c POST test failed, detected by post_run_single() + + 34 common/cmd_doc.c before loading a Image from a DOC device + -35 common/cmd_doc.c Bad usage of "doc" command + 35 common/cmd_doc.c correct usage of "doc" command + -36 common/cmd_doc.c No boot device + 36 common/cmd_doc.c correct boot device + -37 common/cmd_doc.c Unknown Chip ID on boot device + 37 common/cmd_doc.c correct chip ID found, device available + -38 common/cmd_doc.c Read Error on boot device + 38 common/cmd_doc.c reading Image header from DOC device OK + -39 common/cmd_doc.c Image header has bad magic number + 39 common/cmd_doc.c Image header has correct magic number + -40 common/cmd_doc.c Error reading Image from DOC device + 40 common/cmd_doc.c Image header has correct magic number + 41 common/cmd_ide.c before loading a Image from a IDE device + -42 common/cmd_ide.c Bad usage of "ide" command + 42 common/cmd_ide.c correct usage of "ide" command + -43 common/cmd_ide.c No boot device + 43 common/cmd_ide.c boot device found + -44 common/cmd_ide.c Device not available + 44 common/cmd_ide.c Device available + -45 common/cmd_ide.c wrong partition selected + 45 common/cmd_ide.c partition selected + -46 common/cmd_ide.c Unknown partition table + 46 common/cmd_ide.c valid partition table found + -47 common/cmd_ide.c Invalid partition type + 47 common/cmd_ide.c correct partition type + -48 common/cmd_ide.c Error reading Image Header on boot device + 48 common/cmd_ide.c reading Image Header from IDE device OK + -49 common/cmd_ide.c Image header has bad magic number + 49 common/cmd_ide.c Image header has correct magic number + -50 common/cmd_ide.c Image header has bad checksum + 50 common/cmd_ide.c Image header has correct checksum + -51 common/cmd_ide.c Error reading Image from IDE device + 51 common/cmd_ide.c reading Image from IDE device OK + 52 common/cmd_nand.c before loading a Image from a NAND device + -53 common/cmd_nand.c Bad usage of "nand" command + 53 common/cmd_nand.c correct usage of "nand" command + -54 common/cmd_nand.c No boot device + 54 common/cmd_nand.c boot device found + -55 common/cmd_nand.c Unknown Chip ID on boot device + 55 common/cmd_nand.c correct chip ID found, device available + -56 common/cmd_nand.c Error reading Image Header on boot device + 56 common/cmd_nand.c reading Image Header from NAND device OK + -57 common/cmd_nand.c Image header has bad magic number + 57 common/cmd_nand.c Image header has correct magic number + -58 common/cmd_nand.c Error reading Image from NAND device + 58 common/cmd_nand.c reading Image from NAND device OK + + -60 common/env_common.c Environment has a bad CRC, using default + + 64 net/eth.c starting with Ethernet configuration. + -64 net/eth.c no Ethernet found. + 65 net/eth.c Ethernet found. + + -80 common/cmd_net.c usage wrong + 80 common/cmd_net.c before calling net_loop() + -81 common/cmd_net.c some error in net_loop() occurred + 81 common/cmd_net.c net_loop() back without error + -82 common/cmd_net.c size == 0 (File with size 0 loaded) + 82 common/cmd_net.c trying automatic boot + 83 common/cmd_net.c running "source" command + -83 common/cmd_net.c some error in automatic boot or "source" command + 84 common/cmd_net.c end without errors + + FIT uImage format: + + Arg Where When + 100 common/cmd_bootm.c Kernel FIT Image has correct format + -100 common/cmd_bootm.c Kernel FIT Image has incorrect format + 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration + -101 common/cmd_bootm.c Can't get configuration for kernel subimage + 102 common/cmd_bootm.c Kernel unit name specified + -103 common/cmd_bootm.c Can't get kernel subimage node offset + 103 common/cmd_bootm.c Found configuration node + 104 common/cmd_bootm.c Got kernel subimage node offset + -104 common/cmd_bootm.c Kernel subimage hash verification failed + 105 common/cmd_bootm.c Kernel subimage hash verification OK + -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture + 106 common/cmd_bootm.c Architecture check OK + -106 common/cmd_bootm.c Kernel subimage has wrong type + 107 common/cmd_bootm.c Kernel subimage type OK + -107 common/cmd_bootm.c Can't get kernel subimage data/size + 108 common/cmd_bootm.c Got kernel subimage data/size + -108 common/cmd_bootm.c Wrong image type (not legacy, FIT) + -109 common/cmd_bootm.c Can't get kernel subimage type + -110 common/cmd_bootm.c Can't get kernel subimage comp + -111 common/cmd_bootm.c Can't get kernel subimage os + -112 common/cmd_bootm.c Can't get kernel subimage load address + -113 common/cmd_bootm.c Image uncompress/copy overwrite error + + 120 common/image.c Start initial ramdisk verification + -120 common/image.c Ramdisk FIT image has incorrect format + 121 common/image.c Ramdisk FIT image has correct format + 122 common/image.c No ramdisk subimage unit name, using configuration + -122 common/image.c Can't get configuration for ramdisk subimage + 123 common/image.c Ramdisk unit name specified + -124 common/image.c Can't get ramdisk subimage node offset + 125 common/image.c Got ramdisk subimage node offset + -125 common/image.c Ramdisk subimage hash verification failed + 126 common/image.c Ramdisk subimage hash verification OK + -126 common/image.c Ramdisk subimage for unsupported architecture + 127 common/image.c Architecture check OK + -127 common/image.c Can't get ramdisk subimage data/size + 128 common/image.c Got ramdisk subimage data/size + 129 common/image.c Can't get ramdisk load address + -129 common/image.c Got ramdisk load address + + -130 common/cmd_doc.c Incorrect FIT image format + 131 common/cmd_doc.c FIT image format OK + + -140 common/cmd_ide.c Incorrect FIT image format + 141 common/cmd_ide.c FIT image format OK + + -150 common/cmd_nand.c Incorrect FIT image format + 151 common/cmd_nand.c FIT image format OK + endmenu menu "Boot media" diff --git a/common/autoboot.c b/common/autoboot.c index 94133eaeda..42fbd7614a 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -10,6 +10,7 @@ #include <cli.h> #include <console.h> #include <fdtdec.h> +#include <hash.h> #include <menu.h> #include <post.h> #include <u-boot/sha256.h> @@ -27,9 +28,19 @@ DECLARE_GLOBAL_DATA_PTR; /* Stored value of bootdelay, used by autoboot_command() */ static int stored_bootdelay; +static int menukey; + +#ifdef CONFIG_AUTOBOOT_ENCRYPTION +#define AUTOBOOT_STOP_STR_SHA256 CONFIG_AUTOBOOT_STOP_STR_SHA256 +#else +#define AUTOBOOT_STOP_STR_SHA256 "" +#endif -#if defined(CONFIG_AUTOBOOT_KEYED) -#if defined(CONFIG_AUTOBOOT_STOP_STR_SHA256) +#ifdef CONFIG_USE_AUTOBOOT_MENUKEY +#define AUTOBOOT_MENUKEY CONFIG_USE_AUTOBOOT_MENUKEY +#else +#define AUTOBOOT_MENUKEY 0 +#endif /* * Use a "constant-length" time compare function for this @@ -48,7 +59,15 @@ static int slow_equals(u8 *a, u8 *b, int len) return diff == 0; } -static int passwd_abort(uint64_t etime) +/** + * passwd_abort_sha256() - check for a hashed key sequence to abort booting + * + * This checks for the user entering a SHA256 hash within a given time. + * + * @etime: Timeout value ticks (stop when get_ticks() reachs this) + * @return 0 if autoboot should continue, 1 if it should stop + */ +static int passwd_abort_sha256(uint64_t etime) { const char *sha_env_str = env_get("bootstopkeysha256"); u8 sha_env[SHA256_SUM_LEN]; @@ -61,7 +80,7 @@ static int passwd_abort(uint64_t etime) int ret; if (sha_env_str == NULL) - sha_env_str = CONFIG_AUTOBOOT_STOP_STR_SHA256; + sha_env_str = AUTOBOOT_STOP_STR_SHA256; /* * Generate the binary value from the environment hash value @@ -99,8 +118,16 @@ static int passwd_abort(uint64_t etime) return abort; } -#else -static int passwd_abort(uint64_t etime) + +/** + * passwd_abort_key() - check for a key sequence to aborted booting + * + * This checks for the user entering a string within a given time. + * + * @etime: Timeout value ticks (stop when get_ticks() reachs this) + * @return 0 if autoboot should continue, 1 if it should stop + */ +static int passwd_abort_key(uint64_t etime) { int abort = 0; struct { @@ -176,13 +203,12 @@ static int passwd_abort(uint64_t etime) return abort; } -#endif /*************************************************************************** * Watch for 'delay' seconds for autoboot stop or autoboot delay string. * returns: 0 - no key string, allow autoboot 1 - got key string, abort */ -static int __abortboot(int bootdelay) +static int abortboot_key_sequence(int bootdelay) { int abort; uint64_t etime = endtick(bootdelay); @@ -195,29 +221,22 @@ static int __abortboot(int bootdelay) printf(CONFIG_AUTOBOOT_PROMPT, bootdelay); # endif - abort = passwd_abort(etime); + if (IS_ENABLED(CONFIG_AUTOBOOT_ENCRYPTION)) + abort = passwd_abort_sha256(etime); + else + abort = passwd_abort_key(etime); if (!abort) debug_bootkeys("key timeout\n"); return abort; } -# else /* !defined(CONFIG_AUTOBOOT_KEYED) */ - -#ifdef CONFIG_MENUKEY -static int menukey; -#endif - -static int __abortboot(int bootdelay) +static int abortboot_single_key(int bootdelay) { int abort = 0; unsigned long ts; -#ifdef CONFIG_MENUPROMPT - printf(CONFIG_MENUPROMPT); -#else printf("Hit any key to stop autoboot: %2d ", bootdelay); -#endif /* * Check if key already pressed @@ -234,13 +253,13 @@ static int __abortboot(int bootdelay) ts = get_timer(0); do { if (tstc()) { /* we got a key press */ + int key; + abort = 1; /* don't auto boot */ bootdelay = 0; /* no more delay */ -# ifdef CONFIG_MENUKEY - menukey = getc(); -# else - (void) getc(); /* consume input */ -# endif + key = getc(); /* consume input */ + if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY)) + menukey = key; break; } udelay(10000); @@ -253,26 +272,27 @@ static int __abortboot(int bootdelay) return abort; } -# endif /* CONFIG_AUTOBOOT_KEYED */ static int abortboot(int bootdelay) { int abort = 0; - if (bootdelay >= 0) - abort = __abortboot(bootdelay); + if (bootdelay >= 0) { + if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED)) + abort = abortboot_key_sequence(bootdelay); + else + abort = abortboot_single_key(bootdelay); + } -#ifdef CONFIG_SILENT_CONSOLE - if (abort) + if (IS_ENABLED(CONFIG_SILENT_CONSOLE) && abort) gd->flags &= ~GD_FLG_SILENT; -#endif return abort; } static void process_fdt_options(const void *blob) { -#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_SYS_TEXT_BASE) +#ifdef CONFIG_SYS_TEXT_BASE ulong addr; /* Add an env variable to point to a kernel payload, if available */ @@ -284,7 +304,7 @@ static void process_fdt_options(const void *blob) addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0); if (addr) env_set_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr)); -#endif /* CONFIG_OF_CONTROL && CONFIG_SYS_TEXT_BASE */ +#endif /* CONFIG_SYS_TEXT_BASE */ } const char *bootdelay_process(void) @@ -297,16 +317,14 @@ const char *bootdelay_process(void) s = env_get("bootdelay"); bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; -#ifdef CONFIG_OF_CONTROL - bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", - bootdelay); -#endif + if (IS_ENABLED(CONFIG_OF_CONTROL)) + bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", + bootdelay); debug("### main_loop entered: bootdelay=%d\n\n", bootdelay); -#if defined(CONFIG_MENU_SHOW) - bootdelay = menu_show(bootdelay); -#endif + if (IS_ENABLED(CONFIG_AUTOBOOT_MENU_SHOW)) + bootdelay = menu_show(bootdelay); bootretry_init_cmd_timeout(); #ifdef CONFIG_POST @@ -319,7 +337,8 @@ const char *bootdelay_process(void) else s = env_get("bootcmd"); - process_fdt_options(gd->fdt_blob); + if (IS_ENABLED(CONFIG_OF_CONTROL)) + process_fdt_options(gd->fdt_blob); stored_bootdelay = bootdelay; return s; @@ -330,22 +349,24 @@ void autoboot_command(const char *s) debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>"); if (stored_bootdelay != -1 && s && !abortboot(stored_bootdelay)) { -#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) - int prev = disable_ctrlc(1); /* disable Control C checking */ -#endif + bool lock; + int prev; + + lock = IS_ENABLED(CONFIG_AUTOBOOT_KEYED) && + !IS_ENABLED(CONFIG_AUTOBOOT_KEYED_CTRLC); + if (lock) + prev = disable_ctrlc(1); /* disable Ctrl-C checking */ run_command_list(s, -1, 0); -#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC) - disable_ctrlc(prev); /* restore Control C checking */ -#endif + if (lock) + disable_ctrlc(prev); /* restore Ctrl-C checking */ } -#ifdef CONFIG_MENUKEY - if (menukey == CONFIG_MENUKEY) { + if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY) && + menukey == AUTOBOOT_MENUKEY) { s = env_get("menucmd"); if (s) run_command_list(s, -1, 0); } -#endif /* CONFIG_MENUKEY */ } diff --git a/common/edid.c b/common/edid.c index f244d26e04..f99f42dc40 100644 --- a/common/edid.c +++ b/common/edid.c @@ -202,7 +202,9 @@ int edid_get_timing_validate(u8 *buf, int buf_size, timing); else timing_done = true; - break; + + if (timing_done) + break; } } if (!timing_done) diff --git a/common/main.c b/common/main.c index 07b34bf2b0..ce39c8d189 100644 --- a/common/main.c +++ b/common/main.c @@ -19,7 +19,6 @@ __weak void show_boot_progress(int val) {} static void run_preboot_environment_command(void) { -#ifdef CONFIG_PREBOOT char *p; p = env_get("preboot"); @@ -34,7 +33,6 @@ static void run_preboot_environment_command(void) if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED)) disable_ctrlc(prev); /* restore Ctrl-C checking */ } -#endif /* CONFIG_PREBOOT */ } /* We come here after U-Boot is initialised and ready to process commands */ @@ -49,7 +47,8 @@ void main_loop(void) cli_init(); - run_preboot_environment_command(); + if (IS_ENABLED(CONFIG_USE_PREBOOT)) + run_preboot_environment_command(); if (IS_ENABLED(CONFIG_UPDATE_TFTP)) update_tftp(0UL, NULL, NULL); diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index a986bf880e..9eea922d10 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -11,6 +11,7 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 26c927ffde..d92a70e4d0 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC1_CD_PIN="PG13" CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index 1d48214aa4..da80d35054 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="PB10" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 63c8a2a895..dfd439a52e 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index b00fcf34fd..298c9f2072 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -13,6 +13,7 @@ CONFIG_SATAPWR="PC3" CONFIG_SPL_SPI_SUNXI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index db1c25c6f8..084dab0ceb 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -11,6 +11,7 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index e1e72ed3a3..ffeeda414e 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -9,6 +9,7 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index 62d878f404..f4c6c54cfd 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -11,6 +11,7 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 29efaf6bc4..440eebbeec 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -12,6 +12,7 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index 59dfdcc407..48c4c3e53a 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -13,6 +13,7 @@ CONFIG_USB0_VBUS_DET="PH5" CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index c41e4356a4..193e20aa8b 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -13,6 +13,7 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index 38cc65bd5c..42a73c8057 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -12,6 +12,7 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index 4389856987..6ea4238342 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PB2" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index c44050f899..9b7f19736c 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 0a2774761e..1810d48a0b 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index c0fb54749e..2dc6c8d8e2 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index ae320b7033..4395d5b724 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 384820d939..40b60599d5 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra" diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 86cc3a2f04..abd7d3d125 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -9,6 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index 87e2d34e4d..b4f3794153 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -10,6 +10,7 @@ CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 8636eab238..c5d33a2e14 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -11,6 +11,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index 95c564c407..78681084ba 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 6cd500f3be..82994212a2 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index d1ba5c87b7..65b6777e0e 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index acd931c910..39caa75ff3 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 5e52388e7e..9065792149 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23" CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24" CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index d1ff8fd116..ee5412cdb8 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index 013482094f..e44d79e0c2 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -12,6 +12,7 @@ CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" CONFIG_AXP_GPIO=y +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 1ff72708dd..593dbe86a1 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index ed8fbe9f2a..fe92f64644 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -13,6 +13,7 @@ CONFIG_SATAPWR="PH12" CONFIG_GMAC_TX_DELAY=1 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 0573c1f2fa..9748805dca 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -15,6 +15,7 @@ CONFIG_USB2_VBUS_PIN="PL6" CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index f5dd96d6e8..ff6562df5c 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index b8c3c56a91..767d497b3c 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index f7a7b736b2..44a66028bd 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -9,6 +9,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 2b1b1ccfbb..0fe7c11300 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index f44fc9e935..01f259f45d 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index 0ce8c1110a..974ff1c76b 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -10,6 +10,7 @@ CONFIG_SATAPWR="PB3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index 760cb1b068..ca0bcc0cf2 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -4,6 +4,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 3277461b92..23651ec985 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -10,6 +10,7 @@ CONFIG_SATAPWR="PH2" CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index ce07a8c7ec..6cb36637a3 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_ZQ=122 CONFIG_SATAPWR="PH2" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 9685757e30..dd2b2802e4 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN4I=y CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 2da7a857a2..7f23f9e608 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig index f99aaecfb0..00dc72d81c 100644 --- a/configs/MPC8349EMDS_PCI64_defconfig +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -84,6 +84,8 @@ CONFIG_LCRR_CLKDIV_4=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index 3a1268a5ae..7550aa30c7 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -84,6 +84,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" CONFIG_BOOTDELAY=6 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index a446bb9f2c..ba00a275cd 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -85,6 +85,8 @@ CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 746e5686ab..a4d137cd23 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -10,6 +10,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index 5eaf24aa89..12f8bd91b5 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index 2666f1b601..d4cdcb7907 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index 4d900c1950..08d847989d 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -8,6 +8,7 @@ CONFIG_INITIAL_USB_SCAN_DELAY=2000 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index fe6c0fa165..d1cd98db90 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -8,6 +8,7 @@ CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index 10c151f4e0..3b3b35d6d5 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index b3b38a5288..8f03d1e96a 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index 57b25bac02..d455a56315 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index 70facee385..9865e83f06 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index 288b5e6be8..b45b6cde1c 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -12,6 +12,7 @@ CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" CONFIG_AXP_GPIO=y +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index 6000e397f2..7d440d1813 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index d0a788987c..2a75804105 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ODT_EN=y CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index 2a7bfffc95..1ff40a09ef 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -12,6 +12,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 9f41fabddb..af98dc8396 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index 0714430403..3588a2c9dd 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -11,6 +11,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 978e856d79..a7383f1eda 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index 46ef97d7eb..691fd85f47 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index 914fc9d506..6ded24e294 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -16,6 +16,7 @@ CONFIG_USB1_VBUS_PIN="PD24" CONFIG_AXP_GPIO=y CONFIG_SATAPWR="PD25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig index c884d8f955..8bc353112b 100644 --- a/configs/Sunchip_CX-A99_defconfig +++ b/configs/Sunchip_CX-A99_defconfig @@ -12,6 +12,7 @@ CONFIG_USB0_VBUS_PIN="PH15" CONFIG_USB1_VBUS_PIN="PL7" CONFIG_USB3_VBUS_PIN="PL8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 65ab07ee4d..d2e85c9408 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -119,6 +119,8 @@ CONFIG_LCRR_CLKDIV_8=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index 5be41f1880..2b10629cbf 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -20,6 +20,7 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index b721118418..6413fabf84 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 954a6b777b..437c86795b 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -12,6 +12,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index 3a2c2877a8..e21e4e0ab4 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PB3" CONFIG_USB1_VBUS_PIN="PG12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index 9a4743ff6a..0f8c8afc29 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -19,6 +19,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index cd2b6744b8..9c8107c50d 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index 65430c32fc..8a3561bed5 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index 9ccbd68241..a7fcde6940 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -33,7 +33,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -# CONFIG_BLK is not set +# CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y @@ -42,6 +42,8 @@ CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y +# CONFIG_SPL_DM_MMC is not set +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SPI_FLASH_WINBOND=y @@ -50,6 +52,7 @@ CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index aa4caf6534..972fc0ad22 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SERIES=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SHOW_BOOT_PROGRESS=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="am335x-shc" diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index 2083857b8d..9a68ae47b0 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SHC_ICT=y CONFIG_SERIES=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SHOW_BOOT_PROGRESS=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="am335x-shc" diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index fdb22afb9e..c526cd568c 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SHC_NETBOOT=y CONFIG_SERIES=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SHOW_BOOT_PROGRESS=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="am335x-shc" diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 1bbd85fd0f..b412ecaf46 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SHC_SDBOOT=y CONFIG_SERIES=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SHOW_BOOT_PROGRESS=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="am335x-shc" diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index a3de7a4ec4..96de6f48c9 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -28,7 +28,9 @@ CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_CMD_DTIMG=y CONFIG_CMD_SPL=y +CONFIG_CMD_BCB=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_PMIC is not set diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index d2548ff660..d776a0b244 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -31,6 +31,8 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_DTIMG=y +CONFIG_CMD_BCB=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_PMIC is not set diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index b52d321a69..6419c53296 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -36,6 +36,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_CMD_DTIMG=y +CONFIG_CMD_BCB=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_PMIC is not set diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 2cf3a693fc..d43df6a187 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -28,14 +28,12 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y # CONFIG_ISO_PARTITION is not set @@ -79,7 +77,6 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y -CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 48b28b390e..8ac16f0372 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -31,13 +31,11 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y # CONFIG_ISO_PARTITION is not set @@ -76,7 +74,6 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y -CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index d41eb34691..9eda731a77 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -7,6 +7,7 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig index 0f5123abb0..29e9e3b9a9 100644 --- a/configs/apf27_defconfig +++ b/configs/apf27_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySMX0,115200 mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs) ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run check_flash check_env;" CONFIG_VERSION_VARIABLE=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_TEXT_BASE=0xA0000000 diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index c1b727e0df..6f586bae68 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -9,6 +9,7 @@ CONFIG_IDENT_STRING=" for ARNDALE" CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_BEST_MATCH=y +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y # CONFIG_SPL_FRAMEWORK is not set diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig index 68b68f89d1..fed2de5c37 100644 --- a/configs/aspenite_defconfig +++ b/configs/aspenite_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nMarvell-Aspenite DB" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_FLASH is not set diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig new file mode 100644 index 0000000000..b326231b68 --- /dev/null +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_ZYNQMP_TWO_SDHCI=y +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=0 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_TEXT_BASE=0xfffc0000 +CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK_ZYNQMP=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index dc47292ce0..a384399b41 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -9,6 +9,7 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index c534a548d8..549d13ee48 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -9,6 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 27999555b6..75fd0b173a 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=576 CONFIG_MMC0_CD_PIN="PH13" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry" diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig index 87fa0a9b45..fbfa273069 100644 --- a/configs/bananapi_m2_plus_h3_defconfig +++ b/configs/bananapi_m2_plus_h3_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index bff6f37e28..3bc83134b3 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig index 8546674b23..933ec4db43 100644 --- a/configs/bananapi_m2_zero_defconfig +++ b/configs/bananapi_m2_zero_defconfig @@ -5,6 +5,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 0f5d531136..498b6601a5 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -7,6 +7,7 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 5292ef96ee..a125f78fa5 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -14,6 +14,7 @@ CONFIG_SEABIOS=y CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 6e0266be45..2c18d36afc 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -6,6 +6,8 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" CONFIG_EFI_PARTITION=y diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index f22b06e9ce..c79de19919 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -6,6 +6,8 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};" CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" CONFIG_CMD_SF=y diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index f142cde779..c89fba5b83 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig index be946956fa..7c62944e98 100644 --- a/configs/beelink_x2_defconfig +++ b/configs/beelink_x2_defconfig @@ -3,14 +3,13 @@ CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=567 -CONFIG_DRAM_ZQ=3881979 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_CONSOLE_MUX=y +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2" CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index 7f432e5720..14f8d769bb 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -18,6 +18,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index d9e337a8a9..5d47395f5e 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -10,6 +10,7 @@ CONFIG_TARGET_BK4R1=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 5487e5517c..94b9babf5e 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -19,6 +19,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=0 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run cfgscr; run brdefaultip" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 5ab3f929b2..75fc6b7dcd 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -18,6 +18,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=0 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run cfgscr; run brdefaultip" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index ce7c8522b1..9d629f69c5 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x20000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y +CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x0 @@ -21,6 +22,8 @@ CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=0 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run cfgscr; run brdefaultip" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -70,7 +73,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-spi" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas " CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SPL_DM=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index f2f10ba4bc..a4b0c45ee3 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -20,6 +20,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=0 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev 1; run b_default" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run cfgscr; run brdefaultip" CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 3cbc949a01..6ab336fe6e 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -8,6 +8,7 @@ CONFIG_TARGET_CHERRYHILL=y CONFIG_DEBUG_UART=y CONFIG_SMP=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index cf815dccbd..e9c3a8d152 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -87,6 +88,5 @@ CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index f6056f85cc..a3b0c587eb 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_LOG=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb" @@ -96,6 +97,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y # CONFIG_USE_PRIVATE_LIBGCC is not set -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 67526e87c0..4bbd7a67dc 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -15,6 +15,7 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index c3c29d38e5..340ab1509d 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -14,6 +14,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index b4bae3b197..64142e026d 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -94,6 +95,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 522e60bbb5..43264abacc 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -14,6 +14,7 @@ CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 3b2cbdcd44..973460082d 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -14,6 +14,7 @@ CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 999dc69452..4179e80a8c 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -93,7 +94,6 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y # CONFIG_USE_PRIVATE_LIBGCC is not set -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y # CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index a42d726b71..a37661bf4a 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -8,6 +8,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index b7b886be4f..280c981a36 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -18,6 +18,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index 2f919b597d..a4f6f096fb 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 002db24b04..6f4fe45760 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -18,6 +18,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start;sf probe" CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y CONFIG_SPL_TEXT_BASE=0x00908000 diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index c9d5d4d510..45653089f1 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 338317203e..3e193edef3 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -19,8 +19,10 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sda2 ro quiet" +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 4fdee998be..2e71156b84 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -15,8 +15,10 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sda2 ro quiet" +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index 326668d742..93abad2a81 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -16,6 +16,7 @@ CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 7fba44f007..6eeb7c519b 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -5,6 +5,7 @@ CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_PRE_CONSOLE_BUFFER=y diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index b05da76ef1..2fd2b8954e 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -8,6 +8,7 @@ CONFIG_TARGET_COUGARCANYON2=y CONFIG_SMP=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index e575040a47..7beb1cad81 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -9,6 +9,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_FIT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig index df77cb89ca..c5e2d890cd 100644 --- a/configs/crs305-1g-4s_defconfig +++ b/configs/crs305-1g-4s_defconfig @@ -4,10 +4,11 @@ CONFIG_SYS_TEXT_BASE=0x00800000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_CRS305_1G_4S=y CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_SF=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 845565d620..2723c56068 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 7de1d2ffc4..a161ad5e02 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -30,13 +30,15 @@ CONFIG_CRC32_VERIFY=y CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set +CONFIG_CMD_MTD=y +# CONFIG_CMD_SF is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_TIME is not set # CONFIG_CMD_EXT4 is not set CONFIG_CMD_FS_UUID=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:512k(u-boot.ais),64k(u-boot-env),7552k(kernel-spare),64k(MAC-Address)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:32k(SPL),480k(u-boot),64k(u-boot-env),7552k(kernel-spare),64k(MAC-Address)" CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -77,4 +79,3 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_DA8XX=y CONFIG_USB_STORAGE=y # CONFIG_FAT_WRITE is not set -CONFIG_USE_TINY_PRINTF=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index c1a430cf3b..a2d27efd80 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index d55dfc095f..38d519237f 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index b8f036e317..f54538ab11 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index 65995b2b5c..5654fd7b44 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig index 071a889cd3..3a311ebdf2 100644 --- a/configs/db-xc3-24g4xg_defconfig +++ b/configs/db-xc3-24g4xg_defconfig @@ -7,6 +7,7 @@ CONFIG_BUILD_TARGET="u-boot.kwb" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index 111011c854..13c58831f4 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -14,8 +14,10 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sda1 ro quiet" +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index 3600863eca..7e28dec718 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index aca8abbe9c..6dec69d73a 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nD-Link DNS-325" # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 679c18236f..70fbb3660a 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_DOCKSTAR=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="DockStar> " # CONFIG_CMD_FLASH is not set diff --git a/configs/draco_defconfig b/configs/draco_defconfig index d23ca8a4c6..d6b2b4a42b 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index e148208f99..5762c70a4a 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nMarvell-DreamPlug" # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 671572b976..a22c067a3e 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_DS109=y CONFIG_NR_DRAM_BANKS=2 # CONFIG_SYS_MALLOC_F is not set +CONFIG_USE_PREBOOT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 9abfae5b6b..3f8c1773c4 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -16,6 +16,8 @@ CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start; sf probe" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40004030 diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index 0a192a090a..c664bf5684 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/efi-x86_app_defconfig b/configs/efi-x86_app_defconfig index ea3743dd12..e732ec0733 100644 --- a/configs/efi-x86_app_defconfig +++ b/configs/efi-x86_app_defconfig @@ -6,6 +6,7 @@ CONFIG_VENDOR_EFI=y CONFIG_TARGET_EFI_APP=y CONFIG_DEBUG_UART=y CONFIG_FIT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 01fe5c8b5f..b304dd7e59 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -4,6 +4,7 @@ CONFIG_VENDOR_EFI=y CONFIG_TARGET_EFI_PAYLOAD=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_PRE_CONSOLE_BUFFER=y diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index c4071eccf8..ecd8d3ea80 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -4,6 +4,7 @@ CONFIG_VENDOR_EFI=y CONFIG_TARGET_EFI_PAYLOAD=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_PRE_CONSOLE_BUFFER=y diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig index c1307aa1c5..e85287e3ec 100644 --- a/configs/emlid_neutis_n5_devboard_defconfig +++ b/configs/emlid_neutis_n5_devboard_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index aded18fb77..cec52592ef 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 0eb7384340..45ae1e3c26 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 20329784ae..985469a128 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -14,12 +14,12 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_SOURCE="arch/arm/mach-rockchip/fit_spl_optee.its" +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x60000000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SPL_OPTEE=y @@ -68,6 +68,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_FUNCTION_MASS_STORAGE=y -CONFIG_USE_TINY_PRINTF=y CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index a6df143276..25bd4ef2f4 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -79,6 +80,5 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 CONFIG_DISPLAY_ROCKCHIP_MIPI=y -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index 16d8fb155c..ab0faccbc6 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-fennec.dtb" @@ -79,6 +80,5 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 8abe8a648a..d7dcb82344 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -89,6 +90,5 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index d8eceac37a..b82325dfe8 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index ba5a501963..f8d12e1179 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -7,6 +7,7 @@ CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y CONFIG_FIT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index b5d31db322..5984bee1ae 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nSeagate GoFlex Home" # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="GoFlexHome> " diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig index fe2e00a0b6..d0c1abf080 100644 --- a/configs/gplugd_defconfig +++ b/configs/gplugd_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x00f00000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nMarvell-gplugD" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_FLASH is not set diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index 1cbee126e7..b317d4d1d7 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 787ba6c87a..c1827a16f2 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nMarvell-GuruPlug" # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 19aa73f765..70b663a526 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -18,6 +18,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 1461cb175a..96acfff385 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -18,6 +18,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index f440363d6f..e511fd3cb3 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -18,6 +18,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index c1144c4094..70c566da6a 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -10,6 +10,7 @@ CONFIG_USB0_VBUS_PIN="PL5" CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 3b1737b385..9710c3af72 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -15,6 +15,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index abb409d23e..6afd64733d 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -100,6 +100,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 6f221a3366..544a98c504 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -101,6 +101,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH" CONFIG_BOOTDELAY=5 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index 629aea90eb..c512d36ba0 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH21" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index f7b2e4ff0d..6c047ca98b 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 38d80482e9..3b4ffe494b 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 71442226a3..5fff4ad585 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index c3fc0b290c..d36c3eec7d 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 979f724d85..4998db3669 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_IB62X0=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ib62x0 => " diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index b745dac738..1372c7606c 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo CONFIG_VIDEO_LCD_POWER="PH22" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_UNZIP=y # CONFIG_CMD_FLASH is not set diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index eb0e8a9c88..53ba459965 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_ICONNECT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" Iomega iConnect" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="iconnect => " # CONFIG_CMD_FLASH is not set diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 31ed63c000..418a4b3706 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -121,6 +121,8 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="echo;echo Type \"run nfsboot\" to mount root filesystem over NFS;echo" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index 831b5d0041..3cb6664157 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index 77da929584..9038811eac 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index a5e4c6a9db..2b43142bc6 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index d96250d23f..76baeec5f2 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index c19c10fba7..771dc1fadf 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index 66c7628a0d..4b26a926a6 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 53898a15c5..daf6662abf 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 237dc6b601..917e33d683 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -28,13 +28,11 @@ CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SF=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -73,7 +71,6 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y -CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 974e63c61d..ab4a2718de 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -8,6 +8,7 @@ CONFIG_MACPWR="PH19" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index a76ae9d326..8a6854e8d5 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index 55785a3559..f4f7b068a1 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -9,6 +9,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" libretech-ac" CONFIG_DEBUG_UART=y CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig index 7d42356993..d9c9b6de47 100644 --- a/configs/libretech_all_h3_cc_h2_plus_defconfig +++ b/configs/libretech_all_h3_cc_h2_plus_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index 7ef0000cd5..e99dc5c172 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index 1e22469022..088246d60b 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index f02776da24..010beaebdb 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -8,10 +8,12 @@ CONFIG_IDENT_STRING=" LS-CHLv2" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" CONFIG_API=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2" CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}" +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_MISC_INIT_R=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index daeecb5e51..1223d7131a 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -8,10 +8,12 @@ CONFIG_IDENT_STRING=" LS-XHL" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="LSXHL" CONFIG_API=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sda2" CONFIG_BOOTCOMMAND="run bootcmd_${bootsource}" +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_MISC_INIT_R=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index c551ea2daa..49cb37e810 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -18,6 +18,8 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttymxc0,115200" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run try_bootscript" CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_TEXT_BASE=0x70008000 diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index 0d4b6264e9..581e5bf756 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig index 0bef67e8cd..479466286f 100644 --- a/configs/meesc_dataflash_defconfig +++ b/configs/meesc_dataflash_defconfig @@ -6,9 +6,11 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x4200 CONFIG_ENV_OFFSET=0x4200 CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SECT_SIZE=0x210 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_MISC_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y @@ -24,7 +26,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=15000000 -CONFIG_ENV_SECT_SIZE=0x210 CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig index 970e8b8052..74426677d4 100644 --- a/configs/meesc_defconfig +++ b/configs/meesc_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_MISC_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index e8756267b0..94b9c78a6c 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -15,6 +15,8 @@ CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=-1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=romfs" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="echo U-BOOT for ${hostname};setenv preboot;echo" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 446c2f2c03..0b317bc563 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -19,6 +19,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index c9a35115fb..3f5d502eda 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -84,6 +85,5 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 4dce096d69..04d2426361 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PH24" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index 48659dbb09..396879015e 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 58986e3d9c..416cb9a9c2 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 243a19500c..221c2bc88b 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -4,6 +4,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN4I=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 209349bf64..900c98de35 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index 7697d7552c..875db3b40b 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index cdfa091efc..2d834e5170 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index 39a49d5bf9..6b05522870 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 42b37af0dc..d30687a56f 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_MX51EVK=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg" +CONFIG_USE_PREBOOT=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index e57d0dfc67..4ed38250f3 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=2 # CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg" CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 2c76b83d5e..b4c3b0e315 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_MX53LOCO=y CONFIG_NR_DRAM_BANKS=2 # CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" +CONFIG_USE_PREBOOT=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index cc2ed9af9c..9fc443c386 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -15,6 +15,8 @@ CONFIG_CMD_HDMIDETECT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vga; setenv stderr serial,vga; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;" CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0x00908000 diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 0d402f2196..65e9c4f117 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -8,6 +8,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index eb031e661f..95a9c965f7 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index f021d87190..7568fb1b4b 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index c676579e54..a359de8069 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -8,6 +8,7 @@ CONFIG_MACPWR="PD6" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index 984d9ddb84..cfda325442 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index bba31fc1bc..246658b699 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index af36ad43af..fba6ff516d 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 3aa9ceaa6a..5f78a8b63a 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 80b122d74f..4672e78c3f 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nNAS 220" # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nas220> " diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 9ae774a0ec..e5dd072347 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 6611046803..3d2a95a0e7 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 41eeab8ad1..5fc9e94a4d 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index fd56ae0dc2..c6460dd324 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index ffb60dabcf..6427c79215 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 015675b377..c50e79aba8 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index ee353f2f29..85a8a8d708 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index ebd9bf8dee..5a2df361fd 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index d324282ea5..fdc0f2b03f 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index b26bce4923..230b12f7e6 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index a2fb07f9b2..72e590a4fe 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -6,6 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index fe2ecf6c94..ab5bb2de6f 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -5,11 +5,14 @@ CONFIG_SYS_TEXT_BASE=0x80008000 CONFIG_TARGET_NOKIA_RX51=y CONFIG_NR_DRAM_BANKS=2 CONFIG_BOOTDELAY=30 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv mmcnum 1; setenv mmcpart 1;setenv mmcscriptfile bootmenu.scr;if run switchmmc; then setenv mmcdone true;setenv mmctype fat;if run scriptload; then true; else setenv mmctype ext2;if run scriptload; then true; else setenv mmctype ext4;if run scriptload; then true; else setenv mmcdone false;fi;fi;fi;if ${mmcdone}; then run scriptboot;fi;fi;if run slide; then true; else setenv bootmenu_delay 0;setenv bootdelay 0;fi" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Nokia RX-51 # " CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_SAVEENV is not set diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index a428d76129..d74149e3c5 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NSA310S=y CONFIG_NR_DRAM_BANKS=2 CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nsa310s => " diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index 219de7ae50..23a181335b 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -10,6 +10,7 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig new file mode 100644 index 0000000000..38d1549375 --- /dev/null +++ b/configs/odroid-n2_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_MESON_G12A=y +CONFIG_SYS_BOARD="w400" +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" odroid-n2" +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_G12A=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB=y +CONFIG_USB_HOST=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_PHY=y +CONFIG_MESON_G12A_USB_PHY=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_MESON_G12A=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 4a31a747ed..bd1b1605c0 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -12,6 +12,8 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index fb7e7146b2..8ed962c255 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -12,6 +12,8 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index b389d1d3c5..4a2bbdc339 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 26d0e65589..8b1719280b 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 9a74a8f24d..278ce2c2a3 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -12,6 +12,8 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_TEXT_BASE=0x40200000 diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index f8dd7f37df..d93ec395d0 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -12,6 +12,8 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb" CONFIG_VERSION_VARIABLE=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 23521b295f..2b9fd16182 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nOpenRD-Base" CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index ea53231555..4e9a99f7ba 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nOpenRD-Client" CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 589e248bbd..aeae24b1f5 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nOpenRD-Ultimate" CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 4f8bc289bd..14e15b03b2 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -16,6 +16,8 @@ CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttymxc0,115200" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run check_env" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index a561a117d4..664b4b3541 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -7,6 +7,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index 74c11d8355..0d6101fc68 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -7,6 +7,7 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index 8b274e651b..5638c4a3a6 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index b56588a42e..4fe81f8ab9 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index f86bb29e34..890e6abd45 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -7,6 +7,7 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 15ad3af991..84801a6586 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 7fe516ecf6..6ac46649c9 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index 8586bfc188..685b577a31 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 59294bc09b..79da5ce235 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index e63295495b..808f937b1d 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" CONFIG_SATAPWR="PG11" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 8a8266935f..d7b80040de 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index d80d83a5db..b2aa3eef3f 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=624 # CONFIG_VIDEO_DE2 is not set CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1" diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 5b800b59bb..8a9cc40095 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 69471de36b..a7c72f7c80 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=624 # CONFIG_VIDEO_DE2 is not set CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index ed417dc306..7cfb39dcdf 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index ad3a6b739f..c63b70f20c 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig index 02c6d7126b..b33b0c4028 100644 --- a/configs/ot1200_defconfig +++ b/configs/ot1200_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_OT1200=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig index dd745911ea..82ee6d0fc6 100644 --- a/configs/ot1200_spl_defconfig +++ b/configs/ot1200_spl_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index 50147457b1..d0ef1b6fa5 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -12,6 +12,7 @@ CONFIG_USB0_ID_DET="PD10" CONFIG_USB1_VBUS_PIN="PD12" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index dfddc4af5e..c6b6590d35 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" @@ -83,6 +84,5 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index 0da6b70ea8..35c05f7f28 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -10,6 +10,7 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 65ea32d1ff..a7ea1bcc89 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_PINE64_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index dd1368af39..c840ca0a18 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -6,12 +6,13 @@ CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_USB3_VBUS_PIN="PL5" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -CONFIG_USB3_VBUS_PIN="PL5" diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig index 2760f8cc39..1ed907df7a 100644 --- a/configs/pinebook_defconfig +++ b/configs/pinebook_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig index 130d8accd3..4cc4954e84 100644 --- a/configs/platinum_picon_defconfig +++ b/configs/platinum_picon_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig index 71914ad83f..1410bf8c8d 100644 --- a/configs/platinum_titanium_defconfig +++ b/configs/platinum_titanium_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 58780607eb..7207eb41bc 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_POGO_E02=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nPogo E02" CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="PogoE02> " # CONFIG_CMD_FLASH is not set diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index 0186a69424..012e1f2434 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index 265e6b85f9..3564ddc9a1 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 4c9a7f0824..11bbfe5695 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb" @@ -79,6 +80,5 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index 80cdacfd4d..0b6bf6dfd8 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 31f5888184..a34620b6f7 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 8f81b9a7bf..4933e6f861 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index 04132688ef..59683190cc 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index 7367306ecf..05a82c41f8 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index 03006e382c..94a680ce8b 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index d89cd44144..532611f4a9 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -17,6 +17,7 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 898d656ac3..ef85c52592 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -10,6 +10,7 @@ CONFIG_BUILD_ROM=y CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index b47e256a02..7237819909 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -4,6 +4,8 @@ CONFIG_TARGET_QEMU_ARM_64BIT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_BOOTEFI_SELFTEST=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 19d572afb4..7c95892d98 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -5,6 +5,8 @@ CONFIG_TARGET_QEMU_ARM_32BIT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_BOOTEFI_SELFTEST=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 500d5e95e3..b7d738526d 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index efd6e49333..fa1d0daa59 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 7639b558cf..72c6b1f756 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -11,6 +11,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -83,6 +84,5 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 5c29548059..37cd5c55c3 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_STACK_R_ADDR=0x60080000 CONFIG_DEBUG_UART_BASE=0x20064000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 1ab35f1b25..3d56b4ac7c 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -5,6 +5,8 @@ CONFIG_TARGET_RPI_0_W=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 53aa554cc7..3cb2bb6713 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -5,6 +5,8 @@ CONFIG_TARGET_RPI_2=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index c33ea58438..9d9d12074e 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index 2ae7b6dcae..7655fe7060 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -3,9 +3,11 @@ CONFIG_ARCH_BCM283X=y CONFIG_SYS_TEXT_BASE=0x00080000 CONFIG_TARGET_RPI_3=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 98573bb89a..af8718a1ee 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -6,6 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index bd15c98697..55d70eb68a 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -5,6 +5,8 @@ CONFIG_TARGET_RPI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 330f7e2371..7669053e6b 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index aa09c4571a..7355e3aa1e 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -93,6 +93,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_DM_BOOTCOUNT_RTC=y CONFIG_CLK=y +CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y CONFIG_DM_DEMO=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index a70793b7ad..898815fe53 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -66,6 +66,7 @@ CONFIG_DEBUG_DEVRES=y CONFIG_ADC=y CONFIG_ADC_SANDBOX=y CONFIG_CLK=y +CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y CONFIG_DM_DEMO=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 47c4540656..efc8586e8b 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -5,6 +5,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TEGRA20=y CONFIG_TARGET_SEABOARD=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # " # CONFIG_CMD_IMI is not set diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 74a52e6670..73f567f0c9 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index f474409516..e5c7bdd6cc 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -18,6 +18,8 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_TEXT_BASE=0x02023400 CONFIG_SYS_PROMPT="snow # " +CONFIG_USE_AUTOBOOT_MENUKEY=y +CONFIG_AUTOBOOT_MENUKEY=33 CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index dd14be4219..66f894efd2 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -4,6 +4,8 @@ CONFIG_TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1=y CONFIG_FIT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run try_bootscript" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 958f146e1c..9e86a23704 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -7,6 +7,8 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="setenv hostname vining-${unit_serial} ; setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; if gpio input 78 ; then setenv bootdelay 10 ; setenv boottype rcvr ; else setenv bootdelay 5 ; setenv boottype norm ; fi" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 1dadc122cf..58d135b907 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -7,6 +7,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index fe1aa8236b..5d13e55d6e 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -16,6 +16,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index e47218cb6a..b78f9e8807 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -11,6 +11,7 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 1bdbe9ebdd..6a561d0cd1 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -95,6 +95,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON" CONFIG_BOOTDELAY=5 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 424c915c29..eb4ad77456 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -95,6 +95,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP" CONFIG_BOOTDELAY=5 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 1149b13bef..8a48df25f6 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -95,6 +95,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU" CONFIG_BOOTDELAY=5 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index ec68d3d3e8..26793dbdd6 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -95,6 +95,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP" CONFIG_BOOTDELAY=5 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index 3543e95883..34cbb1e0c1 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -9,6 +9,7 @@ CONFIG_USB0_VBUS_PIN="axp_drivebus" CONFIG_USB0_VBUS_DET="axp_vbus_detect" CONFIG_USB1_VBUS_PIN="PH7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index 62b6838a95..f3d77f1cd1 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -11,6 +11,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index ac1bac877d..8b72983b23 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -16,6 +16,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 17c90a7d6c..88fbbf4bc0 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -7,6 +7,8 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start; if hdmidet; then run set_con_hdmi; else run set_con_serial; fi" CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_PRE_CON_BUF_ADDR=0x7c000000 CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index d56bf68468..196c4ce400 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -13,6 +13,7 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH11" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index 421a8d3d40..cfd696f8a3 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y +CONFIG_USE_PREBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 2653f71f78..770804f893 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -17,6 +17,8 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index ee9189aeae..d69c2a91db 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -16,6 +16,8 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 7da1beaa99..d53aff0ea0 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -15,6 +15,8 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 50f9df0db4..9b003870e5 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 68ce230704..4c52610271 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index b234539a53..73b442fc93 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" @@ -78,6 +79,5 @@ CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 6b126c52c0..daab4b2998 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -14,6 +14,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_BOOTDELAY=0 +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index a0b016c004..f92014224a 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -14,6 +14,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_BOOTDELAY=0 +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index c34b034072..9ba7282c6f 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -14,6 +14,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_BOOTDELAY=0 +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index d26cb3cfe0..4d3f7ba8ef 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_CLOCK=25804800 CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index e04156311f..e7ece9e4b7 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -20,6 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 2209330048..c312b1af6a 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -12,6 +12,7 @@ CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_SPI_BOOT=y +CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index c33862c26a..c16ddb97c1 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -5,6 +5,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TEGRA20=y CONFIG_TARGET_VENTANA=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (Ventana) # " # CONFIG_CMD_IMI is not set diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index eaea625007..c74c1457a7 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -84,6 +85,5 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 -CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig index ed6c1b8296..c73a97a050 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revA_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_SF=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revA" CONFIG_SPL_DM=y CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig index 0c2491aceb..0d4302ea73 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revB_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_SF=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revB" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_ZYNQMP=y diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig index cad95d338e..86819427fa 100644 --- a/configs/xpedite517x_defconfig +++ b/configs/xpedite517x_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig index 1c0bd951ee..81689a44d5 100644 --- a/configs/xpedite520x_defconfig +++ b/configs/xpedite520x_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_MISC_INIT_R is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig index e009aabb55..72a2a424e2 100644 --- a/configs/xpedite537x_defconfig +++ b/configs/xpedite537x_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_MISC_INIT_R is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig index 5d3569b34d..f86d1bdc2d 100644 --- a/configs/xpedite550x_defconfig +++ b/configs/xpedite550x_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y # CONFIG_MISC_INIT_R is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index e95b6649a3..deb979944a 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -1,6 +1,7 @@ CONFIG_XTENSA=y CONFIG_SYS_CPU="dc233c" CONFIG_XTFPGA_KC705=y +CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=10 CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig index 60f0efd46e..3bba1ec74a 100644 --- a/configs/zmx25_defconfig +++ b/configs/zmx25_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0xA0000000 CONFIG_TARGET_ZMX25=y CONFIG_NR_DRAM_BANKS=1 CONFIG_BOOTDELAY=5 +CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig index 4d914ea725..76a9a120ca 100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index fca0382a90..0910d3bf9d 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL=y CONFIG_SYS_MALLOC_LEN=0x1000 CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_USE_PREBOOT=y # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 21d7dd556e..0a6b172b7e 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL=y CONFIG_SYS_MALLOC_LEN=0x1000 CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_USE_PREBOOT=y # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 8f9ba072ba..e12306f844 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_USE_PREBOOT=y # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_ARCH_EARLY_INIT_R is not set diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig index 1e15889bda..1b4233ca9a 100644 --- a/configs/zynq_dlc20_rev1_0_defconfig +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -15,6 +15,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 1fceccdc09..3de1928e75 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -11,6 +11,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig index 60fe72f04e..3c95f0aceb 100644 --- a/configs/zynq_minized_defconfig +++ b/configs/zynq_minized_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 453cd549c1..6457876ce4 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig index 0908fc767c..ea24915203 100644 --- a/configs/zynq_z_turn_defconfig +++ b/configs/zynq_z_turn_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 2ff263034a..caf97d83f1 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -15,6 +15,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 33f26a6f2a..d4fcf9da04 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -17,6 +17,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 55ae55edc4..6458e62e1e 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -15,6 +15,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 7792ba29a0..feedb327bd 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -16,6 +16,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig index 3a3740629b..28d63c9ec5 100644 --- a/configs/zynq_zc770_xm011_x16_defconfig +++ b/configs/zynq_zc770_xm011_x16_defconfig @@ -16,6 +16,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index d777ba889e..01e3d5fb84 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index c5288e56e3..5195ec3d8c 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index e47cce5e07..1254b4efe9 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index ee15d83147..078b436add 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index 43b746f56c..3c974925c4 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/doc/README.autoboot b/doc/README.autoboot index eeb7e4c662..5e9a5e1cf7 100644 --- a/doc/README.autoboot +++ b/doc/README.autoboot @@ -132,8 +132,31 @@ What they do provides an escape sequence from the limited "password" strings. + CONFIG_AUTOBOOT_ENCRYPTION + + "bootstopkeysha256" environment variable + + - Hash value of the input which unlocks the device and + stops autoboot. + + This option allows a string to be entered into U-Boot to stop the + autoboot. The string itself is hashed and compared against the hash + in the environment variable 'bootstopkeysha256'. If it matches then + boot stops and a command-line prompt is presented. + + This provides a way to ship a secure production device which can also + be accessed at the U-Boot command line. + CONFIG_RESET_TO_RETRY (Only effective when CONFIG_BOOT_RETRY_TIME is also set) After the countdown timed out, the board will be reset to restart again. + + CONFIG_AUTOBOOT_USE_MENUKEY + CONFIG_AUTOBOOT_MENUKEY + + If this key is pressed to stop autoboot, then the commands in the + environment variable 'menucmd' will be executed before boot starts. + For example, 33 means "!" in ASCII, so pressing ! at boot would take + this action. diff --git a/doc/README.bootmenu b/doc/README.bootmenu index 34ff8d5ecc..ca5099089e 100644 --- a/doc/README.bootmenu +++ b/doc/README.bootmenu @@ -91,7 +91,7 @@ To run the bootmenu at startup add these additional definitions: #define CONFIG_AUTOBOOT_KEYED #define CONFIG_BOOTDELAY 30 - #define CONFIG_MENU_SHOW + #define CONFIG_AUTOBOOT_MENU_SHOW When you intend to use the bootmenu on color frame buffer console, make sure to additionally define CONFIG_CFB_CONSOLE_ANSI in the diff --git a/doc/README.menu b/doc/README.menu index 450c6a83a7..0f3d741605 100644 --- a/doc/README.menu +++ b/doc/README.menu @@ -14,7 +14,7 @@ Menus are composed of items. Each item has a key used to identify it in the menu, and an opaque pointer to data controlled by the consumer. If you want to show a menu, instead starting the shell, define -CONFIG_MENU_SHOW. You have to code the int menu_show(int bootdelay) +CONFIG_AUTOBOOT_MENU_SHOW. You have to code the int menu_show(int bootdelay) function, which handle your menu. This function returns the remaining bootdelay. diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 5e92446c18..a3f0171b45 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -53,6 +53,13 @@ config SPL_CLK_CCF Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] code in U-Boot's SPL. +config SPL_CLK_COMPOSITE_CCF + bool "SPL Common Clock Framework [CCF] composite clk support " + depends on SPL_CLK_CCF + help + Enable this option if you want to (re-)use the Linux kernel's Common + Clock Framework [CCF] composite code in U-Boot's SPL. + config CLK_CCF bool "Common Clock Framework [CCF] support " depends on CLK_IMX6Q || SANDBOX_CLK_CCF @@ -60,6 +67,13 @@ config CLK_CCF Enable this option if you want to (re-)use the Linux kernel's Common Clock Framework [CCF] code in U-Boot's clock driver. +config CLK_COMPOSITE_CCF + bool "Common Clock Framework [CCF] composite clk support " + depends on CLK_CCF + help + Enable this option if you want to (re-)use the Linux kernel's Common + Clock Framework [CCF] composite code in U-Boot's clock driver. + config CLK_STM32F bool "Enable clock driver support for STM32F family" depends on CLK && (STM32F7 || STM32F4) diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index b7fec605c6..68aabe1ca9 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -7,8 +7,9 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o -obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o +obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o +obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o obj-y += analogbits/ obj-y += imx/ diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c new file mode 100644 index 0000000000..a5626c33d1 --- /dev/null +++ b/drivers/clk/clk-composite.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved. + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/clk-provider.h> +#include <clk.h> + +#include "clk.h" + +#define UBOOT_DM_CLK_COMPOSITE "clk_composite" + +static u8 clk_composite_get_parent(struct clk *clk) +{ + struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? + (struct clk *)dev_get_clk_ptr(clk->dev) : clk); + struct clk *mux = composite->mux; + + return clk_mux_get_parent(mux); +} + +static int clk_composite_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? + (struct clk *)dev_get_clk_ptr(clk->dev) : clk); + const struct clk_ops *mux_ops = composite->mux_ops; + struct clk *mux = composite->mux; + + return mux_ops->set_parent(mux, parent); +} + +static unsigned long clk_composite_recalc_rate(struct clk *clk) +{ + struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? + (struct clk *)dev_get_clk_ptr(clk->dev) : clk); + const struct clk_ops *rate_ops = composite->rate_ops; + struct clk *rate = composite->rate; + + return rate_ops->get_rate(rate); +} + +static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? + (struct clk *)dev_get_clk_ptr(clk->dev) : clk); + const struct clk_ops *rate_ops = composite->rate_ops; + struct clk *clk_rate = composite->rate; + + return rate_ops->set_rate(clk_rate, rate); +} + +static int clk_composite_enable(struct clk *clk) +{ + struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? + (struct clk *)dev_get_clk_ptr(clk->dev) : clk); + const struct clk_ops *gate_ops = composite->gate_ops; + struct clk *gate = composite->gate; + + return gate_ops->enable(gate); +} + +static int clk_composite_disable(struct clk *clk) +{ + struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ? + (struct clk *)dev_get_clk_ptr(clk->dev) : clk); + const struct clk_ops *gate_ops = composite->gate_ops; + struct clk *gate = composite->gate; + + gate_ops->disable(gate); + + return 0; +} + +struct clk_ops clk_composite_ops = { + /* This will be set according to clk_register_composite */ +}; + +struct clk *clk_register_composite(struct device *dev, const char *name, + const char * const *parent_names, + int num_parents, struct clk *mux, + const struct clk_ops *mux_ops, + struct clk *rate, + const struct clk_ops *rate_ops, + struct clk *gate, + const struct clk_ops *gate_ops, + unsigned long flags) +{ + struct clk *clk; + struct clk_composite *composite; + int ret; + struct clk_ops *composite_ops = &clk_composite_ops; + + composite = kzalloc(sizeof(*composite), GFP_KERNEL); + if (!composite) + return ERR_PTR(-ENOMEM); + + if (mux && mux_ops) { + composite->mux = mux; + composite->mux_ops = mux_ops; + if (mux_ops->set_parent) + composite_ops->set_parent = clk_composite_set_parent; + mux->data = (ulong)composite; + } + + if (rate && rate_ops) { + if (!rate_ops->get_rate) { + clk = ERR_PTR(-EINVAL); + goto err; + } + composite_ops->get_rate = clk_composite_recalc_rate; + + /* .set_rate requires either .round_rate or .determine_rate */ + if (rate_ops->set_rate) + composite_ops->set_rate = clk_composite_set_rate; + + composite->rate = rate; + composite->rate_ops = rate_ops; + rate->data = (ulong)composite; + } + + if (gate && gate_ops) { + if (!gate_ops->enable || !gate_ops->disable) { + clk = ERR_PTR(-EINVAL); + goto err; + } + + composite->gate = gate; + composite->gate_ops = gate_ops; + composite_ops->enable = clk_composite_enable; + composite_ops->disable = clk_composite_disable; + gate->data = (ulong)composite; + } + + clk = &composite->clk; + ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name, + parent_names[clk_composite_get_parent(clk)]); + if (ret) { + clk = ERR_PTR(ret); + goto err; + } + + return clk; + +err: + kfree(composite); + return clk; +} + +U_BOOT_DRIVER(clk_composite) = { + .name = UBOOT_DM_CLK_COMPOSITE, + .id = UCLASS_CLK, + .ops = &clk_composite_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 6921c76a48..822e09b084 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -18,6 +18,7 @@ #include <dm/lists.h> #include <dm/device-internal.h> #include <linux/clk-provider.h> +#include <linux/log2.h> #include <div64.h> #include <clk.h> #include "clk.h" @@ -69,8 +70,8 @@ unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate, static ulong clk_divider_recalc_rate(struct clk *clk) { - struct clk_divider *divider = - to_clk_divider(dev_get_clk_ptr(clk->dev)); + struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ? + dev_get_clk_ptr(clk->dev) : clk); unsigned long parent_rate = clk_get_parent_rate(clk); unsigned int val; @@ -86,8 +87,95 @@ static ulong clk_divider_recalc_rate(struct clk *clk) divider->flags, divider->width); } +static bool _is_valid_table_div(const struct clk_div_table *table, + unsigned int div) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->div == div) + return true; + return false; +} + +static bool _is_valid_div(const struct clk_div_table *table, unsigned int div, + unsigned long flags) +{ + if (flags & CLK_DIVIDER_POWER_OF_TWO) + return is_power_of_2(div); + if (table) + return _is_valid_table_div(table, div); + return true; +} + +static unsigned int _get_table_val(const struct clk_div_table *table, + unsigned int div) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->div == div) + return clkt->val; + return 0; +} + +static unsigned int _get_val(const struct clk_div_table *table, + unsigned int div, unsigned long flags, u8 width) +{ + if (flags & CLK_DIVIDER_ONE_BASED) + return div; + if (flags & CLK_DIVIDER_POWER_OF_TWO) + return __ffs(div); + if (flags & CLK_DIVIDER_MAX_AT_ZERO) + return (div == clk_div_mask(width) + 1) ? 0 : div; + if (table) + return _get_table_val(table, div); + return div - 1; +} +int divider_get_val(unsigned long rate, unsigned long parent_rate, + const struct clk_div_table *table, u8 width, + unsigned long flags) +{ + unsigned int div, value; + + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); + + if (!_is_valid_div(table, div, flags)) + return -EINVAL; + + value = _get_val(table, div, flags, width); + + return min_t(unsigned int, value, clk_div_mask(width)); +} + +static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ? + dev_get_clk_ptr(clk->dev) : clk); + unsigned long parent_rate = clk_get_parent_rate(clk); + int value; + u32 val; + + value = divider_get_val(rate, parent_rate, divider->table, + divider->width, divider->flags); + if (value < 0) + return value; + + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + val = clk_div_mask(divider->width) << (divider->shift + 16); + } else { + val = readl(divider->reg); + val &= ~(clk_div_mask(divider->width) << divider->shift); + } + val |= (u32)value << divider->shift; + writel(val, divider->reg); + + return clk_get_rate(clk); +} + const struct clk_ops clk_divider_ops = { .get_rate = clk_divider_recalc_rate, + .set_rate = clk_divider_set_rate, }; static struct clk *_register_divider(struct device *dev, const char *name, diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c new file mode 100644 index 0000000000..70b8794554 --- /dev/null +++ b/drivers/clk/clk-gate.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> + * Copyright 2019 NXP + * + * Gated clock implementation + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/clk-provider.h> +#include <clk.h> +#include "clk.h" + +#define UBOOT_DM_CLK_GATE "clk_gate" + +/** + * DOC: basic gatable clock which can gate and ungate it's output + * + * Traits of this clock: + * prepare - clk_(un)prepare only ensures parent is (un)prepared + * enable - clk_enable and clk_disable are functional & control gating + * rate - inherits rate from parent. No clk_set_rate support + * parent - fixed parent. No clk_set_parent support + */ + +/* + * It works on following logic: + * + * For enabling clock, enable = 1 + * set2dis = 1 -> clear bit -> set = 0 + * set2dis = 0 -> set bit -> set = 1 + * + * For disabling clock, enable = 0 + * set2dis = 1 -> set bit -> set = 1 + * set2dis = 0 -> clear bit -> set = 0 + * + * So, result is always: enable xor set2dis. + */ +static void clk_gate_endisable(struct clk *clk, int enable) +{ + struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ? + dev_get_clk_ptr(clk->dev) : clk); + int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + u32 reg; + + set ^= enable; + + if (gate->flags & CLK_GATE_HIWORD_MASK) { + reg = BIT(gate->bit_idx + 16); + if (set) + reg |= BIT(gate->bit_idx); + } else { +#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) + reg = gate->io_gate_val; +#else + reg = readl(gate->reg); +#endif + + if (set) + reg |= BIT(gate->bit_idx); + else + reg &= ~BIT(gate->bit_idx); + } + + writel(reg, gate->reg); +} + +static int clk_gate_enable(struct clk *clk) +{ + clk_gate_endisable(clk, 1); + + return 0; +} + +static int clk_gate_disable(struct clk *clk) +{ + clk_gate_endisable(clk, 0); + + return 0; +} + +int clk_gate_is_enabled(struct clk *clk) +{ + struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ? + dev_get_clk_ptr(clk->dev) : clk); + u32 reg; + +#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) + reg = gate->io_gate_val; +#else + reg = readl(gate->reg); +#endif + + /* if a set bit disables this clk, flip it before masking */ + if (gate->flags & CLK_GATE_SET_TO_DISABLE) + reg ^= BIT(gate->bit_idx); + + reg &= BIT(gate->bit_idx); + + return reg ? 1 : 0; +} + +const struct clk_ops clk_gate_ops = { + .enable = clk_gate_enable, + .disable = clk_gate_disable, + .get_rate = clk_generic_get_rate, +}; + +struct clk *clk_register_gate(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_gate *gate; + struct clk *clk; + int ret; + + if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { + if (bit_idx > 15) { + pr_err("gate bit exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + + /* allocate the gate */ + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + /* struct clk_gate assignments */ + gate->reg = reg; + gate->bit_idx = bit_idx; + gate->flags = clk_gate_flags; +#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) + gate->io_gate_val = *(u32 *)reg; +#endif + + clk = &gate->clk; + + ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name); + if (ret) { + kfree(gate); + return ERR_PTR(ret); + } + + return clk; +} + +U_BOOT_DRIVER(clk_gate) = { + .name = UBOOT_DM_CLK_GATE, + .id = UCLASS_CLK, + .ops = &clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 3c075aa09e..5acc0b8cbd 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -35,7 +35,8 @@ int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags, unsigned int val) { - struct clk_mux *mux = to_clk_mux(clk); + struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ? + dev_get_clk_ptr(clk->dev) : clk); int num_parents = mux->num_parents; if (table) { @@ -59,9 +60,27 @@ int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags, return val; } -static u8 clk_mux_get_parent(struct clk *clk) +unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index) { - struct clk_mux *mux = to_clk_mux(clk); + unsigned int val = index; + + if (table) { + val = table[index]; + } else { + if (flags & CLK_MUX_INDEX_BIT) + val = 1 << index; + + if (flags & CLK_MUX_INDEX_ONE) + val++; + } + + return val; +} + +u8 clk_mux_get_parent(struct clk *clk) +{ + struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ? + dev_get_clk_ptr(clk->dev) : clk); u32 val; #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) @@ -75,8 +94,57 @@ static u8 clk_mux_get_parent(struct clk *clk) return clk_mux_val_to_index(clk, mux->table, mux->flags, val); } +static int clk_fetch_parent_index(struct clk *clk, + struct clk *parent) +{ + struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ? + dev_get_clk_ptr(clk->dev) : clk); + + int i; + + if (!parent) + return -EINVAL; + + for (i = 0; i < mux->num_parents; i++) { + if (!strcmp(parent->dev->name, mux->parent_names[i])) + return i; + } + + return -EINVAL; +} + +static int clk_mux_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ? + dev_get_clk_ptr(clk->dev) : clk); + int index; + u32 val; + u32 reg; + + index = clk_fetch_parent_index(clk, parent); + if (index < 0) { + printf("Could not fetch index\n"); + return index; + } + + val = clk_mux_index_to_val(mux->table, mux->flags, index); + + if (mux->flags & CLK_MUX_HIWORD_MASK) { + reg = mux->mask << (mux->shift + 16); + } else { + reg = readl(mux->reg); + reg &= ~(mux->mask << mux->shift); + } + val = val << mux->shift; + reg |= val; + writel(reg, mux->reg); + + return 0; +} + const struct clk_ops clk_mux_ops = { - .get_rate = clk_generic_get_rate, + .get_rate = clk_generic_get_rate, + .set_parent = clk_mux_set_parent, }; struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 85dfe712f5..cee4d912b0 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -285,6 +285,9 @@ int clk_set_defaults(struct udevice *dev) { int ret; + if (!dev_of_valid(dev)) + return 0; + /* If this not in SPL and pre-reloc state, don't take any action. */ if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC))) return 0; diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 7d748c9fc7..39b3087067 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -55,3 +55,11 @@ const char *clk_hw_get_name(const struct clk *hw) { return hw->dev->name; } + +bool clk_dev_binded(struct clk *clk) +{ + if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND)) + return true; + + return false; +} diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 1fdf8c4e54..08cce0d79b 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -6,13 +6,7 @@ #include <common.h> #include <clk-uclass.h> #include <dm.h> - -struct clk_fixed_rate { - struct clk clk; - unsigned long fixed_rate; -}; - -#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev)) +#include <linux/clk-provider.h> static ulong clk_fixed_rate_get_rate(struct clk *clk) { diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index edeb0f2cf3..e126f18d8e 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -130,6 +130,80 @@ U_BOOT_DRIVER(sandbox_clk_gate2) = { .ops = &clk_gate2_ops, }; +static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk) +{ + struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); + struct clk_composite *composite = (struct clk_composite *)clk->data; + ulong parent_rate = clk_get_parent_rate(&composite->clk); + unsigned int val; + + val = divider->io_divider_val; + val >>= divider->shift; + val &= clk_div_mask(divider->width); + + return divider_recalc_rate(clk, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static const struct clk_ops sandbox_clk_composite_divider_ops = { + .get_rate = sandbox_clk_composite_divider_recalc_rate, +}; + +struct clk *sandbox_clk_composite(const char *name, + const char * const *parent_names, + int num_parents, void __iomem *reg, + unsigned long flags) +{ + struct clk *clk = ERR_PTR(-ENOMEM); + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux->reg = reg; + mux->shift = 24; + mux->mask = 0x7; + mux->num_parents = num_parents; + mux->flags = flags; + mux->parent_names = parent_names; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div->reg = reg; + div->shift = 16; + div->width = 3; + div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto fail; + + gate->reg = reg; + gate->bit_idx = 28; + gate->flags = flags; + + clk = clk_register_composite(NULL, name, + parent_names, num_parents, + &mux->clk, &clk_mux_ops, &div->clk, + &sandbox_clk_composite_divider_ops, + &gate->clk, &clk_gate_ops, flags); + if (IS_ERR(clk)) + goto fail; + + return clk; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(clk); +} + /* --- Sandbox Gate --- */ /* The CCF core driver itself */ static const struct udevice_id sandbox_clk_ccf_test_ids[] = { @@ -138,6 +212,7 @@ static const struct udevice_id sandbox_clk_ccf_test_ids[] = { }; static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", }; +static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", }; static int sandbox_clk_ccf_probe(struct udevice *dev) { @@ -174,6 +249,11 @@ static int sandbox_clk_ccf_probe(struct udevice *dev) sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); + reg = BIT(28) | BIT(24) | BIT(16); + clk_dm(SANDBOX_CLK_I2C, + sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels), + ®, 0)); + return 0; } diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 571be32088..1b9db6e791 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -60,7 +60,18 @@ static int clk_gate2_disable(struct clk *clk) return 0; } +static ulong clk_gate2_set_rate(struct clk *clk, ulong rate) +{ + struct clk *parent = clk_get_parent(clk); + + if (parent) + return clk_set_rate(parent, rate); + + return -ENODEV; +} + static const struct clk_ops clk_gate2_ops = { + .set_rate = clk_gate2_set_rate, .enable = clk_gate2_enable, .disable = clk_gate2_disable, .get_rate = clk_generic_get_rate, diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index e6d51830e8..1d480d8722 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -36,6 +36,23 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent, shift, 0x3, 0); } +static inline struct clk *imx_clk_gate4(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_register_gate2(NULL, name, parent, + CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, 0x3, 0); +} + +static inline struct clk *imx_clk_gate4_flags(const char *name, + const char *parent, void __iomem *reg, u8 shift, + unsigned long flags) +{ + return clk_register_gate2(NULL, name, parent, + flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, 0x3, 0); +} + static inline struct clk *imx_clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) { @@ -50,6 +67,14 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent, reg, shift, width, 0); } +static inline struct clk *imx_clk_divider2(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width) +{ + return clk_register_divider(NULL, name, parent, + CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0); +} + struct clk *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx); @@ -57,6 +82,16 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, void (*fixup)(u32 *val)); +static inline struct clk *imx_clk_mux_flags(const char *name, + void __iomem *reg, u8 shift, u8 width, + const char * const *parents, int num_parents, + unsigned long flags) +{ + return clk_register_mux(NULL, name, parents, num_parents, + flags | CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0); +} + static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) @@ -66,4 +101,50 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, width, 0); } +static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, + u8 shift, u8 width, const char * const *parents, + int num_parents) +{ + return clk_register_mux(NULL, name, parents, num_parents, + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0); +} + +static inline struct clk *imx_clk_gate(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + shift, 0, NULL); +} + +static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent, + void __iomem *reg, u8 shift, unsigned long flags) +{ + return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, + shift, 0, NULL); +} + +static inline struct clk *imx_clk_gate3(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_register_gate(NULL, name, parent, + CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, 0, NULL); +} + +struct clk *imx8m_clk_composite_flags(const char *name, + const char * const *parent_names, + int num_parents, void __iomem *reg, unsigned long flags); + +#define __imx8m_clk_composite(name, parent_names, reg, flags) \ + imx8m_clk_composite_flags(name, parent_names, \ + ARRAY_SIZE(parent_names), reg, \ + flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + +#define imx8m_clk_composite(name, parent_names, reg) \ + __imx8m_clk_composite(name, parent_names, reg, 0) + +#define imx8m_clk_composite_critical(name, parent_names, reg) \ + __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) + #endif /* __MACH_IMX_CLK_H */ diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 2cb53fb92d..abb5337e78 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -823,10 +823,7 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id, case CLKID_MPLL1: case CLKID_MPLL2: case CLKID_CLK81: - if (current_rate != rate) - return -EINVAL; - - return 0; + return -EINVAL; case CLKID_VPU: return meson_clk_set_rate_by_id(clk, meson_mux_get_parent(clk, CLKID_VPU), rate, diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 8f59193e3c..105a299812 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -58,9 +58,17 @@ config FPGA_ZYNQMPPL config FPGA_SPARTAN3 bool "Enable Spartan3 FPGA driver" + depends on FPGA_XILINX help Enable Spartan3 FPGA driver for loading in BIT format. +config FPGA_VIRTEX2 + bool "Enable Xilinx Virtex-II and later FPGA driver" + depends on FPGA_XILINX + help + Enable Virtex-II FPGA driver for loading in BIT format. This driver + also supports many newer Xilinx FPGA families. + config FPGA_ZYNQPL bool "Enable Xilinx FPGA for Zynq" depends on ARCH_ZYNQ diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 6755956e85..c929cd2cc5 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -11,9 +11,9 @@ /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) +#define PRINTF(fmt, args...) printf(fmt, ##args) #else -#define PRINTF(fmt,args...) +#define PRINTF(fmt, args...) #endif /* Note: The assumption is that we cannot possibly run fast enough to @@ -26,7 +26,7 @@ #endif #ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ +#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */ #endif static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); @@ -41,8 +41,8 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case passive_serial: - PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); - ret_val = CYC2_ps_load (desc, buf, bsize); + PRINTF("%s: Launching Passive Serial Loader\n", __func__); + ret_val = CYC2_ps_load(desc, buf, bsize); break; case fast_passive_parallel: @@ -50,16 +50,16 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) * done in the write() callback. Use the existing PS load * function for FPP, too. */ - PRINTF ("%s: Launching Fast Passive Parallel Loader\n", - __FUNCTION__); + PRINTF("%s: Launching Fast Passive Parallel Loader\n", + __func__); ret_val = CYC2_ps_load(desc, buf, bsize); break; /* Add new interface types here */ default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; @@ -71,59 +71,58 @@ int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case passive_serial: - PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); - ret_val = CYC2_ps_dump (desc, buf, bsize); + PRINTF("%s: Launching Passive Serial Dump\n", __func__); + ret_val = CYC2_ps_dump(desc, buf, bsize); break; /* Add new interface types here */ default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; } -int CYC2_info( Altera_desc *desc ) +int CYC2_info(Altera_desc *desc) { return FPGA_SUCCESS; } /* ------------------------------------------------------------------------- */ -/* CYCLON2 Passive Serial Generic Implementation */ +/* CYCLON2 Passive Serial Generic Implementation */ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; int ret = 0; - PRINTF ("%s: start with interface functions @ 0x%p\n", - __FUNCTION__, fn); + PRINTF("%s: start with interface functions @ 0x%p\n", + __func__, fn); if (fn) { int cookie = desc->cookie; /* make a local copy */ unsigned long ts; /* timestamp */ - PRINTF ("%s: Function Table:\n" + PRINTF("%s: Function Table:\n" "ptr:\t0x%p\n" "struct: 0x%p\n" "config:\t0x%p\n" "status:\t0x%p\n" "write:\t0x%p\n" "done:\t0x%p\n\n", - __FUNCTION__, &fn, fn, fn->config, fn->status, + __func__, &fn, fn, fn->config, fn->status, fn->write, fn->done); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Loading FPGA Device %d...", cookie); + printf("Loading FPGA Device %d...", cookie); #endif /* * Run the pre configuration function if there is one. */ - if (*fn->pre) { + if (*fn->pre) (*fn->pre) (cookie); - } /* Establish the initial state */ (*fn->config) (false, true, cookie); /* De-assert nCONFIG */ @@ -133,22 +132,23 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) udelay(2); /* T_cfg > 2us */ /* Wait for nSTATUS to be asserted */ - ts = get_timer (0); /* get current time */ + ts = get_timer(0); /* get current time */ do { - CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ - puts ("** Timeout waiting for STATUS to go high.\n"); + CONFIG_FPGA_DELAY(); + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + /* check the time */ + puts("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); return FPGA_FAIL; } } while (!(*fn->status) (cookie)); /* Get ready for the burn */ - CONFIG_FPGA_DELAY (); + CONFIG_FPGA_DELAY(); ret = (*fn->write) (buf, bsize, true, cookie); if (ret) { - puts ("** Write failed.\n"); + puts("** Write failed.\n"); (*fn->abort) (cookie); return FPGA_FAIL; } @@ -156,39 +156,41 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) puts(" OK? ..."); #endif - CONFIG_FPGA_DELAY (); + CONFIG_FPGA_DELAY(); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc (' '); /* terminate the dotted line */ + putc(' '); /* terminate the dotted line */ #endif - /* - * Checking FPGA's CONF_DONE signal - correctly booted ? - */ + /* + * Checking FPGA's CONF_DONE signal - correctly booted ? + */ - if ( ! (*fn->done) (cookie) ) { - puts ("** Booting failed! CONF_DONE is still deasserted.\n"); - (*fn->abort) (cookie); - return (FPGA_FAIL); - } + if (!(*fn->done) (cookie)) { + puts("** Booting failed! CONF_DONE is still deasserted.\n"); + (*fn->abort) (cookie); + return FPGA_FAIL; + } #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - puts(" OK\n"); + puts(" OK\n"); #endif - ret_val = FPGA_SUCCESS; + ret_val = FPGA_SUCCESS; #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (ret_val == FPGA_SUCCESS) { - puts ("Done.\n"); - } - else { - puts ("Fail.\n"); - } + if (ret_val == FPGA_SUCCESS) + puts("Done.\n"); + else + puts("Fail.\n"); #endif - (*fn->post) (cookie); + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) + (*fn->post) (cookie); } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -198,7 +200,6 @@ static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ - printf ("%s: Passive Serial Dumping is unavailable\n", - __FUNCTION__); + printf("%s: Passive Serial Dumping is unavailable\n", __func__); return FPGA_FAIL; } diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 02773d6a0e..395736875f 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -3,6 +3,8 @@ * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * Keith Outwater, keith_outwater@mvis.com + * + * Copyright (c) 2019 SED Systems, a division of Calian Ltd. */ /* @@ -19,16 +21,16 @@ #endif #ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) +#define PRINTF(fmt, args...) printf(fmt, ##args) #else -#define PRINTF(fmt,args...) +#define PRINTF(fmt, args...) #endif /* * If the SelectMap interface can be overrun by the processor, define - * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration - * file and add board-specific support for checking BUSY status. By default, - * assume that the SelectMap interface cannot be overrun. + * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board + * configuration file and add board-specific support for checking BUSY status. + * By default, assume that the SelectMap interface cannot be overrun. */ #ifndef CONFIG_SYS_FPGA_CHECK_BUSY #undef CONFIG_SYS_FPGA_CHECK_BUSY @@ -65,7 +67,7 @@ * an XC2V1000, if anyone can ever get ahold of one. */ #ifndef CONFIG_SYS_FPGA_WAIT_INIT -#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */ +#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ #endif /* @@ -74,14 +76,14 @@ * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. */ #ifndef CONFIG_SYS_FPGA_WAIT_BUSY -#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/ +#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ #endif /* Default timeout for waiting for FPGA to enter operational mode after * configuration data has been written. */ #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG -#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ +#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ #endif static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -97,18 +99,18 @@ static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize, switch (desc->iface) { case slave_serial: - PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); + PRINTF("%s: Launching Slave Serial Load\n", __func__); ret_val = virtex2_ss_load(desc, buf, bsize); break; case slave_selectmap: - PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); + PRINTF("%s: Launching Slave Parallel Load\n", __func__); ret_val = virtex2_ssm_load(desc, buf, bsize); break; default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; } @@ -119,18 +121,18 @@ static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case slave_serial: - PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); + PRINTF("%s: Launching Slave Serial Dump\n", __func__); ret_val = virtex2_ss_dump(desc, buf, bsize); break; case slave_parallel: - PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); + PRINTF("%s: Launching Slave Parallel Dump\n", __func__); ret_val = virtex2_ssm_dump(desc, buf, bsize); break; default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; } @@ -141,8 +143,8 @@ static int virtex2_info(xilinx_desc *desc) } /* - * Virtex-II Slave SelectMap configuration loader. Configuration via - * SelectMap is as follows: + * Virtex-II Slave SelectMap or Serial configuration loader. Configuration + * is as follows: * 1. Set the FPGA's PROG_B line low. * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high. * 3. Write data to the SelectMap port. If INIT_B goes low at any time @@ -154,200 +156,236 @@ static int virtex2_info(xilinx_desc *desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) { - int ret_val = FPGA_FAIL; - xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; + unsigned long ts; - PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", - __FUNCTION__, __LINE__, fn); + PRINTF("%s:%d: Start with interface functions @ 0x%p\n", + __func__, __LINE__, fn); - if (fn) { - size_t bytecount = 0; - unsigned char *data = (unsigned char *) buf; - int cookie = desc->cookie; - unsigned long ts; - - /* Gotta split this one up (so the stack won't blow??) */ - PRINTF ("%s:%d: Function Table:\n" - " base 0x%p\n" - " struct 0x%p\n" - " pre 0x%p\n" - " prog 0x%p\n" - " init 0x%p\n" - " error 0x%p\n", - __FUNCTION__, __LINE__, - &fn, fn, fn->pre, fn->pgm, fn->init, fn->err); - PRINTF (" clock 0x%p\n" - " cs 0x%p\n" - " write 0x%p\n" - " rdata 0x%p\n" - " wdata 0x%p\n" - " busy 0x%p\n" - " abort 0x%p\n" - " post 0x%p\n\n", - fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, - fn->busy, fn->abort, fn->post); + if (!fn) { + printf("%s:%d: NULL Interface function table!\n", + __func__, __LINE__); + return FPGA_FAIL; + } + + /* Gotta split this one up (so the stack won't blow??) */ + PRINTF("%s:%d: Function Table:\n" + " base 0x%p\n" + " struct 0x%p\n" + " pre 0x%p\n" + " prog 0x%p\n" + " init 0x%p\n" + " error 0x%p\n", + __func__, __LINE__, + &fn, fn, fn->pre, fn->pgm, fn->init, fn->err); + PRINTF(" clock 0x%p\n" + " cs 0x%p\n" + " write 0x%p\n" + " rdata 0x%p\n" + " wdata 0x%p\n" + " busy 0x%p\n" + " abort 0x%p\n" + " post 0x%p\n\n", + fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, + fn->busy, fn->abort, fn->post); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Initializing FPGA Device %d...\n", cookie); + printf("Initializing FPGA Device %d...\n", cookie); #endif - /* - * Run the pre configuration function if there is one. - */ - if (*fn->pre) { - (*fn->pre) (cookie); + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) + (*fn->pre)(cookie); + + /* + * Assert the program line. The minimum pulse width for + * Virtex II devices is 300 nS (Tprogram parameter in datasheet). + * There is no maximum value for the pulse width. Check to make + * sure that INIT_B goes low after assertion of PROG_B + */ + (*fn->pgm)(true, true, cookie); + udelay(10); + ts = get_timer(0); + do { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n", + __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + (*fn->abort)(cookie); + return FPGA_FAIL; + } + } while (!(*fn->init)(cookie)); + + (*fn->pgm)(false, true, cookie); + CONFIG_FPGA_DELAY(); + if (fn->clk) + (*fn->clk)(true, true, cookie); + + /* + * Start a timer and wait for INIT_B to go high + */ + ts = get_timer(0); + do { + CONFIG_FPGA_DELAY(); + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", + __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + (*fn->abort)(cookie); + return FPGA_FAIL; } + } while ((*fn->init)(cookie) && (*fn->busy)(cookie)); - /* - * Assert the program line. The minimum pulse width for - * Virtex II devices is 300 nS (Tprogram parameter in datasheet). - * There is no maximum value for the pulse width. Check to make - * sure that INIT_B goes low after assertion of PROG_B - */ - (*fn->pgm) (true, true, cookie); - udelay (10); - ts = get_timer (0); - do { - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { - printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" - " to assert.\n", __FUNCTION__, __LINE__, - CONFIG_SYS_FPGA_WAIT_INIT); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - } while (!(*fn->init) (cookie)); + if (fn->wr) + (*fn->wr)(true, true, cookie); + if (fn->cs) + (*fn->cs)(true, true, cookie); - (*fn->pgm) (false, true, cookie); - CONFIG_FPGA_DELAY (); - (*fn->clk) (true, true, cookie); + mdelay(10); + return FPGA_SUCCESS; +} - /* - * Start a timer and wait for INIT_B to go high - */ - ts = get_timer (0); - do { - CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { - printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" - " to deassert.\n", __FUNCTION__, __LINE__, - CONFIG_SYS_FPGA_WAIT_INIT); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); +static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, + int cookie) +{ + int ret_val = FPGA_SUCCESS; + int num_done = 0; + unsigned long ts; + + /* + * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. + */ + CONFIG_FPGA_DELAY(); + if (fn->cs) + (*fn->cs)(false, true, cookie); + if (fn->wr) + (*fn->wr)(false, true, cookie); - (*fn->wr) (true, true, cookie); - (*fn->cs) (true, true, cookie); +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc('\n'); +#endif - udelay (10000); + /* + * Check for successful configuration. FPGA INIT_B and DONE + * should both be high upon successful configuration. Continue pulsing + * clock with data set to all ones until DONE is asserted and for 8 + * clock cycles afterwards. + */ + ts = get_timer(0); + while (true) { + if ((*fn->done)(cookie) == FPGA_SUCCESS && + !((*fn->init)(cookie))) { + if (num_done++ >= 8) + break; + } + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { + printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n", + __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); + (*fn->abort)(cookie); + ret_val = FPGA_FAIL; + break; + } + if (fn->wbulkdata) { + unsigned char dummy = 0xff; + (*fn->wbulkdata)(&dummy, 1, true, cookie); + } else { + (*fn->wdata)(0xff, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(true, true, cookie); + } + } + + if (ret_val == FPGA_SUCCESS) { +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + printf("Initialization of FPGA device %d complete\n", cookie); +#endif /* - * Load the data byte by byte + * Run the post configuration function if there is one. */ - while (bytecount < bsize) { -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc ()) { - (*fn->abort) (cookie); - return FPGA_FAIL; - } + if (*fn->post) + (*fn->post)(cookie); + } else { +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + printf("** Initialization of FPGA device %d FAILED\n", + cookie); #endif + } + return ret_val; +} - if ((*fn->done) (cookie) == FPGA_SUCCESS) { - PRINTF ("%s:%d:done went active early, bytecount = %d\n", - __FUNCTION__, __LINE__, bytecount); - break; - } - -#ifdef CONFIG_SYS_FPGA_CHECK_ERROR - if ((*fn->init) (cookie)) { - printf ("\n%s:%d: ** Error: INIT asserted during" - " configuration\n", __FUNCTION__, __LINE__); - printf ("%d = buffer offset, %d = buffer size\n", - bytecount, bsize); - (*fn->abort) (cookie); - return FPGA_FAIL; - } +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + xilinx_virtex2_slave_fns *fn = desc->iface_fns; + size_t bytecount = 0; + unsigned char *data = (unsigned char *)buf; + int cookie = desc->cookie; + + ret_val = virtex2_slave_pre(fn, cookie); + if (ret_val != FPGA_SUCCESS) + return ret_val; + + /* + * Load the data byte by byte + */ + while (bytecount < bsize) { +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) { + (*fn->abort)(cookie); + return FPGA_FAIL; + } #endif - (*fn->wdata) (data[bytecount++], true, cookie); - CONFIG_FPGA_DELAY (); - - /* - * Cycle the clock pin - */ - (*fn->clk) (false, true, cookie); - CONFIG_FPGA_DELAY (); - (*fn->clk) (true, true, cookie); + if ((*fn->done)(cookie) == FPGA_SUCCESS) { + PRINTF("%s:%d:done went active early, bytecount = %d\n", + __func__, __LINE__, bytecount); + break; + } -#ifdef CONFIG_SYS_FPGA_CHECK_BUSY - ts = get_timer (0); - while ((*fn->busy) (cookie)) { - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { - printf ("%s:%d: ** Timeout after %d ticks waiting for" - " BUSY to deassert\n", - __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - } +#ifdef CONFIG_SYS_FPGA_CHECK_ERROR + if ((*fn->init)(cookie)) { + printf("\n%s:%d: ** Error: INIT asserted during configuration\n", + __func__, __LINE__); + printf("%zu = buffer offset, %zu = buffer size\n", + bytecount, bsize); + (*fn->abort)(cookie); + return FPGA_FAIL; + } #endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (bytecount % (bsize / 40) == 0) - putc ('.'); -#endif - } + (*fn->wdata)(data[bytecount++], true, cookie); + CONFIG_FPGA_DELAY(); /* - * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. + * Cycle the clock pin */ - CONFIG_FPGA_DELAY (); - (*fn->cs) (false, true, cookie); - (*fn->wr) (false, true, cookie); - -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc ('\n'); -#endif + (*fn->clk)(false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(true, true, cookie); - /* - * Check for successful configuration. FPGA INIT_B and DONE should - * both be high upon successful configuration. - */ - ts = get_timer (0); - ret_val = FPGA_SUCCESS; - while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) { - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { - printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to" - "assert and INIT to deassert\n", - __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); - (*fn->abort) (cookie); - ret_val = FPGA_FAIL; - break; +#ifdef CONFIG_SYS_FPGA_CHECK_BUSY + ts = get_timer(0); + while ((*fn->busy)(cookie)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { + printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n", + __func__, __LINE__, + CONFIG_SYS_FPGA_WAIT_BUSY); + (*fn->abort)(cookie); + return FPGA_FAIL; } } - - if (ret_val == FPGA_SUCCESS) { -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Initialization of FPGA device %d complete\n", cookie); #endif - /* - * Run the post configuration function if there is one. - */ - if (*fn->post) { - (*fn->post) (cookie); - } - } else { + #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("** Initialization of FPGA device %d FAILED\n", - cookie); + if (bytecount % (bsize / 40) == 0) + putc('.'); #endif - } - } else { - printf ("%s:%d: NULL Interface function table!\n", - __FUNCTION__, __LINE__); } - return ret_val; + + return virtex2_slave_post(fn, cookie); } /* @@ -356,64 +394,127 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_fns *fn = desc->iface_fns; if (fn) { - unsigned char *data = (unsigned char *) buf; + unsigned char *data = (unsigned char *)buf; size_t bytecount = 0; int cookie = desc->cookie; - printf ("Starting Dump of FPGA Device %d...\n", cookie); + printf("Starting Dump of FPGA Device %d...\n", cookie); - (*fn->cs) (true, true, cookie); - (*fn->clk) (true, true, cookie); + (*fn->cs)(true, true, cookie); + (*fn->clk)(true, true, cookie); while (bytecount < bsize) { #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc ()) { - (*fn->abort) (cookie); + if (ctrlc()) { + (*fn->abort)(cookie); return FPGA_FAIL; } #endif /* * Cycle the clock and read the data */ - (*fn->clk) (false, true, cookie); - (*fn->clk) (true, true, cookie); - (*fn->rdata) (&(data[bytecount++]), cookie); + (*fn->clk)(false, true, cookie); + (*fn->clk)(true, true, cookie); + (*fn->rdata)(&data[bytecount++], cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % (bsize / 40) == 0) - putc ('.'); + putc('.'); #endif } /* * Deassert CS_B and cycle the clock to deselect the device. */ - (*fn->cs) (false, false, cookie); - (*fn->clk) (false, true, cookie); - (*fn->clk) (true, true, cookie); + (*fn->cs)(false, false, cookie); + (*fn->clk)(false, true, cookie); + (*fn->clk)(true, true, cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc ('\n'); + putc('\n'); #endif - puts ("Done.\n"); + puts("Done.\n"); } else { - printf ("%s:%d: NULL Interface function table!\n", - __FUNCTION__, __LINE__); + printf("%s:%d: NULL Interface function table!\n", + __func__, __LINE__); } return ret_val; } static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { - printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); - return FPGA_FAIL; + int ret_val = FPGA_FAIL; + xilinx_virtex2_slave_fns *fn = desc->iface_fns; + unsigned char *data = (unsigned char *)buf; + int cookie = desc->cookie; + + ret_val = virtex2_slave_pre(fn, cookie); + if (ret_val != FPGA_SUCCESS) + return ret_val; + + if (fn->wbulkdata) { + /* Load the data in a single chunk */ + (*fn->wbulkdata)(data, bsize, true, cookie); + } else { + size_t bytecount = 0; + + /* + * Load the data bit by bit + */ + while (bytecount < bsize) { + unsigned char curr_data = data[bytecount++]; + int bit; + +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) { + (*fn->abort) (cookie); + return FPGA_FAIL; + } +#endif + + if ((*fn->done)(cookie) == FPGA_SUCCESS) { + PRINTF("%s:%d:done went active early, bytecount = %d\n", + __func__, __LINE__, bytecount); + break; + } + +#ifdef CONFIG_SYS_FPGA_CHECK_ERROR + if ((*fn->init)(cookie)) { + printf("\n%s:%d: ** Error: INIT asserted during configuration\n", + __func__, __LINE__); + printf("%zu = buffer offset, %zu = buffer size\n", + bytecount, bsize); + (*fn->abort)(cookie); + return FPGA_FAIL; + } +#endif + + for (bit = 7; bit >= 0; --bit) { + unsigned char curr_bit = (curr_data >> bit) & 1; + (*fn->wdata)(curr_bit, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(true, true, cookie); + } + + /* Slave serial never uses a busy pin */ + +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc('.'); +#endif + } + } + + return virtex2_slave_post(fn, cookie); } static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { - printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); + printf("%s: Slave Serial Dumping is unsupported\n", __func__); return FPGA_FAIL; } diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c9aa13b409..eecc7d687e 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2819,12 +2819,12 @@ int mmc_start_init(struct mmc *mmc) MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT; #if !defined(CONFIG_MMC_BROKEN_CD) - /* we pretend there's no card when init is NULL */ no_card = mmc_getcd(mmc) == 0; #else no_card = 0; #endif #if !CONFIG_IS_ENABLED(DM_MMC) + /* we pretend there's no card when init is NULL */ no_card = no_card || (mmc->cfg->ops->init == NULL); #endif if (no_card) { diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index e0ac3e9d69..49085090c8 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -13,6 +13,7 @@ #include <errno.h> #include <malloc.h> #include <stdbool.h> +#include <watchdog.h> #include <asm/gpio.h> #include <dm/pinctrl.h> #include <linux/bitops.h> @@ -623,6 +624,8 @@ static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) u32 size; int ret; + WATCHDOG_RESET(); + if (data->flags == MMC_DATA_WRITE) host->last_data_write = 1; diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index bf26d2e4e2..f5f3e43247 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -114,6 +114,9 @@ static int mv_sdhci_probe(struct udevice *dev) host->name = MVSDH_NAME; host->ioaddr = (void *)devfdt_get_addr(dev); host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD; + host->mmc = &plat->mmc; + host->mmc->dev = dev; + host->mmc->priv = host; ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret) @@ -124,9 +127,6 @@ static int mv_sdhci_probe(struct udevice *dev) sdhci_mvebu_mbus_config(host->ioaddr); } - host->mmc = &plat->mmc; - host->mmc->dev = dev; - host->mmc->priv = host; upriv->mmc = host->mmc; return sdhci_probe(dev); diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 0a0770cc20..2779bca93f 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -623,7 +623,7 @@ static int sdhci_init(struct mmc *mmc) #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO) struct udevice *dev = mmc->dev; - gpio_request_by_name(dev, "cd-gpio", 0, + gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN); #endif diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 33c2f16be8..724bbee752 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -739,8 +739,8 @@ static void davinci_nand_init(struct nand_chip *nand) layout = &nand_keystone_rbl_4bit_layout_oobfirst; layout->oobavail = 0; - for (i = 0; layout->oobfree[i].length && - i < ARRAY_SIZE(layout->oobfree); i++) + for (i = 0; i < ARRAY_SIZE(layout->oobfree) && + layout->oobfree[i].length; i++) layout->oobavail += layout->oobfree[i].length; nand->write_page = nand_davinci_write_page; diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index ef23ca278a..5e1502ed96 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -4745,7 +4745,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP3_17_15, GP_0_30_FN, FN_IP3_14_12, GP_0_29_FN, FN_IP3_11_8, @@ -4777,9 +4777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_11_9, GP_0_2_FN, FN_IP0_8_6, GP_0_1_FN, FN_IP0_5_3, - GP_0_0_FN, FN_IP0_2_0 } + GP_0_0_FN, FN_IP0_2_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, GP_1_29_FN, FN_IP6_13_11, @@ -4811,9 +4811,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP3_28_26, GP_1_2_FN, FN_IP3_25_23, GP_1_1_FN, FN_IP3_22_20, - GP_1_0_FN, FN_IP3_19_18, } + GP_1_0_FN, FN_IP3_19_18, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 0, 0, 0, 0, GP_2_29_FN, FN_IP7_15_13, @@ -4845,9 +4845,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP8_3_2, GP_2_2_FN, FN_IP8_1_0, GP_2_1_FN, FN_IP7_30_29, - GP_2_0_FN, FN_IP7_28_27 } + GP_2_0_FN, FN_IP7_28_27 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP11_21_18, GP_3_30_FN, FN_IP11_17_15, GP_3_29_FN, FN_IP11_14_13, @@ -4879,9 +4879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP9_3_2, GP_3_2_FN, FN_IP9_1_0, GP_3_1_FN, FN_IP8_30_29, - GP_3_0_FN, FN_IP8_28 } + GP_3_0_FN, FN_IP8_28 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP14_18_16, GP_4_30_FN, FN_IP14_15_12, GP_4_29_FN, FN_IP14_11_9, @@ -4913,9 +4913,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP11_31_30, GP_4_2_FN, FN_IP11_29_27, GP_4_1_FN, FN_IP11_26_24, - GP_4_0_FN, FN_IP11_23_22 } + GP_4_0_FN, FN_IP11_23_22 )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( GP_5_31_FN, FN_IP7_24_22, GP_5_30_FN, FN_IP7_21_19, GP_5_29_FN, FN_IP7_18_16, @@ -4947,10 +4947,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP14_30_28, GP_5_2_FN, FN_IP14_27_25, GP_5_1_FN, FN_IP14_24_22, - GP_5_0_FN, FN_IP14_21_19 } + GP_5_0_FN, FN_IP14_21_19 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { + GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3), + GROUP( /* IP0_31 [1] */ 0, 0, /* IP0_30_27 [4] */ @@ -4983,10 +4984,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP0_2_0 [3] */ FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { + GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4), + GROUP( /* IP1_31_30 [2] */ 0, 0, 0, 0, /* IP1_29_28 [2] */ @@ -5020,10 +5022,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_3_0 [4] */ FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { + GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3), + GROUP( /* IP2_31_29 [3] */ 0, 0, 0, 0, 0, 0, 0, 0, /* IP2_28_26 [3] */ @@ -5049,10 +5052,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_5_3 [3] */ FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, /* IP2_2_0 [3] */ - FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } + FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { + GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4), + GROUP( /* IP3_31_29 [3] */ FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 0, 0, 0, @@ -5082,10 +5086,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_3_0 [4] */ FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, - 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP4_31_30 [2] */ 0, 0, 0, 0, /* IP4_29_27 [3] */ @@ -5115,10 +5120,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, /* IP4_2_0 [3] */ FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, - } + )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3), + GROUP( /* IP5_31_30 [2] */ 0, 0, 0, 0, /* IP5_29_27 [3] */ @@ -5152,10 +5158,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_INTC_EN0_N, FN_I2C1_SCL, /* IP5_2_0 [3] */ FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, - FN_VI2_R3, 0, 0, } + FN_VI2_R3, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3), + GROUP( /* IP6_31_29 [3] */ FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, @@ -5188,10 +5195,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, /* IP6_2_0 [3] */ FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, - FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { + GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), + GROUP( /* IP7_31 [1] */ 0, 0, /* IP7_30_29 [2] */ @@ -5223,11 +5231,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, /* IP7_2_0 [3] */ FN_ETH_MDIO, 0, FN_HRTS0_N_E, - FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2) { + GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2), + GROUP( /* IP8_31 [1] */ 0, 0, /* IP8_30_29 [2] */ @@ -5264,10 +5273,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP8_3_2 [2] */ FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, /* IP8_1_0 [2] */ - FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { + GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2), + GROUP( /* IP9_31_28 [4] */ FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, @@ -5299,10 +5309,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP9_3_2 [2] */ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, /* IP9_1_0 [2] */ - FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - 2, 4, 3, 4, 4, 4, 4, 3, 4) { + GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4), + GROUP( /* IP10_31_30 [2] */ 0, 0, 0, 0, /* IP10_29_26 [4] */ @@ -5338,10 +5349,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP10_3_0 [4] */ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, - FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } + FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { + GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4), + GROUP( /* IP11_31_30 [2] */ FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, /* IP11_29_27 [3] */ @@ -5373,10 +5385,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP11_3_0 [4] */ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, - FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2), + GROUP( /* IP12_31 [1] */ 0, 0, /* IP12_30_28 [3] */ @@ -5412,10 +5425,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP12_3_2 [2] */ FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, /* IP12_1_0 [2] */ - FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } + FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { + GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3), + GROUP( /* IP13_31 [1] */ 0, 0, /* IP13_30_29 [2] */ @@ -5448,10 +5462,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_2_0 [3] */ FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, - FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } + FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, - 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { + GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3), + GROUP( /* IP14_30 [1] */ 0, 0, /* IP14_30_28 [3] */ @@ -5486,10 +5501,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP14_2_0 [3] */ FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, - FN_REMOCON, 0, } + FN_REMOCON, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, - 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { + GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3), + GROUP( /* IP15_31_30 [2] */ 0, 0, 0, 0, /* IP15_29_28 [2] */ @@ -5521,10 +5537,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_IIC2_SCL, FN_I2C2_SCL, 0, /* IP15_2_0 [3] */ FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, - FN_LCDOUT15, FN_SCIF_CLK_B, 0, } + FN_LCDOUT15, FN_SCIF_CLK_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, - 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { + GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3), + GROUP( /* IP16_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5552,11 +5569,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, /* IP16_2_0 [3] */ FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, - FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { + GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1, + 1, 1, 1, 2, 1, 1, 2, 1, 1), + GROUP( /* SEL_SCIF1 [3] */ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, FN_SEL_SCIF1_4, 0, 0, 0, @@ -5602,11 +5620,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SOF3 [1] */ FN_SEL_SOF3_0, FN_SEL_SOF3_1, /* SEL_SOF0 [1] */ - FN_SEL_SOF0_0, FN_SEL_SOF0_1, } + FN_SEL_SOF0_0, FN_SEL_SOF0_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - 3, 1, 1, 1, 2, 1, 2, 1, 2, - 1, 1, 1, 3, 3, 2, 3, 2, 2) { + GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1, + 3, 3, 2, 3, 2, 2), + GROUP( /* RESERVED [3] */ 0, 0, 0, 0, 0, 0, 0, 0, /* SEL_TMU1 [1] */ @@ -5644,11 +5663,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SIM [2] */ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, /* SEL_SSI8 [2] */ - FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - 1, 1, 2, 4, 4, 2, 2, - 4, 2, 3, 2, 3, 2) { + GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2), + GROUP( /* SEL_IICDVFS [1] */ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, /* SEL_IIC0 [1] */ @@ -5679,7 +5698,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, FN_SEL_I2C2_4, 0, 0, 0, /* SEL_I2C1 [2] */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index 8166955459..d6095d6f67 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -5431,7 +5431,7 @@ static const struct { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP1_22_20, GP_0_30_FN, FN_IP1_19_17, GP_0_29_FN, FN_IP1_16_14, @@ -5463,9 +5463,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_3, GP_0_2_FN, FN_IP0_2, GP_0_1_FN, FN_IP0_1, - GP_0_0_FN, FN_IP0_0, } + GP_0_0_FN, FN_IP0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5497,9 +5497,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP2_2_0, GP_1_2_FN, FN_IP1_31_29, GP_1_1_FN, FN_IP1_28_26, - GP_1_0_FN, FN_IP1_25_23, } + GP_1_0_FN, FN_IP1_25_23, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_IP6_7_6, GP_2_30_FN, FN_IP6_5_3, GP_2_29_FN, FN_IP6_2_0, @@ -5531,9 +5531,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP4_4_2, GP_2_2_FN, FN_IP4_1_0, GP_2_1_FN, FN_IP3_30_28, - GP_2_0_FN, FN_IP3_27_25 } + GP_2_0_FN, FN_IP3_27_25 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP9_18_17, GP_3_30_FN, FN_IP9_16, GP_3_29_FN, FN_IP9_15_13, @@ -5565,9 +5565,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP7_12_11, GP_3_2_FN, FN_IP7_10_9, GP_3_1_FN, FN_IP7_8_6, - GP_3_0_FN, FN_IP7_5_3 } + GP_3_0_FN, FN_IP7_5_3 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP15_5_4, GP_4_30_FN, FN_IP15_3_2, GP_4_29_FN, FN_IP15_1_0, @@ -5599,9 +5599,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP9_24_23, GP_4_2_FN, FN_IP9_22_21, GP_4_1_FN, FN_IP9_20_19, - GP_4_0_FN, FN_VI0_CLK } + GP_4_0_FN, FN_VI0_CLK )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( GP_5_31_FN, FN_IP3_24_22, GP_5_30_FN, FN_IP13_9_7, GP_5_29_FN, FN_IP13_6_5, @@ -5633,9 +5633,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP11_18_17, GP_5_2_FN, FN_IP11_16_15, GP_5_1_FN, FN_IP11_14_12, - GP_5_0_FN, FN_IP11_11_9 } + GP_5_0_FN, FN_IP11_11_9 )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( GP_6_31_FN, FN_DU0_DOTCLKIN, GP_6_30_FN, FN_USB1_OVC, GP_6_29_FN, FN_IP14_31_29, @@ -5667,9 +5667,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_IP13_13, GP_6_2_FN, FN_IP13_12, GP_6_1_FN, FN_IP13_11, - GP_6_0_FN, FN_IP13_10 } + GP_6_0_FN, FN_IP13_10 )) }, - { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5701,11 +5701,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, FN_IP15_26_24, GP_7_2_FN, FN_IP15_23_21, GP_7_1_FN, FN_IP15_20_18, - GP_7_0_FN, FN_IP15_17_15 } + GP_7_0_FN, FN_IP15_17_15 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP0_31 [1] */ 0, 0, /* IP0_30_29 [2] */ @@ -5760,10 +5761,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP0_1 [1] */ FN_D1, 0, /* IP0_0 [1] */ - FN_D0, 0, } + FN_D0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2), + GROUP( /* IP1_31_29 [3] */ FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, 0, 0, 0, @@ -5796,10 +5798,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0, /* IP1_1_0 [2] */ FN_A7, FN_MSIOF1_SYNC, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) { + GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3), + GROUP( /* IP2_31_30 [2] */ 0, 0, 0, 0, /* IP2_29_27 [3] */ @@ -5832,10 +5835,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A20, FN_SPCLK, 0, 0, /* IP2_2_0 [3] */ FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0, - FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, } + FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) { + GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3), + GROUP( /* IP3_31 [1] */ 0, 0, /* IP3_30_28 [3] */ @@ -5870,10 +5874,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0, /* IP3_2_0 [3] */ FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) { + GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, + 3, 3, 2), + GROUP( /* IP4_31 [1] */ 0, 0, /* IP4_30_28 [3] */ @@ -5912,10 +5918,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 0, 0, 0, /* IP4_1_0 [2] */ - FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, } + FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, + )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) { + GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3), + GROUP( /* IP5_31_29 [3] */ FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 0, 0, 0, 0, 0, @@ -5950,10 +5958,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP5_2_0 [3] */ FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, FN_MSIOF2_TXD_D, FN_VI1_R3_B, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) { + GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3), + GROUP( /* IP6_31_30 [2] */ 0, 0, 0, 0, /* IP6_29_27 [3] */ @@ -5990,10 +5999,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP6_2_0 [3] */ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) { + GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3), + GROUP( /* IP7_31_30 [2] */ 0, 0, 0, 0, /* IP7_29_27 [3] */ @@ -6031,10 +6041,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_2_0 [3] */ FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, FN_SCIF_CLK_B, FN_GPS_MAG_D, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP8_31 [1] */ 0, 0, /* IP8_30_28 [3] */ @@ -6074,10 +6085,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, /* IP8_2_0 [3] */ FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) { + GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, + 1, 1, 3, 3), + GROUP( /* IP9_31_29 [3] */ FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, @@ -6117,10 +6130,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP9_2_0 [3] */ FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) { + GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3), + GROUP( /* IP10_31_29 [3] */ FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 0, 0, 0, @@ -6154,11 +6168,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, /* IP10_2_0 [3] */ FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, - FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, } + FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, - 3, 3, 3, 3, 3) { + GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, + 2, 3, 3, 3, 3, 3), + GROUP( /* IP11_31_30 [2] */ FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0, /* IP11_29_28 [2] */ @@ -6201,10 +6216,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP11_2_0 [3] */ FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, - FN_I2C1_SDA_D, 0, 0, 0, } + FN_I2C1_SDA_D, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { + GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2), + GROUP( /* IP12_31_30 [2] */ 0, 0, 0, 0, /* IP12_29_27 [3] */ @@ -6242,11 +6258,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP12_3_2 [2] */ FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, /* IP12_1_0 [2] */ - FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, } + FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, - 3, 2, 2, 3) { + GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, + 1, 1, 1, 3, 2, 2, 3), + GROUP( /* IP13_31 [1] */ 0, 0, /* IP13_30_28 [3] */ @@ -6293,10 +6310,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP13_2_0 [3] */ FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, FN_ADICLK_B, FN_MSIOF0_SS1_C, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, - 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) { + GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, + 1, 1, 2), + GROUP( /* IP14_31_29 [3] */ FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0, @@ -6336,10 +6355,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP14_2 [1] */ FN_SD2_CLK, FN_MMC_CLK, /* IP14_1_0 [2] */ - FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, } + FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, - 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) { + GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2), + GROUP( /* IP15_31_30 [2] */ 0, 0, 0, 0, /* IP15_29_27 [3] */ @@ -6377,10 +6397,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP15_3_2 [2] */ FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, /* IP15_1_0 [2] */ - FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, } + FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, - 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) { + GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3), + GROUP( /* IP16_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -6409,11 +6430,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP16_2_0 [3] */ FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, - 3, 2, 2, 2, 1, 2, 2, 2) { + GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2, + 2, 2, 1, 2, 2, 2), + GROUP( /* RESERVED [1] */ 0, 0, /* SEL_SCIF1 [2] */ @@ -6454,11 +6476,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_TSIF0 [2] */ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, /* SEL_SOF0 [2] */ - FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - 3, 1, 1, 3, 2, 1, 1, 2, 2, - 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { + GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2, + 1, 2, 2, 2, 1, 1, 1), + GROUP( /* SEL_SCIF0 [3] */ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, @@ -6502,11 +6525,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [1] */ 0, 0, /* SEL_SSI8 [1] */ - FN_SEL_SSI8_0, FN_SEL_SSI8_1, } + FN_SEL_SSI8_0, FN_SEL_SSI8_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 2, 2, 3, 2, 2, 2, 1) { + GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2, + 3, 2, 2, 2, 1), + GROUP( /* SEL_HSCIF2 [2] */ FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, @@ -6544,11 +6568,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [2] */ 0, 0, 0, 0, /* RESERVED [1] */ - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, - 3, 2, 2, 1, 1, 1, 1, 3, 2, - 2, 3, 1, 1, 1, 2, 2, 2, 2) { + GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1, + 1, 1, 2, 2, 2, 2), + GROUP( /* SEL_SOF1 [3] */ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, FN_SEL_SOF1_4, @@ -6590,7 +6615,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [2] */ 0, 0, 0, 0, /* RESERVED [2] */ - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 95bb5237d9..1c90412093 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -1991,7 +1991,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2023,9 +2023,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_3, GP_0_2_FN, FN_IP0_2, GP_0_1_FN, FN_IP0_1, - GP_0_0_FN, FN_IP0_0 } + GP_0_0_FN, FN_IP0_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2057,9 +2057,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP1_8, GP_1_2_FN, FN_IP1_7, GP_1_1_FN, FN_IP1_6, - GP_1_0_FN, FN_IP1_5, } + GP_1_0_FN, FN_IP1_5, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_A15, GP_2_30_FN, FN_A14, GP_2_29_FN, FN_A13, @@ -2091,9 +2091,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_D3, GP_2_2_FN, FN_D2, GP_2_1_FN, FN_D1, - GP_2_0_FN, FN_D0 } + GP_2_0_FN, FN_D0 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2125,9 +2125,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_A19, GP_3_2_FN, FN_A18, GP_3_1_FN, FN_A17, - GP_3_0_FN, FN_A16 } + GP_3_0_FN, FN_A16 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2159,9 +2159,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_VI0_VSYNC_N, GP_4_2_FN, FN_VI0_HSYNC_N, GP_4_1_FN, FN_VI0_CLKENB, - GP_4_0_FN, FN_VI0_CLK } + GP_4_0_FN, FN_VI0_CLK )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2193,9 +2193,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_VI1_VSYNC_N, GP_5_2_FN, FN_VI1_HSYNC_N, GP_5_1_FN, FN_VI1_CLKENB, - GP_5_0_FN, FN_VI1_CLK } + GP_5_0_FN, FN_VI1_CLK )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2227,9 +2227,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_IP2_3, GP_6_2_FN, FN_IP2_2, GP_6_1_FN, FN_IP2_1, - GP_6_0_FN, FN_IP2_0 } + GP_6_0_FN, FN_IP2_0 )) }, - { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2261,9 +2261,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, FN_IP3_3, GP_7_2_FN, FN_IP3_2, GP_7_1_FN, FN_IP3_1, - GP_7_0_FN, FN_IP3_0 } + GP_7_0_FN, FN_IP3_0 )) }, - { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) { + { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2295,9 +2295,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_8_3_FN, FN_IP4_3_2, GP_8_2_FN, FN_IP4_1, GP_8_1_FN, FN_IP4_0, - GP_8_0_FN, FN_VI4_CLK } + GP_8_0_FN, FN_VI4_CLK )) }, - { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) { + { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2329,9 +2329,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_9_3_FN, FN_IP5_2, GP_9_2_FN, FN_IP5_1, GP_9_1_FN, FN_IP5_0, - GP_9_0_FN, FN_VI5_CLK } + GP_9_0_FN, FN_VI5_CLK )) }, - { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) { + { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP( GP_10_31_FN, FN_CAN1_RX, GP_10_30_FN, FN_CAN1_TX, GP_10_29_FN, FN_CAN_CLK, @@ -2363,9 +2363,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_10_3_FN, FN_IP6_2, GP_10_2_FN, FN_HRTS0_N, GP_10_1_FN, FN_IP6_1, - GP_10_0_FN, FN_IP6_0 } + GP_10_0_FN, FN_IP6_0 )) }, - { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) { + { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP( 0, 0, 0, 0, GP_11_29_FN, FN_AVS2, @@ -2397,13 +2397,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_11_3_FN, FN_IP7_6, GP_11_2_FN, FN_IP7_5_4, GP_11_1_FN, FN_IP7_3_2, - GP_11_0_FN, FN_IP7_1_0 } + GP_11_0_FN, FN_IP7_1_0 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP0_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP0_27_24 [4] */ @@ -2455,13 +2456,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP0_1 [1] */ FN_DU0_DR1_DATA1, 0, /* IP0_0 [1] */ - FN_DU0_DR0_DATA0, 0 } + FN_DU0_DR0_DATA0, 0 )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP1_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP1_27_24 [4] */ @@ -2513,13 +2515,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_1 [1] */ FN_DU0_EXVSYNC_DU0_VSYNC, 0, /* IP1_0 [1] */ - FN_DU0_EXHSYNC_DU0_HSYNC, 0 } + FN_DU0_EXHSYNC_DU0_HSYNC, 0 )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, - 4, 4, - 4, 3, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 3, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP2_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP2_27_24 [4] */ @@ -2561,13 +2564,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_1 [1] */ FN_VI2_CLKENB, FN_AVB_RX_DV, /* IP2_0 [1] */ - FN_VI2_CLK, FN_AVB_RX_CLK } + FN_VI2_CLK, FN_AVB_RX_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, - 4, 4, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP3_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP3_27_24 [4] */ @@ -2607,12 +2611,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_1 [1] */ FN_VI3_CLKENB, FN_AVB_TXD4, /* IP3_0 [1] */ - FN_VI3_CLK, FN_AVB_TX_CLK } + FN_VI3_CLK, FN_AVB_TX_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, - 4, 3, 1, - 1, 1, 1, 2, 2, 2, - 2, 2, 2, 2, 2, 1, 2, 1, 1) { + GROUP(4, 3, 1, + 1, 1, 1, 2, 2, 2, + 2, 2, 2, 2, 2, 1, 2, 1, 1), + GROUP( /* IP4_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP4_27_25 [3] */ @@ -2648,13 +2653,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP4_1 [1] */ FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5, /* IP4_0 [1] */ - FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 } + FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, - 4, 4, - 4, 4, - 4, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 4, + 4, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP5_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP5_27_24 [4] */ @@ -2688,13 +2694,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP5_1 [1] */ FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B, /* IP5_0 [1] */ - FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B } + FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, - 4, 4, - 4, 1, 2, 1, - 2, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 1, 2, 1, + 2, 2, 2, 2, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP6_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP6_27_24 [4] */ @@ -2730,13 +2737,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP6_1 [1] */ FN_MSIOF0_SYNC, FN_HCTS0_N, /* IP6_0 [1] */ - FN_MSIOF0_SCK, FN_HSCK0 } + FN_MSIOF0_SCK, FN_HSCK0 )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, - 4, 4, - 3, 1, 1, 1, 1, 1, - 2, 2, 2, 2, - 1, 1, 2, 2, 2) { + GROUP(4, 4, + 3, 1, 1, 1, 1, 1, + 2, 2, 2, 2, + 1, 1, 2, 2, 2), + GROUP( /* IP7_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP7_27_24 [4] */ @@ -2770,7 +2778,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_3_2 [2] */ FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0, /* IP7_1_0 [2] */ - FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 } + FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 657ebca783..91ac815f3d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -4619,7 +4619,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP2_17_16, GP_0_30_FN, FN_IP2_15_14, GP_0_29_FN, FN_IP2_13_12, @@ -4651,9 +4651,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_27_26, GP_0_2_FN, FN_IP0_25, GP_0_1_FN, FN_IP0_24, - GP_0_0_FN, FN_IP0_23_22, } + GP_0_0_FN, FN_IP0_23_22, )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4685,9 +4685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP2_29_27, GP_1_2_FN, FN_IP2_26_24, GP_1_1_FN, FN_IP2_23_21, - GP_1_0_FN, FN_IP2_20_18, } + GP_1_0_FN, FN_IP2_20_18, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_IP6_7_6, GP_2_30_FN, FN_IP6_5_4, GP_2_29_FN, FN_IP6_3_2, @@ -4719,9 +4719,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP4_11_10, GP_2_2_FN, FN_IP4_9_8, GP_2_1_FN, FN_IP4_7_5, - GP_2_0_FN, FN_IP4_4_2 } + GP_2_0_FN, FN_IP4_4_2 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP8_22_20, GP_3_30_FN, FN_IP8_19_17, GP_3_29_FN, FN_IP8_16_15, @@ -4753,9 +4753,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP6_11, GP_3_2_FN, FN_IP6_10, GP_3_1_FN, FN_IP6_9, - GP_3_0_FN, FN_IP6_8 } + GP_3_0_FN, FN_IP6_8 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP11_17_16, GP_4_30_FN, FN_IP11_15_14, GP_4_29_FN, FN_IP11_13_11, @@ -4787,9 +4787,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP9_2_0, GP_4_2_FN, FN_IP8_31_29, GP_4_1_FN, FN_IP8_28_26, - GP_4_0_FN, FN_IP8_25_23 } + GP_4_0_FN, FN_IP8_25_23 )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4821,9 +4821,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP11_29_27, GP_5_2_FN, FN_IP11_26_24, GP_5_1_FN, FN_IP11_23_21, - GP_5_0_FN, FN_IP11_20_18 } + GP_5_0_FN, FN_IP11_20_18 )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4855,11 +4855,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_SD0_DATA1, GP_6_2_FN, FN_SD0_DATA0, GP_6_1_FN, FN_SD0_CMD, - GP_6_0_FN, FN_SD0_CLK } + GP_6_0_FN, FN_SD0_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, - 2, 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, + 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP0_31_30 [2] */ FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, /* IP0_29_28 [2] */ @@ -4909,11 +4910,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP0_1 [1] */ 0, 0, /* IP0_0 [1] */ - FN_SD1_CD, FN_CAN0_RX, } + FN_SD1_CD, FN_CAN0_RX, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, - 2, 2) { + GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, + 3, 2, 2, 2, 2), + GROUP( /* IP1_31_30 [2] */ FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, /* IP1_29_28 [2] */ @@ -4949,10 +4951,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_3_2 [2] */ FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, /* IP1_1_0 [2] */ - FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, } + FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { + GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2), + GROUP( /* IP2_31_30 [2] */ FN_A20, FN_SPCLK, 0, 0, /* IP2_29_27 [3] */ @@ -4984,10 +4987,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_3_2 [2] */ FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, /* IP2_1_0 [2] */ - FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, } + FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) { + GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, + 2, 2, 2, 2), + GROUP( /* IP3_31 [1] */ FN_RD_WR_N, FN_ATAG1_N, /* IP3_30 [1] */ @@ -5024,10 +5029,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_3_2 [2] */ FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N, /* IP3_1_0 [2] */ - FN_A21, FN_MOSI_IO0, 0, 0, } + FN_A21, FN_MOSI_IO0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { + GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2), + GROUP( /* IP4_31_30 [2] */ FN_DU0_DG4, FN_LCDOUT12, 0, 0, /* IP4_29_28 [2] */ @@ -5059,10 +5065,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, 0, 0, 0, 0, /* IP4_1_0 [2] */ - FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, } + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { + GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, + 2, 2, 2), + GROUP( /* IP5_31_30 [2] */ FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0, /* IP5_29_28 [2] */ @@ -5094,11 +5102,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP5_3_2 [2] */ FN_DU0_DG6, FN_LCDOUT14, 0, 0, /* IP5_1_0 [2] */ - FN_DU0_DG5, FN_LCDOUT13, 0, 0, } + FN_DU0_DG5, FN_LCDOUT13, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, - 2, 2) { + GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 2, 2, 2, 2), + GROUP( /* IP6_31_29 [3] */ FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK, FN_ADIDATA, 0, 0, @@ -5140,10 +5149,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, /* IP6_1_0 [2] */ - FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, } + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP7_31 [1] */ FN_DREQ0_N, FN_SCIFB1_RXD, /* IP7_30 [1] */ @@ -5177,10 +5187,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AVB_TXD1, FN_ADICLK, 0, 0, /* IP7_2_0 [3] */ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, - FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, } + FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { + GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3), + GROUP( /* IP8_31_29 [3] */ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, 0, FN_TS_SDEN_D, FN_FMCLK_C, 0, @@ -5212,10 +5223,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, /* IP8_2_0 [3] */ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, - FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } + FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) { + GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3), + GROUP( /* IP9_31 [1] */ 0, 0, /* IP9_30_28 [3] */ @@ -5248,10 +5260,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, FN_TPUTO1_C, 0, 0, /* IP9_2_0 [3] */ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, - 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, } + 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP10_31_30 [2] */ FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0, /* IP10_29_27 [3] */ @@ -5283,10 +5296,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, /* IP10_2_0 [3] */ FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { + GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3), + GROUP( /* IP11_31_30 [2] */ 0, 0, 0, 0, /* IP11_29_27 [3] */ @@ -5318,10 +5332,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, /* IP11_2_0 [3] */ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3), + GROUP( /* IP12_31_30 [2] */ 0, 0, 0, 0, /* IP12_29_27 [3] */ @@ -5353,10 +5368,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_CAN1_RX_C, FN_DACK1_B, 0, 0, /* IP12_2_0 [3] */ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, - 0, FN_DREQ1_N_B, 0, 0, } + 0, FN_DREQ1_N_B, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP13_31 [1] */ 0, 0, /* IP13_30 [1] */ @@ -5393,11 +5409,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, /* IP13_2_0 [3] */ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, - 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, } + 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, - 2, 1) { + GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1), + GROUP( /* SEL_ADG [2] */ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, /* RESERVED [1] */ @@ -5431,11 +5447,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_I2C05 [2] */ FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, /* RESERVED [1] */ - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, - 2, 2, 2, 1, 1, 2) { + GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, + 2, 2, 1, 1, 2, 2, 2, 1, 1, 2), + GROUP( /* SEL_IEB [2] */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, /* SEL_IIC0 [2] */ @@ -5482,11 +5499,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_HSCIF1 [1] */ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, /* RESERVED [2] */ - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* SEL_SCIF0 [2] */ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, /* SEL_SCIF1 [2] */ @@ -5539,7 +5557,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [1] */ 0, 0, /* RESERVED [1] */ - 0, 0, } + 0, 0, )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c index 89ae6f6ed7..ba17a55775 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7795.c +++ b/drivers/pinctrl/renesas/pfc-r8a7795.c @@ -2,7 +2,7 @@ /* * R8A7795 ES2.0+ processor support - PFC hardware block. * - * Copyright (C) 2015-2017 Renesas Electronics Corporation + * Copyright (C) 2015-2019 Renesas Electronics Corporation */ #include <common.h> @@ -202,8 +202,8 @@ #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) /* GPSR7 */ -#define GPSR7_3 FM(HDMI1_CEC) -#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_3 FM(GP7_03) +#define GPSR7_2 FM(GP7_02) #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) @@ -352,7 +352,7 @@ #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) @@ -463,7 +463,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -499,8 +499,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) -#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) -#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) +#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS \ @@ -592,8 +592,8 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS1), PINMUX_SINGLE(AVS2), PINMUX_SINGLE(CLKOUT), - PINMUX_SINGLE(HDMI0_CEC), - PINMUX_SINGLE(HDMI1_CEC), + PINMUX_SINGLE(GP7_02), + PINMUX_SINGLE(GP7_03), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -1131,7 +1131,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), @@ -1164,7 +1164,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), @@ -1223,7 +1223,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), @@ -1270,7 +1270,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), - PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), @@ -1279,7 +1279,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), @@ -1410,10 +1410,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), - PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), @@ -2133,22 +2132,6 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; -/* - HDMI ------------------------------------------------------------------- */ -static const unsigned int hdmi0_cec_pins[] = { - /* HDMI0_CEC */ - RCAR_GP_PIN(7, 2), -}; -static const unsigned int hdmi0_cec_mux[] = { - HDMI0_CEC_MARK, -}; -static const unsigned int hdmi1_cec_pins[] = { - /* HDMI1_CEC */ - RCAR_GP_PIN(7, 3), -}; -static const unsigned int hdmi1_cec_mux[] = { - HDMI1_CEC_MARK, -}; - /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -4227,8 +4210,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hdmi0_cec), - SH_PFC_PIN_GROUP(hdmi1_cec), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4613,14 +4594,6 @@ static const char * const du_groups[] = { "du_disp", }; -static const char * const hdmi0_groups[] = { - "hdmi0_cec", -}; - -static const char * const hdmi1_groups[] = { - "hdmi1_cec", -}; - static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -5039,8 +5012,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hdmi0), - SH_PFC_FUNCTION(hdmi1), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5090,7 +5061,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5122,9 +5093,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5156,9 +5127,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5190,9 +5161,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5224,9 +5195,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5258,9 +5229,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5292,9 +5263,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( GP_6_31_FN, GPSR6_31, GP_6_30_FN, GPSR6_30, GP_6_29_FN, GPSR6_29, @@ -5326,9 +5297,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5360,14 +5331,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, } + GP_7_0_FN, GPSR7_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -5375,9 +5346,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -5385,9 +5356,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -5395,9 +5366,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -5405,9 +5376,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -5415,9 +5386,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -5425,9 +5396,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -5435,9 +5406,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -5445,9 +5416,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -5455,9 +5426,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -5465,9 +5436,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -5475,9 +5446,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -5485,9 +5456,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -5495,9 +5466,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -5505,9 +5476,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -5515,9 +5486,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -5525,9 +5496,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( IP16_31_28 IP16_27_24 IP16_23_20 @@ -5535,9 +5506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP16_15_12 IP16_11_8 IP16_7_4 - IP16_3_0 } + IP16_3_0 )) }, - { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( IP17_31_28 IP17_27_24 IP17_23_20 @@ -5545,9 +5516,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_15_12 IP17_11_8 IP17_7_4 - IP17_3_0 } + IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5555,7 +5526,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP18_7_4 - IP18_3_0 } + IP18_3_0 )) }, #undef F_ #undef FM @@ -5563,8 +5534,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, + 1, 1, 1, 2, 2, 1, 2, 3), + GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 MOD_SEL0_26_25_24 @@ -5585,11 +5557,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_5 MOD_SEL0_4_3 /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, + 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 MOD_SEL1_26 @@ -5612,11 +5585,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3 MOD_SEL1_2 MOD_SEL1_1 - MOD_SEL1_0 } + MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 4, 4, 4, 3, 1) { + GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, + 1, 4, 4, 4, 3, 1), + GROUP( MOD_SEL2_31 MOD_SEL2_30 MOD_SEL2_29 @@ -5643,7 +5617,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1 */ 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_0 } + MOD_SEL2_0 )) }, { }, }; @@ -5764,8 +5738,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ } }, @@ -5899,10 +5873,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -6019,8 +5995,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(0, 15), /* D15 */ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ - [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ + [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ } }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 24fbbf19aa..a92c8ad18c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -2,7 +2,7 @@ /* * R8A7796 processor support - PFC hardware block. * - * Copyright (C) 2016-2017 Renesas Electronics Corp. + * Copyright (C) 2016-2019 Renesas Electronics Corp. * * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c * @@ -209,7 +209,7 @@ /* GPSR7 */ #define GPSR7_3 FM(GP7_03) -#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_2 FM(GP7_02) #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) @@ -358,7 +358,7 @@ #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) @@ -469,7 +469,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -502,12 +502,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) -#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) -#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) +#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS \ @@ -600,7 +600,7 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS2), PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(GP7_03), - PINMUX_SINGLE(HDMI0_CEC), + PINMUX_SINGLE(GP7_02), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -1024,35 +1024,35 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), @@ -1118,28 +1118,28 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), - PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), - PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), @@ -1172,7 +1172,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), @@ -1231,7 +1231,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), @@ -1277,8 +1277,8 @@ static const u16 pinmux_data[] = { /* IPSR14 */ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), - PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), @@ -1287,7 +1287,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), @@ -1415,10 +1415,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), - PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), @@ -1502,11 +1501,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), - /* I2C */ - PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), - /* * Static pins can not be muxed between different functions but * still need mark entries in the pinmux list. Add each static @@ -2143,15 +2137,6 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; -/* - HDMI ------------------------------------------------------------------- */ -static const unsigned int hdmi0_cec_pins[] = { - /* HDMI0_CEC */ - RCAR_GP_PIN(7, 2), -}; -static const unsigned int hdmi0_cec_mux[] = { - HDMI0_CEC_MARK, -}; - /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -4127,8 +4112,8 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[310]; - struct sh_pfc_pin_group automotive[33]; + struct sh_pfc_pin_group common[312]; + struct sh_pfc_pin_group automotive[30]; } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a_a), @@ -4163,6 +4148,9 @@ static const struct { SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -4171,7 +4159,6 @@ static const struct { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hdmi0_cec), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4443,9 +4430,6 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk), }, .automotive = { - SH_PFC_PIN_GROUP(canfd0_data_a), - SH_PFC_PIN_GROUP(canfd0_data_b), - SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), SH_PFC_PIN_GROUP(drif0_data1_a), @@ -4588,10 +4572,6 @@ static const char * const du_groups[] = { "du_disp", }; -static const char * const hdmi0_groups[] = { - "hdmi0_cec", -}; - static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -4985,8 +4965,8 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[48]; - struct sh_pfc_function automotive[6]; + struct sh_pfc_function common[49]; + struct sh_pfc_function automotive[4]; } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -4994,8 +4974,9 @@ static const struct { SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hdmi0), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5039,8 +5020,6 @@ static const struct { SH_PFC_FUNCTION(vin5), }, .automotive = { - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), @@ -5051,7 +5030,7 @@ static const struct { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5083,9 +5062,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5117,9 +5096,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5151,9 +5130,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5185,9 +5164,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5219,9 +5198,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5253,9 +5232,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( GP_6_31_FN, GPSR6_31, GP_6_30_FN, GPSR6_30, GP_6_29_FN, GPSR6_29, @@ -5287,9 +5266,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5321,14 +5300,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, } + GP_7_0_FN, GPSR7_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -5336,9 +5315,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -5346,9 +5325,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -5356,9 +5335,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -5366,9 +5345,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -5376,9 +5355,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -5386,9 +5365,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -5396,9 +5375,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -5406,9 +5385,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -5416,9 +5395,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -5426,9 +5405,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -5436,9 +5415,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -5446,9 +5425,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -5456,9 +5435,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -5466,9 +5445,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -5476,9 +5455,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -5486,9 +5465,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( IP16_31_28 IP16_27_24 IP16_23_20 @@ -5496,9 +5475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP16_15_12 IP16_11_8 IP16_7_4 - IP16_3_0 } + IP16_3_0 )) }, - { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( IP17_31_28 IP17_27_24 IP17_23_20 @@ -5506,9 +5485,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_15_12 IP17_11_8 IP17_7_4 - IP17_3_0 } + IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5516,7 +5495,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP18_7_4 - IP18_3_0 } + IP18_3_0 )) }, #undef F_ #undef FM @@ -5524,8 +5503,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, + 1, 1, 1, 2, 2, 1, 2, 3), + GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 MOD_SEL0_26_25_24 @@ -5546,11 +5526,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_5 MOD_SEL0_4_3 /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, + 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 MOD_SEL1_26 @@ -5573,11 +5554,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3 MOD_SEL1_2 MOD_SEL1_1 - MOD_SEL1_0 } + MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 4, 4, 4, 3, 1) { + GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, + 1, 4, 4, 4, 3, 1), + GROUP( MOD_SEL2_31 MOD_SEL2_30 MOD_SEL2_29 @@ -5603,7 +5585,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1 */ 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_0 } + MOD_SEL2_0 )) }, { }, }; @@ -5724,7 +5706,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ @@ -5858,10 +5840,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -5978,7 +5962,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(0, 15), /* D15 */ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 7c24836d2c..2523904aec 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -3,7 +3,7 @@ * R8A77965 processor support - PFC hardware block. * * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> - * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016-2019 Renesas Electronics Corp. * * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c * @@ -210,7 +210,7 @@ /* GPSR7 */ #define GPSR7_3 FM(GP7_03) -#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_2 FM(GP7_02) #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) @@ -359,7 +359,7 @@ #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) @@ -470,7 +470,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -503,12 +503,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) -#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) -#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) +#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS \ @@ -560,6 +560,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) + enum { PINMUX_RESERVED = 0, @@ -585,6 +588,7 @@ enum { PINMUX_IPSR PINMUX_MOD_SELS PINMUX_STATIC + PINMUX_PHYS PINMUX_MARK_END, #undef F_ #undef FM @@ -597,7 +601,7 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS2), PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(GP7_03), - PINMUX_SINGLE(HDMI0_CEC), + PINMUX_SINGLE(GP7_02), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -622,13 +626,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), - PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -681,14 +687,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1019,35 +1027,35 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), @@ -1114,26 +1122,28 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), - PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), - PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), - PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), - PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), - PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), @@ -1166,7 +1176,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), @@ -1225,7 +1235,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), @@ -1271,8 +1281,8 @@ static const u16 pinmux_data[] = { /* IPSR14 */ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), - PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), @@ -1281,7 +1291,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), @@ -1410,10 +1420,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), - PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), @@ -1497,11 +1506,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), - /* I2C */ - PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), - /* * Static pins can not be muxed between different functions but * still need mark entries in the pinmux list. Add each static @@ -2481,52 +2485,92 @@ static const unsigned int hscif4_data_b_mux[] = { }; /* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; + static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), }; + static const unsigned int i2c1_a_mux[] = { SDA1_A_MARK, SCL1_A_MARK, }; + static const unsigned int i2c1_b_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), }; + static const unsigned int i2c1_b_mux[] = { SDA1_B_MARK, SCL1_B_MARK, }; + static const unsigned int i2c2_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), }; + static const unsigned int i2c2_a_mux[] = { SDA2_A_MARK, SCL2_A_MARK, }; + static const unsigned int i2c2_b_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), }; + static const unsigned int i2c2_b_mux[] = { SDA2_B_MARK, SCL2_B_MARK, }; + +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; + +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + static const unsigned int i2c6_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), }; + static const unsigned int i2c6_a_mux[] = { SDA6_A_MARK, SCL6_A_MARK, }; + static const unsigned int i2c6_b_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), }; + static const unsigned int i2c6_b_mux[] = { SDA6_B_MARK, SCL6_B_MARK, }; + static const unsigned int i2c6_c_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), }; + static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; @@ -4416,10 +4460,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), @@ -4810,6 +4857,10 @@ static const char * const hscif4_groups[] = { "hscif4_data_b", }; +static const char * const i2c0_groups[] = { + "i2c0", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -4820,6 +4871,14 @@ static const char * const i2c2_groups[] = { "i2c2_b", }; +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + static const char * const i2c6_groups[] = { "i2c6_a", "i2c6_b", @@ -5169,8 +5228,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), @@ -5208,7 +5270,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5240,9 +5302,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5274,9 +5336,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5308,9 +5370,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5342,9 +5404,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5376,9 +5438,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5410,9 +5472,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( GP_6_31_FN, GPSR6_31, GP_6_30_FN, GPSR6_30, GP_6_29_FN, GPSR6_29, @@ -5444,9 +5506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5478,14 +5540,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, } + GP_7_0_FN, GPSR7_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -5493,9 +5555,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -5503,9 +5565,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -5513,9 +5575,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -5523,9 +5585,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -5533,9 +5595,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -5543,9 +5605,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -5553,9 +5615,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -5563,9 +5625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -5573,9 +5635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -5583,9 +5645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -5593,9 +5655,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -5603,9 +5665,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -5613,9 +5675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -5623,9 +5685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -5633,9 +5695,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -5643,9 +5705,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( IP16_31_28 IP16_27_24 IP16_23_20 @@ -5653,9 +5715,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP16_15_12 IP16_11_8 IP16_7_4 - IP16_3_0 } + IP16_3_0 )) }, - { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( IP17_31_28 IP17_27_24 IP17_23_20 @@ -5663,9 +5725,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_15_12 IP17_11_8 IP17_7_4 - IP17_3_0 } + IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5673,7 +5735,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP18_7_4 - IP18_3_0 } + IP18_3_0 )) }, #undef F_ #undef FM @@ -5681,8 +5743,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, + 1, 1, 1, 2, 2, 1, 2, 3), + GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 MOD_SEL0_26_25_24 @@ -5703,11 +5766,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_5 MOD_SEL0_4_3 /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, + 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 MOD_SEL1_26 @@ -5730,11 +5794,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3 MOD_SEL1_2 MOD_SEL1_1 - MOD_SEL1_0 } + MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 4, 4, 4, 3, 1) { + GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, + 1, 4, 4, 4, 3, 1), + GROUP( MOD_SEL2_31 MOD_SEL2_30 MOD_SEL2_29 @@ -5760,7 +5825,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1 */ 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_0 } + MOD_SEL2_0 )) }, { }, }; @@ -5881,7 +5946,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ @@ -6015,10 +6080,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -6135,7 +6202,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(0, 15), /* D15 */ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 823edb559d..33ecd93398 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -173,19 +173,19 @@ #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -200,18 +200,18 @@ #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -472,7 +472,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), - PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT), PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), @@ -498,7 +497,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), - PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), PINMUX_IPSR_GPSR(IP3_15_12, HRX3), PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), @@ -529,7 +528,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), PINMUX_IPSR_GPSR(IP4_11_8, HRX1), - PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), @@ -619,7 +618,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5), PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), - PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS), + PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N), PINMUX_IPSR_GPSR(IP6_23_20, D12), PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6), PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1), @@ -666,7 +665,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1), PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), - PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC), PINMUX_IPSR_GPSR(IP7_23_20, SCL2), @@ -1470,7 +1469,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ @@ -1493,7 +1492,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; static const unsigned int scif1_data_b_pins[] = { /* RX, TX */ @@ -1523,7 +1522,7 @@ static const unsigned int scif3_ctrl_pins[] = { RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), }; static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_TANS_MARK, CTS3_N_MARK, + RTS3_N_MARK, CTS3_N_MARK, }; /* - SCIF4 ------------------------------------------------------------------ */ @@ -1546,7 +1545,7 @@ static const unsigned int scif4_ctrl_pins[] = { RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), }; static const unsigned int scif4_ctrl_mux[] = { - RTS4_N_TANS_MARK, CTS4_N_MARK, + RTS4_N_MARK, CTS4_N_MARK, }; /* - TMU -------------------------------------------------------------------- */ @@ -2074,7 +2073,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2106,9 +2105,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2140,9 +2139,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2174,9 +2173,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2208,9 +2207,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2242,9 +2241,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2276,14 +2275,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -2291,9 +2290,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -2301,9 +2300,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -2311,9 +2310,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -2321,9 +2320,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -2331,9 +2330,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -2341,9 +2340,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -2351,9 +2350,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -2361,9 +2360,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_15_12 IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -2371,7 +2370,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, #undef F_ #undef FM @@ -2379,8 +2378,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 4, 4, 4, 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( /* RESERVED 31, 30, 29, 28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 27, 26, 25, 24 */ @@ -2402,21 +2402,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_3 MOD_SEL0_2 MOD_SEL0_1 - MOD_SEL0_0 } + MOD_SEL0_0 )) }, { }, }; enum ioctrl_regs { - IOCTRL30, - IOCTRL31, - IOCTRL32, + POCCTRL0, + POCCTRL1, + POCCTRL2, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { - [IOCTRL30] = { 0xe6060380 }, - [IOCTRL31] = { 0xe6060384 }, - [IOCTRL32] = { 0xe6060388 }, + [POCCTRL0] = { 0xe6060380 }, + [POCCTRL1] = { 0xe6060384 }, + [POCCTRL2] = { 0xe6060388 }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -2425,13 +2427,13 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, { int bit = pin & 0x1f; - *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) return bit; if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) return bit + 22; - *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg; + *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) return bit - 10; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 1cf08ae471..5313f2f509 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -2,7 +2,7 @@ /* * R8A77990 processor support - PFC hardware block. * - * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018-2019 Renesas Electronics Corp. * * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c * @@ -168,7 +168,7 @@ #define GPSR5_7 F_(SCK2_A, IP12_7_4) #define GPSR5_6 F_(TX1, IP12_3_0) #define GPSR5_5 F_(RX1, IP11_31_28) -#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20) +#define GPSR5_4 F_(RTS0_N_A, IP11_23_20) #define GPSR5_3 F_(CTS0_N_A, IP11_19_16) #define GPSR5_2 F_(TX0_A, IP11_15_12) #define GPSR5_1 F_(RX0_A, IP11_11_8) @@ -222,7 +222,7 @@ #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -243,10 +243,10 @@ #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -292,8 +292,8 @@ #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ @@ -417,7 +417,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3)) #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0)) -#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) @@ -432,8 +432,6 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0)) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ -#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) -#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) @@ -454,8 +452,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM #define PINMUX_MOD_SELS \ \ - MOD_SEL1_31 \ -MOD_SEL0_30_29 MOD_SEL1_30 \ +MOD_SEL0_30_29 \ MOD_SEL1_29 \ MOD_SEL0_28 MOD_SEL1_28 \ MOD_SEL0_27_26 \ @@ -674,7 +671,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), PINMUX_IPSR_GPSR(IP3_15_12, A4), - PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0), PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), @@ -824,7 +821,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), - PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2), PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), PINMUX_IPSR_GPSR(IP5_31_28, D2), @@ -848,7 +845,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), - PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0), PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), @@ -987,23 +984,23 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), - PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1), /* IPSR9 */ PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), - PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), - PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), - PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), @@ -1040,57 +1037,57 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), - PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A), + PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), - PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B), PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), - PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A), + PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), - PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B), PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), /* IPSR11 */ PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), - PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), - PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0), + PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A), PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), - PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), + PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A), PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), - PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), - PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0), - PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), @@ -1099,7 +1096,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), - PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID), @@ -1183,7 +1180,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), - PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), + PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A), PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1), @@ -1251,7 +1248,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), - PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B), PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), @@ -2842,7 +2839,7 @@ static const unsigned int scif0_ctrl_a_pins[] = { }; static const unsigned int scif0_ctrl_a_mux[] = { - RTS0_N_TANS_A_MARK, CTS0_N_A_MARK, + RTS0_N_A_MARK, CTS0_N_A_MARK, }; static const unsigned int scif0_data_b_pins[] = { @@ -2888,7 +2885,7 @@ static const unsigned int scif1_ctrl_pins[] = { }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; /* - SCIF2 ------------------------------------------------------------------ */ @@ -2944,7 +2941,7 @@ static const unsigned int scif3_ctrl_a_pins[] = { }; static const unsigned int scif3_ctrl_a_mux[] = { - RTS3_N_TANS_A_MARK, CTS3_N_A_MARK, + RTS3_N_A_MARK, CTS3_N_A_MARK, }; static const unsigned int scif3_data_b_pins[] = { @@ -2999,7 +2996,7 @@ static const unsigned int scif4_ctrl_a_pins[] = { }; static const unsigned int scif4_ctrl_a_mux[] = { - RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, + RTS4_N_A_MARK, CTS4_N_A_MARK, }; static const unsigned int scif4_data_b_pins[] = { @@ -3035,7 +3032,7 @@ static const unsigned int scif4_ctrl_c_pins[] = { }; static const unsigned int scif4_ctrl_c_mux[] = { - RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, + RTS4_N_C_MARK, CTS4_N_C_MARK, }; /* - SCIF5 ------------------------------------------------------------------ */ @@ -3769,8 +3766,8 @@ static const unsigned int vin5_clk_b_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[245]; - struct sh_pfc_pin_group automotive[23]; + struct sh_pfc_pin_group common[247]; + struct sh_pfc_pin_group automotive[21]; } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -3801,6 +3798,8 @@ static const struct { SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_in_0), @@ -4020,8 +4019,6 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk_b), }, .automotive = { - SH_PFC_PIN_GROUP(canfd0_data), - SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), SH_PFC_PIN_GROUP(drif0_data1_a), @@ -4468,8 +4465,8 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[45]; - struct sh_pfc_function automotive[6]; + struct sh_pfc_function common[47]; + struct sh_pfc_function automotive[4]; } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -4477,6 +4474,8 @@ static const struct { SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -4519,8 +4518,6 @@ static const struct { SH_PFC_FUNCTION(vin5), }, .automotive = { - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), @@ -4531,7 +4528,7 @@ static const struct { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4563,9 +4560,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4597,9 +4594,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4631,9 +4628,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4665,9 +4662,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4699,9 +4696,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4733,9 +4730,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4767,14 +4764,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -4782,9 +4779,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -4792,9 +4789,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -4802,9 +4799,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -4812,9 +4809,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -4822,9 +4819,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -4832,9 +4829,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -4842,9 +4839,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -4852,9 +4849,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_15_12 IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -4862,9 +4859,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -4872,9 +4869,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -4882,9 +4879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -4892,9 +4889,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -4902,9 +4899,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -4912,9 +4909,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -4922,9 +4919,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -4932,7 +4929,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, #undef F_ #undef FM @@ -4940,8 +4937,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, - 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) { + GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1, + 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2), + GROUP( /* RESERVED 31 */ 0, 0, MOD_SEL0_30_29 @@ -4965,13 +4963,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_4 MOD_SEL0_3 MOD_SEL0_2 - MOD_SEL0_1_0 } + MOD_SEL0_1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, - 1, 2, 2, 2, 1, 1, 2, 1, 4) { - MOD_SEL1_31 - MOD_SEL1_30 + GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1, + 2, 2, 2, 1, 1, 2, 1, 4), + GROUP( + /* RESERVED 31, 30 */ + 0, 0, 0, 0, MOD_SEL1_29 MOD_SEL1_28 /* RESERVED 27 */ @@ -4992,17 +4991,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_6_5 MOD_SEL1_4 /* RESERVED 3, 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) }, { }, }; enum ioctrl_regs { - IOCTRL30, + POCCTRL0, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { - [IOCTRL30] = { 0xe6060380, }, + [POCCTRL0] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -5011,7 +5012,7 @@ static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, { int bit = -EINVAL; - *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) bit = pin & 0x1f; @@ -5127,7 +5128,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */ - [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */ + [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */ [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index ed678584cb..724cf4ae3c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -290,7 +290,7 @@ #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -301,7 +301,7 @@ /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -860,7 +860,7 @@ static const u16 pinmux_data[] = { /* IPSR11 */ PINMUX_IPSR_GPSR(IP11_3_0, SDA1), - PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N), PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), @@ -895,7 +895,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), - PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N), PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), PINMUX_IPSR_GPSR(IP12_11_8, SCK2), @@ -1707,7 +1707,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ static const unsigned int scif1_data_a_pins[] = { @@ -1743,7 +1743,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; /* - SCIF2 ------------------------------------------------------------------ */ @@ -2377,7 +2377,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2409,9 +2409,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( GP_1_31_FN, GPSR1_31, GP_1_30_FN, GPSR1_30, GP_1_29_FN, GPSR1_29, @@ -2443,9 +2443,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( GP_2_31_FN, GPSR2_31, GP_2_30_FN, GPSR2_30, GP_2_29_FN, GPSR2_29, @@ -2477,9 +2477,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2511,9 +2511,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( GP_4_31_FN, GPSR4_31, GP_4_30_FN, GPSR4_30, GP_4_29_FN, GPSR4_29, @@ -2545,9 +2545,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2579,9 +2579,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2613,14 +2613,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -2628,9 +2628,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -2638,9 +2638,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -2648,9 +2648,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -2658,9 +2658,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -2668,9 +2668,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -2678,9 +2678,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -2688,9 +2688,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -2698,9 +2698,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_15_12 IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -2708,9 +2708,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -2718,9 +2718,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -2728,9 +2728,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -2738,9 +2738,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -2748,9 +2748,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2758,7 +2758,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, #undef F_ #undef FM @@ -2766,8 +2766,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, - 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) { + GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, + 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1), + GROUP( /* RESERVED 31 */ 0, 0, MOD_SEL0_30 @@ -2795,11 +2796,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_3 MOD_SEL0_2 MOD_SEL0_1 - MOD_SEL0_0 } + MOD_SEL0_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 1, 1, 1, 1, 1, 1, 2, 4, 4, - 4, 4, 4, 4) { + GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4), + GROUP( MOD_SEL1_31 MOD_SEL1_30 MOD_SEL1_29 @@ -2819,7 +2820,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED 7, 6, 5, 4 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) }, { }, }; @@ -2836,6 +2837,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po return bit; } +enum ioctrl_regs { + TDSELCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [TDSELCTRL] = { 0xe60603c0, }, + { /* sentinel */ }, +}; + static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { .pin_to_pocctrl = r8a77995_pin_to_pocctrl, }; @@ -2855,6 +2865,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index d1271dad44..f2973bebef 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -469,7 +469,7 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev, const struct sh_pfc_pin *pin = NULL; int i, ret, idx; - for (i = 1; i < pfc->info->nr_pins; i++) { + for (i = 0; i < pfc->info->nr_pins; i++) { if (priv->pfc.info->pins[i].pin != pin_selector) continue; @@ -505,7 +505,7 @@ static int sh_pfc_gpio_disable_free(struct udevice *dev, const struct sh_pfc_pin *pin = NULL; int i, idx; - for (i = 1; i < pfc->info->nr_pins; i++) { + for (i = 0; i < pfc->info->nr_pins; i++) { if (priv->pfc.info->pins[i].pin != pin_selector) continue; diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 6629e1f772..f6159b8a3a 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -41,7 +41,8 @@ struct sh_pfc_pin { .name = #alias, \ .pins = n##_pins, \ .mux = n##_mux, \ - .nr_pins = ARRAY_SIZE(n##_pins), \ + .nr_pins = ARRAY_SIZE(n##_pins) + \ + BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ } #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) @@ -110,40 +111,54 @@ struct pinmux_func { struct pinmux_cfg_reg { u32 reg; u8 reg_width, field_width; +#ifdef DEBUG + u16 nr_enum_ids; /* for variable width regs only */ +#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n, +#else +#define SET_NR_ENUM_IDS(n) +#endif const u16 *enum_ids; const u8 *var_field_width; }; +#define GROUP(...) __VA_ARGS__ + /* * Describe a config register consisting of several fields of the same width * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) * - f_width: Width of the fixed-width register fields (in bits) - * This macro must be followed by initialization data: For each register field - * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified, - * one for each possible combination of the register field bit values. + * - ids: For each register field (from left to right, i.e. MSB to LSB), + * 2^f_width enum IDs must be specified, one for each possible + * combination of the register field bit values, all wrapped using + * the GROUP() macro. */ -#define PINMUX_CFG_REG(name, r, r_width, f_width) \ - .reg = r, .reg_width = r_width, .field_width = f_width, \ - .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) +#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \ + .reg = r, .reg_width = r_width, \ + .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ + BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ + (r_width / f_width) * (1 << f_width)), \ + .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ + { ids } /* * Describe a config register consisting of several fields of different widths * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) - * - var_fw0, var_fwn...: List of widths of the register fields (in bits), - * From left to right (i.e. MSB to LSB) - * This macro must be followed by initialization data: For each register field - * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified, - * one for each possible combination of the register field bit values. + * - f_widths: List of widths of the register fields (in bits), from left + * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. + * - ids: For each register field (from left to right, i.e. MSB to LSB), + * 2^f_widths[i] enum IDs must be specified, one for each possible + * combination of the register field bit values, all wrapped using + * the GROUP() macro. */ -#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ - .reg = r, .reg_width = r_width, \ - .var_field_width = (const u8 [r_width]) \ - { var_fw0, var_fwn, 0 }, \ - .enum_ids = (const u16 []) +#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ + .reg = r, .reg_width = r_width, \ + .var_field_width = (const u8 []) { f_widths, 0 }, \ + SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ + .enum_ids = (const u16 []) { ids } struct pinmux_drive_reg_field { u16 pin; @@ -186,12 +201,14 @@ struct pinmux_data_reg { * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) - * This macro must be followed by initialization data: For each register bit - * (from left to right, i.e. MSB to LSB), one enum ID must be specified. + * - ids: For each register bit (from left to right, i.e. MSB to LSB), one + * enum ID must be specified, all wrapped using the GROUP() macro. */ -#define PINMUX_DATA_REG(name, r, r_width) \ - .reg = r, .reg_width = r_width, \ - .enum_ids = (const u16 [r_width]) \ +#define PINMUX_DATA_REG(name, r, r_width, ids) \ + .reg = r, .reg_width = r_width + \ + BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ + r_width), \ + .enum_ids = (const u16 [r_width]) { ids } struct pinmux_irq { const short *gpios; @@ -371,8 +388,8 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; /* * Describe a pinmux configuration in which a pin is physically multiplexed * with other pins. - * - ipsr: IPSR field - * - fn: Function name, also referring to the IPSR field + * - ipsr: IPSR field (unused, for documentation purposes only) + * - fn: Function name * - psel: Physical multiplexing selector */ #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ @@ -632,7 +649,9 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; */ #define PORTCR(nr, reg) \ { \ - PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ + PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ + GROUP(2, 2, 1, 3), \ + GROUP( \ /* PULMD[1:0], handled by .set_bias() */ \ 0, 0, 0, 0, \ /* IE and OE */ \ @@ -644,7 +663,7 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT##nr##_FN2, PORT##nr##_FN3, \ PORT##nr##_FN4, PORT##nr##_FN5, \ PORT##nr##_FN6, PORT##nr##_FN7 \ - } \ + )) \ } /* diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 29ecac40a2..c64be38e49 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -24,6 +24,8 @@ #include "ipu.h" #include "mxcfb.h" #include "ipu_regs.h" +#include "display.h" +#include <panel.h> #include <dm.h> #include <video.h> @@ -609,6 +611,7 @@ void *video_hw_init(void) ret = mxcfb_probe(gpixfmt, gdisp, gmode); debug("Framebuffer at 0x%x\n", (unsigned int)panel.frameAdrs); + gd->fb_base = panel.frameAdrs; return (void *)&panel; } @@ -636,6 +639,10 @@ static int ipuv3_video_probe(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); +#if defined(CONFIG_DISPLAY) + struct udevice *disp_dev; +#endif + struct udevice *panel_dev; u32 fb_start, fb_end; int ret; @@ -654,6 +661,18 @@ static int ipuv3_video_probe(struct udevice *dev) if (ret < 0) return ret; +#if defined(CONFIG_DISPLAY) + ret = uclass_first_device(UCLASS_DISPLAY, &disp_dev); + if (disp_dev) { + ret = display_enable(disp_dev, 16, NULL); + if (ret < 0) + return ret; + } +#endif + ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev); + if (panel_dev) + panel_enable_backlight(panel_dev); + uc_priv->xsize = gmode->xres; uc_priv->ysize = gmode->yres; uc_priv->bpix = LCD_MAX_LOG2_BPP; @@ -665,6 +684,7 @@ static int ipuv3_video_probe(struct udevice *dev) mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, DCACHE_WRITEBACK); video_set_flush_dcache(dev, true); + gd->fb_base = fb_start; return 0; } diff --git a/include/ACEX1K.h b/include/ACEX1K.h index 9814bba284..7c5253c66c 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -60,6 +60,16 @@ typedef struct { #define Altera_EP2C35_SIZE 883905 #define Altera_EP3C5_SIZE 368011 /* .rbf size in bytes */ +#define ALTERA_EP4CE6_SIZE 368011 /* 2944088 Bits */ +#define ALTERA_EP4CE10_SIZE 368011 /* 2944088 Bits */ +#define ALTERA_EP4CE15_SIZE 510856 /* 4086848 Bits */ +#define ALTERA_EP4CE22_SIZE 718569 /* 5748552 Bits */ +#define ALTERA_EP4CE30_SIZE 1191788 /* 9534304 Bits */ +#define ALTERA_EP4CE40_SIZE 1191788 /* 9534304 Bits */ +#define ALTERA_EP4CE55_SIZE 1861195 /* 14889560 Bits */ +#define ALTERA_EP4CE75_SIZE 2495719 /* 19965752 Bits */ +#define ALTERA_EP4CE115_SIZE 3571462 /* 28571696 Bits */ + /* Descriptor Macros *********************************************************************/ /* ACEX1K devices */ diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 7c2220643b..5372d5d8cd 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -33,7 +33,7 @@ typedef struct global_data { /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */ unsigned long pci_clk; unsigned long mem_clk; -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) +#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) unsigned long fb_base; /* Base address of framebuffer mem */ #endif #if defined(CONFIG_POST) diff --git a/include/autoboot.h b/include/autoboot.h index 3ebd6f90e3..ac8157e570 100644 --- a/include/autoboot.h +++ b/include/autoboot.h @@ -27,7 +27,7 @@ const char *bootdelay_process(void); * autoboot_command() - run the autoboot command * * If enabled, run the autoboot command returned from bootdelay_process(). - * Also do the CONFIG_MENUKEY processing if enabled. + * Also do the CONFIG_AUTOBOOT_MENUKEY processing if enabled. * * @cmd: Command to run */ diff --git a/include/clk.h b/include/clk.h index f8f56d9cf0..2ebc905e04 100644 --- a/include/clk.h +++ b/include/clk.h @@ -356,4 +356,13 @@ static inline bool clk_valid(struct clk *clk) * @return zero on success, or -ENOENT on error */ int clk_get_by_id(ulong id, struct clk **clkp); + +/** + * clk_dev_binded() - Check whether the clk has a device binded + * + * @clk A pointer to the clk + * + * @return true on binded, or false on no + */ +bool clk_dev_binded(struct clk *clk); #endif diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 7640d7610d..7352e34b9c 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -347,10 +347,6 @@ #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=mpc8349emds\0" \ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 493f6df187..2ae1069e4f 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -404,10 +404,6 @@ #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=mpc8349emds\0" \ diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index e4ebd339de..64172f3619 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -11,7 +11,6 @@ #define CONFIG_CPU_SH7722 1 #define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SHOW_BOOT_PROGRESS /* SMC9111 */ #define CONFIG_SMC91111 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 0da34d05af..9bf5d9d3fd 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -236,10 +236,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 400000 -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=tqm834x\0" \ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 6368872e5b..f4a000f020 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -258,6 +258,4 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 1 - -#define CONFIG_SHOW_BOOT_PROGRESS #endif /* ! __CONFIG_AM335X_SHC_H */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index cacd799aa2..5fa393d45d 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -68,15 +68,6 @@ */ #ifdef CONFIG_USB_AM35X - -#ifdef CONFIG_USB_MUSB_HCD - -#ifdef CONFIG_USB_KEYBOARD -#define CONFIG_PREBOOT "usb start" -#endif /* CONFIG_USB_KEYBOARD */ - -#endif /* CONFIG_USB_MUSB_HCD */ - #ifdef CONFIG_USB_MUSB_UDC /* USB device configuration */ #define CONFIG_USB_DEVICE 1 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index c2c5c1f668..63489133a8 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -29,18 +29,6 @@ #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 -#ifdef CONFIG_USB_MUSB_AM35X - -#ifdef CONFIG_USB_MUSB_HOST - -#ifdef CONFIG_USB_KEYBOARD -#define CONFIG_PREBOOT "usb start" -#endif /* CONFIG_USB_KEYBOARD */ - -#endif /* CONFIG_USB_MUSB_HOST */ - -#endif /* CONFIG_USB_MUSB_AM35X */ - /* I2C */ /* Ethernet */ diff --git a/include/configs/apf27.h b/include/configs/apf27.h index b7a7ec5ee0..044ce4467e 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -83,7 +83,6 @@ #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot argument buffer size */ -#define CONFIG_PREBOOT "run check_flash check_env;" /* * Boot Linux diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 0cb40e721c..0d170ec993 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -14,8 +14,6 @@ #define BOARD_LATE_INIT -#undef CONFIG_SHOW_BOOT_PROGRESS - #define CONFIG_ARCH_CPU_INIT #define CONFIG_TMU_TIMER #define CONFIG_SYS_TIMER_COUNTS_DOWN diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 841f361648..8aa6e1d0c3 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -29,8 +29,6 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -#define CONFIG_PREBOOT - #define CONFIG_S5P_PA_SYSRAM 0x02020000 #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index cc289244ff..b8437052a9 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -157,10 +157,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * Save the prior stage provided DTB. */ -#define CONFIG_PREBOOT \ - "fdt addr ${fdtcontroladdr};" \ - "fdt move ${fdtcontroladdr} ${fdtsaveaddr};" \ - "fdt addr ${fdtsaveaddr};" /* * Enable in-place RFS with this initrd_high setting. */ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 05ebb7d9c5..285e28b535 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -37,7 +37,6 @@ "run manage_userdata; " /* Enable PREBOOT variable */ -#define CONFIG_PREBOOT /* Set ARP_TIMEOUT to 500ms */ #define CONFIG_ARP_TIMEOUT 500UL diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h index 0f293849ab..dff41239ba 100644 --- a/include/configs/bur_cfg_common.h +++ b/include/configs/bur_cfg_common.h @@ -23,8 +23,6 @@ "setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ "setenv stdout nc;setenv stdin nc;setenv stderr nc\0" -#define CONFIG_PREBOOT "run cfgscr; run brdefaultip" - /* Network defines */ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 2e8dda8ab8..60bac9adc8 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -144,8 +144,6 @@ "echo WARNING: Could not determine dtb to use; fi; \0" \ BOOTENV -#define CONFIG_PREBOOT "usb start;sf probe" - #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 2) \ diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index 94aa2736ab..93dcad4b66 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -37,6 +37,4 @@ "upd_uboot=tftp 100000 conga/u-boot.rom;" \ "sf probe;sf update 100000 0 800000;saveenv\0" -#define CONFIG_PREBOOT - #endif /* __CONFIG_H */ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 3affdb0f68..54bbfe3f55 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -124,8 +124,6 @@ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "ccdc.img" -#define CONFIG_PREBOOT /* enable preboot variable */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth1\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index f7bad8e1e9..a8e1850f2b 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -42,6 +42,4 @@ "upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \ "sf probe;sf update 100000 0 800000;saveenv\0" -#define CONFIG_PREBOOT - #endif /* __CONFIG_H */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 7269c42a5f..b175e9d574 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -99,7 +99,5 @@ /* Default Environment */ #define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm" #define CONFIG_LOADADDR 0x80000 -#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */ -#define CONFIG_PREBOOT "usb start; sf probe" #endif /* _CONFIG_SYNOLOGY_DS414_H */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 11d367a151..0ff48287ac 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -100,8 +100,6 @@ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_PREBOOT /* enable preboot variable */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 02ceb4c8fc..a27627e721 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -138,7 +138,6 @@ /* Miscellaneous configurable options */ #define CONFIG_HWCONFIG -#define CONFIG_PREBOOT /* Memory configuration */ #define CONFIG_SYS_MEMTEST_START 0x10000000 diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 6e6c1714ce..8fb321178f 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -403,8 +403,6 @@ void fpga_control_clear(unsigned int bus, int pin); #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_PREBOOT /* enable preboot variable */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index b1d01c58f9..43cb14c14e 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -253,9 +253,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 #define CONFIG_LOADS_ECHO #define CONFIG_TIMESTAMP -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run nfsboot\\\" " \ - "to mount root filesystem over NFS;echo" #define CONFIG_BOOTCOMMAND "run boot_cramfs" #undef CONFIG_SYS_LOADS_BAUD_CHANGE diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 071d9289ef..a2c8224da7 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -18,8 +18,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#undef CONFIG_SHOW_BOOT_PROGRESS - /* MEMORY */ #define KZM_SDRAM_BASE (0x40000000) #define PHYS_SDRAM KZM_SDRAM_BASE diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 55c4e63325..3ba5548f25 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -29,7 +29,6 @@ #define CONFIG_KW88F6281 /* SOC Name */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_KIRKWOOD_GPIO diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index e98dbfbb7e..a432259cfe 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -185,7 +185,6 @@ /* * Extra Environments */ -#define CONFIG_PREBOOT "run try_bootscript" #define CONFIG_HOSTNAME "m53menlo" #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index a1fd5f6195..aeab2e983b 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -40,8 +40,6 @@ #define CONFIG_REVISION_TAG #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_PREBOOT /* enable preboot variable */ - /* * Hardware drivers */ diff --git a/include/configs/meson64.h b/include/configs/meson64.h index d82a674270..78b1615d5c 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -31,7 +31,6 @@ #ifdef CONFIG_USB_KEYBOARD #define STDIN_CFG "usbkbd,serial" -#define CONFIG_PREBOOT "usb start" #else #define STDIN_CFG "serial" #endif diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index d1ab40ec13..814fec5b33 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -140,8 +140,6 @@ /* architecture dependent code */ #define CONFIG_SYS_USR_EXCEP /* user exception */ -#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" - #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ "nor0=flash-0\0"\ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index a803093163..e6d5c680d7 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -38,7 +38,6 @@ #endif /* auto boot */ -#define CONFIG_PREBOOT /* * For booting Linux, the board info and command line data diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 10b94f438f..ff8cc3c770 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -14,7 +14,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* auto boot */ -#define CONFIG_PREBOOT #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index b28f3b9408..f3f8538541 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* auto boot */ -#define CONFIG_PREBOOT #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index f5fd01de22..fc498b2481 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -66,7 +66,6 @@ #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED /* Framebuffer and LCD */ -#define CONFIG_PREBOOT #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index ab61a07f96..bbe0574033 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -160,6 +160,5 @@ /* Framebuffer and LCD */ #define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_PREBOOT #endif /* __CONFIG_H */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 4f179081a8..b734b822dd 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -176,7 +176,6 @@ #endif /* Framebuffer and LCD */ -#define CONFIG_PREBOOT #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 7b4ae2102e..3cf2f1ce28 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -49,17 +49,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_PREBOOT \ - "if hdmidet; then " \ - "usb start; " \ - "setenv stdin serial,usbkbd; "\ - "setenv stdout serial,vga; " \ - "setenv stderr serial,vga; " \ - "else " \ - "setenv stdin serial; " \ - "setenv stdout serial; " \ - "setenv stderr serial; " \ - "fi;" /* Command definition */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index afaa908406..23c370b07c 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -67,8 +67,6 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_PREBOOT "" - #ifdef CONFIG_CMD_MMC #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) #else diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index d9f4bdc1d6..fd755bbcea 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -253,30 +253,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); "bootmenu_delay=30\0" \ "" -#define CONFIG_PREBOOT \ - "setenv mmcnum 1; setenv mmcpart 1;" \ - "setenv mmcscriptfile bootmenu.scr;" \ - "if run switchmmc; then " \ - "setenv mmcdone true;" \ - "setenv mmctype fat;" \ - "if run scriptload; then true; else " \ - "setenv mmctype ext2;" \ - "if run scriptload; then true; else " \ - "setenv mmctype ext4;" \ - "if run scriptload; then true; else " \ - "setenv mmcdone false;" \ - "fi;" \ - "fi;" \ - "fi;" \ - "if ${mmcdone}; then " \ - "run scriptboot;" \ - "fi;" \ - "fi;" \ - "if run slide; then true; else " \ - "setenv bootmenu_delay 0;" \ - "setenv bootdelay 0;" \ - "fi" - #define CONFIG_POSTBOOTMENU \ "echo;" \ "echo Extra commands:;" \ @@ -294,8 +270,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); "run attachboot;" \ "echo" -#define CONFIG_MENU_SHOW - /* * Miscellaneous configurable options */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index a2a6be7cf8..e8c60838b7 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -58,8 +58,6 @@ /* TWL4030 LED Support */ -#define CONFIG_PREBOOT "usb start" - #define MEM_LAYOUT_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 1fbd371a50..b7c3ddf564 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -60,10 +60,6 @@ /* Environment information */ -#define CONFIG_PREBOOT \ - "setenv preboot;" \ - "saveenv;" - #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index e0c76ff43d..309b4717c4 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -76,7 +76,6 @@ #define ACFG_CONSOLE_DEV ttymxc0 #define CONFIG_SYS_AUTOLOAD "no" #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" -#define CONFIG_PREBOOT "run check_env" #define CONFIG_BOOTCOMMAND "run emmcboot" #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 925e7ae3db..7dfcccb82b 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -77,8 +77,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #endif -#define CONFIG_PREBOOT "" - /* Thermal support */ #define CONFIG_IMX_THERMAL diff --git a/include/configs/platinum.h b/include/configs/platinum.h index d1ebaf5561..1b57e9931f 100644 --- a/include/configs/platinum.h +++ b/include/configs/platinum.h @@ -102,7 +102,6 @@ #define CONFIG_BOOTCOMMAND "run bootubi_scr" /* Miscellaneous configurable options */ -#define CONFIG_PREBOOT /* MTD/UBI/UBIFS config */ diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 35e3c5ad7a..c7aaafaad4 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -32,7 +32,6 @@ #include <config_distro_bootcmd.h> -#define CONFIG_PREBOOT "pci enum" #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index df22f780b0..ecea1d4765 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -48,8 +48,4 @@ "ramdisk_addr_r=0x88300000\0" \ BOOTENV -#define CONFIG_PREBOOT \ - "setenv fdt_addr ${fdtcontroladdr};" \ - "fdt addr ${fdtcontroladdr};" - #endif /* __CONFIG_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 7f72ff2e11..146a30b4c2 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -18,8 +18,6 @@ #define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" #endif -#undef CONFIG_SHOW_BOOT_PROGRESS - #define CONFIG_ARCH_CPU_INIT #ifndef CONFIG_PINCTRL_PFC diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 203b0a78f2..11bf16b054 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -23,8 +23,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -#undef CONFIG_SHOW_BOOT_PROGRESS - #define CONFIG_ARCH_CPU_INIT /* Generic Interrupt Controller Definitions */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 73be079b20..ec0e157ec5 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -56,6 +56,4 @@ BOOTENV #endif -#define CONFIG_PREBOOT - #endif diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 92524b06ad..44e8d0ccd2 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -61,6 +61,4 @@ #endif /* CONFIG_SPL_BUILD */ -#define CONFIG_PREBOOT - #endif diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 9582cdfb64..42a49c5502 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -56,6 +56,4 @@ BOOTENV #endif -#define CONFIG_PREBOOT - #endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index da10e29139..eaa1c582e9 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -70,6 +70,4 @@ BOOTENV #endif -#define CONFIG_PREBOOT - #endif diff --git a/include/configs/rpi.h b/include/configs/rpi.h index f76c7d18ef..e706bea8cc 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -73,7 +73,6 @@ /* Environment */ #define CONFIG_ENV_SIZE SZ_16K #define CONFIG_SYS_LOAD_ADDR 0x1000000 -#define CONFIG_PREBOOT "usb start" /* Shell */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index ba613672eb..6aa40caa7c 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -48,8 +48,6 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #endif -#ifdef CONFIG_PCIE1 -#endif #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index c90d8e0e9a..cd7f51c7ce 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -11,7 +11,6 @@ #define CONFIG_CPU_SH7752 1 #define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SHOW_BOOT_PROGRESS /* MEMORY */ #define SH7752EVB_SDRAM_BASE (0x40000000) diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index 83d123f33a..6b00bd7d90 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -11,7 +11,6 @@ #define CONFIG_CPU_SH7753 1 #define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SHOW_BOOT_PROGRESS /* MEMORY */ #define SH7753EVB_SDRAM_BASE (0x40000000) diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index f92f066494..f1955a16b9 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -12,7 +12,6 @@ #define CONFIG_SH7757LCR_DDR_ECC 1 #define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SHOW_BOOT_PROGRESS /* MEMORY */ #define SH7757LCR_SDRAM_BASE (0x80000000) diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index d857fcbd9a..10961b14ba 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -15,7 +15,6 @@ #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SHOW_BOOT_PROGRESS /* SCIF */ #define CONFIG_CONS_SCIF2 1 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index c07814f91b..dd63adb6db 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -189,7 +189,6 @@ /* UBI Support */ /* Commen environment */ -#define CONFIG_PREBOOT #define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ "setenv bootargs ${bootargs};" \ "mtdparts default;" \ diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h index fc1db2442e..befaeaaf54 100644 --- a/include/configs/socfpga_dbm_soc1.h +++ b/include/configs/socfpga_dbm_soc1.h @@ -12,7 +12,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "fitImage" -#define CONFIG_PREBOOT "run try_bootscript" #define CONFIG_BOOTCOMMAND "run mmc_mmc" #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index a2fc1033b3..590a9af274 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -12,7 +12,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "fitImage" -#define CONFIG_PREBOOT "run try_bootscript" #define CONFIG_BOOTCOMMAND "run mmc_mmc" #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 5416c4b170..232536a763 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -33,16 +33,6 @@ * if button B is not pressed, boot normal Linux system immediatelly * if button B is pressed, wait $bootdelay and boot recovery system */ -#define CONFIG_PREBOOT \ - "setenv hostname vining-${unit_serial} ; " \ - "setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; " \ - "if gpio input 78 ; then " \ - "setenv bootdelay 10 ; " \ - "setenv boottype rcvr ; " \ - "else " \ - "setenv bootdelay 5 ; " \ - "setenv boottype norm ; " \ - "fi" #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 7d266d1bcd..c7c30d367a 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -272,11 +272,6 @@ #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome on the ABB Socrates Board;" \ - "echo" - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consdev=ttyS0\0" \ diff --git a/include/configs/strider.h b/include/configs/strider.h index 8b942e3446..e3d64e52aa 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -436,8 +436,6 @@ void fpga_control_clear(unsigned int bus, int pin); #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_PREBOOT /* enable preboot variable */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 7be94ee7d1..d7133a73fc 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -285,10 +285,6 @@ extern int soft_i2c_gpio_scl; #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 #endif -#ifdef CONFIG_USB_KEYBOARD -#define CONFIG_PREBOOT -#endif - #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_ARM64 diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index a753d41835..11f76e777b 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -79,15 +79,6 @@ #ifdef CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USBD_HS #endif /* CONFIG_CMD_USB_MASS_STORAGE */ -#ifdef CONFIG_USB_KEYBOARD -#define CONFIG_PREBOOT \ - "usb start; " \ - "if hdmidet; then " \ - "run set_con_hdmi; " \ - "else " \ - "run set_con_serial; " \ - "fi" -#endif /* CONFIG_USB_KEYBOARD */ #endif /* CONFIG_CMD_USB */ /* Environment organization */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 9685ee5059..fae0e761fb 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -42,7 +42,6 @@ #ifdef CONFIG_USB_KEYBOARD #define STDIN_KBD_USB ",usbkbd" -#define CONFIG_PREBOOT "usb start" #else #define STDIN_KBD_USB "" #endif diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index e0a033bec1..0c563e714d 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) -#define CONFIG_PREBOOT - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 6d41d18493..3562a14261 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -47,8 +47,6 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -#define CONFIG_PREBOOT - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 69aa79bafc..a915c32607 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -79,8 +79,6 @@ # define EXTRA_ENV_USB #endif -#undef CONFIG_PREBOOT - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "kernel_image=uImage\0" \ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 0de40eddcb..7d5f5fa409 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* auto boot */ -#define CONFIG_PREBOOT #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 2354f4e958..89cd8b550a 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -110,8 +110,6 @@ #define CONFIG_PL011_CLOCK 24000000 #endif -/*#define CONFIG_MENU_SHOW*/ - /* BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 7fcf76a6bf..c4deef80af 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -14,7 +14,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_PHYSMEM #define CONFIG_LMB diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 684faaee2e..bbcb20737b 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -62,7 +62,6 @@ #if defined(CONFIG_ZYNQMP_USB) #define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_USB_CABLE_CHECK #define CONFIG_THOR_RESET_OFF #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 1ef803b020..23f0389615 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -472,7 +472,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ /* diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 5737cfee95..21e91ee1a4 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -271,7 +271,6 @@ */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 0a87f226f8..73e1fa313f 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -322,7 +322,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ /* diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 0389874609..e5a41abd4b 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -320,7 +320,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ /* diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 33255a3fe9..b8de931d2c 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -120,7 +120,6 @@ /*==============================*/ #define CONFIG_MX_CYCLIC -#define CONFIG_SHOW_BOOT_PROGRESS /*=========================================*/ diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index c8b6161a29..9d683768f4 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -98,8 +98,6 @@ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) -#define CONFIG_PREBOOT "" - /* * Size of malloc() pool diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b51914d1e0..bb6a835ece 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -65,7 +65,6 @@ # define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 # define DFU_DEFAULT_POLL_TIMEOUT 300 -# define CONFIG_USB_CABLE_CHECK # define CONFIG_THOR_RESET_OFF # define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ @@ -103,7 +102,6 @@ #define CONFIG_ENV_OVERWRITE /* enable preboot to be loaded before CONFIG_BOOTDELAY */ -#define CONFIG_PREBOOT /* Boot configuration */ #define CONFIG_SYS_LOAD_ADDR 0 /* default? */ diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h index 61955016a5..8ec4a269c7 100644 --- a/include/dt-bindings/clock/axg-aoclkc.h +++ b/include/dt-bindings/clock/axg-aoclkc.h @@ -21,6 +21,11 @@ #define CLKID_AO_SAR_ADC_SEL 8 #define CLKID_AO_SAR_ADC_DIV 9 #define CLKID_AO_SAR_ADC_CLK 10 -#define CLKID_AO_ALT_XTAL 11 +#define CLKID_AO_CTS_OSCIN 11 +#define CLKID_AO_32K_PRE 12 +#define CLKID_AO_32K_DIV 13 +#define CLKID_AO_32K_SEL 14 +#define CLKID_AO_32K 15 +#define CLKID_AO_CTS_RTC_OSCIN 16 #endif diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h index fd9c362099..75901c6368 100644 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -7,26 +7,6 @@ #ifndef __AXG_AUDIO_CLKC_BINDINGS_H #define __AXG_AUDIO_CLKC_BINDINGS_H -#define AUD_CLKID_SLV_SCLK0 9 -#define AUD_CLKID_SLV_SCLK1 10 -#define AUD_CLKID_SLV_SCLK2 11 -#define AUD_CLKID_SLV_SCLK3 12 -#define AUD_CLKID_SLV_SCLK4 13 -#define AUD_CLKID_SLV_SCLK5 14 -#define AUD_CLKID_SLV_SCLK6 15 -#define AUD_CLKID_SLV_SCLK7 16 -#define AUD_CLKID_SLV_SCLK8 17 -#define AUD_CLKID_SLV_SCLK9 18 -#define AUD_CLKID_SLV_LRCLK0 19 -#define AUD_CLKID_SLV_LRCLK1 20 -#define AUD_CLKID_SLV_LRCLK2 21 -#define AUD_CLKID_SLV_LRCLK3 22 -#define AUD_CLKID_SLV_LRCLK4 23 -#define AUD_CLKID_SLV_LRCLK5 24 -#define AUD_CLKID_SLV_LRCLK6 25 -#define AUD_CLKID_SLV_LRCLK7 26 -#define AUD_CLKID_SLV_LRCLK8 27 -#define AUD_CLKID_SLV_LRCLK9 28 #define AUD_CLKID_DDR_ARB 29 #define AUD_CLKID_PDM 30 #define AUD_CLKID_TDMIN_A 31 @@ -90,5 +70,15 @@ #define AUD_CLKID_TDMOUT_A_LRCLK 134 #define AUD_CLKID_TDMOUT_B_LRCLK 135 #define AUD_CLKID_TDMOUT_C_LRCLK 136 +#define AUD_CLKID_SPDIFOUT_B 151 +#define AUD_CLKID_SPDIFOUT_B_CLK 152 +#define AUD_CLKID_TDM_MCLK_PAD0 155 +#define AUD_CLKID_TDM_MCLK_PAD1 156 +#define AUD_CLKID_TDM_LRCLK_PAD0 157 +#define AUD_CLKID_TDM_LRCLK_PAD1 158 +#define AUD_CLKID_TDM_LRCLK_PAD2 159 +#define AUD_CLKID_TDM_SCLK_PAD0 160 +#define AUD_CLKID_TDM_SCLK_PAD1 161 +#define AUD_CLKID_TDM_SCLK_PAD2 162 #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 82c9e0c020..b6b127e456 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -130,11 +130,12 @@ #define CLKID_MALI_1_SEL 172 #define CLKID_MALI_1 174 #define CLKID_MALI 175 -#define CLKID_MPLL_5OM 177 +#define CLKID_MPLL_50M 177 #define CLKID_CPU_CLK 187 #define CLKID_PCIE_PLL 201 #define CLKID_VDEC_1 204 #define CLKID_VDEC_HEVC 207 #define CLKID_VDEC_HEVCF 210 +#define CLKID_TS 212 #endif /* __G12A_CLKC_H */ diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h index 05a4b59173..de82d8a15e 100644 --- a/include/dt-bindings/power/r8a77965-sysc.h +++ b/include/dt-bindings/power/r8a77965-sysc.h @@ -21,7 +21,6 @@ #define R8A77965_PD_A3VC 14 #define R8A77965_PD_3DG_A 17 #define R8A77965_PD_3DG_B 18 -#define R8A77965_PD_A3IR 24 #define R8A77965_PD_A2VC1 26 /* Always-on power area */ diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h index bf54779d16..85cc5f23cf 100644 --- a/include/dt-bindings/power/r8a77970-sysc.h +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -16,13 +16,12 @@ #define R8A77970_PD_CA53_CPU0 5 #define R8A77970_PD_CA53_CPU1 6 -#define R8A77970_PD_CR7 13 #define R8A77970_PD_CA53_SCU 21 #define R8A77970_PD_A2IR0 23 -#define R8A77970_PD_A3IR 24 +#define R8A77970_PD_A3IR 24 #define R8A77970_PD_A2IR1 27 -#define R8A77970_PD_A2IR2 28 -#define R8A77970_PD_A2IR3 29 +#define R8A77970_PD_A2DP 28 +#define R8A77970_PD_A2CN 29 #define R8A77970_PD_A2SC0 30 #define R8A77970_PD_A2SC1 31 diff --git a/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/include/dt-bindings/sound/meson-g12a-tohdmitx.h new file mode 100644 index 0000000000..c5e1f48d30 --- /dev/null +++ b/include/dt-bindings/sound/meson-g12a-tohdmitx.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_MESON_G12A_TOHDMITX_H +#define __DT_MESON_G12A_TOHDMITX_H + +#define TOHDMITX_I2S_IN_A 0 +#define TOHDMITX_I2S_IN_B 1 +#define TOHDMITX_I2S_IN_C 2 +#define TOHDMITX_I2S_OUT 3 +#define TOHDMITX_SPDIF_IN_A 4 +#define TOHDMITX_SPDIF_IN_B 5 +#define TOHDMITX_SPDIF_OUT 6 + +#endif /* __DT_MESON_G12A_TOHDMITX_H */ diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h index e55a4aec57..684a744f31 100644 --- a/include/environment/ti/boot.h +++ b/include/environment/ti/boot.h @@ -98,6 +98,10 @@ #define AB_SELECT "" #endif +#define FASTBOOT_CMD \ + "echo Booting into fastboot ...; " \ + "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " + #define DEFAULT_COMMON_BOOT_TI_ARGS \ "console=" CONSOLEDEV ",115200n8\0" \ "fdtfile=undefined\0" \ @@ -117,6 +121,28 @@ "setenv mmcroot /dev/mmcblk0p2 rw; " \ "run mmcboot;\0" \ "emmc_android_boot=" \ + "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \ + CONTROL_PARTITION "; then " \ + "if bcb test command = bootonce-bootloader; then " \ + "echo BCB: Bootloader boot...; " \ + "bcb clear command; bcb store; " \ + FASTBOOT_CMD \ + "elif bcb test command = boot-recovery; then " \ + "echo BCB: Recovery boot...; " \ + "echo Warning: recovery is not implemented; " \ + "echo Performing normal boot for now...; " \ + "bcb clear command; bcb store; " \ + "run emmc_android_normal_boot; " \ + "else " \ + "echo BCB: Normal boot requested...; " \ + "run emmc_android_normal_boot; " \ + "fi; " \ + "else " \ + "echo Warning: BCB is corrupted or does not exist; " \ + "echo Performing normal boot...; " \ + "run emmc_android_normal_boot; " \ + "fi;\0" \ + "emmc_android_normal_boot=" \ "echo Trying to boot Android from eMMC ...; " \ "run update_to_fit; " \ "setenv eval_bootargs setenv bootargs $bootargs; " \ @@ -176,8 +202,7 @@ "if test ${dofastboot} -eq 1; then " \ "echo Boot fastboot requested, resetting dofastboot ...;" \ "setenv dofastboot 0; saveenv;" \ - "echo Booting into fastboot ...; " \ - "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \ + FASTBOOT_CMD \ "fi;" \ "if test ${boot_fit} -eq 1; then " \ "run update_to_fit;" \ diff --git a/include/fpga.h b/include/fpga.h index 51de5c55f8..ec5144334d 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -15,7 +15,7 @@ /* fpga_xxxx function return value definitions */ #define FPGA_SUCCESS 0 -#define FPGA_FAIL -1 +#define FPGA_FAIL 1 /* device numbers must be non-negative */ #define FPGA_INVALID_DEVICE -1 diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 43a25e9c6a..02ff1a311a 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -8,6 +8,7 @@ */ #ifndef __LINUX_CLK_PROVIDER_H #define __LINUX_CLK_PROVIDER_H +#include <clk-uclass.h> static inline void clk_dm(ulong id, struct clk *clk) { @@ -66,6 +67,29 @@ struct clk_mux { }; #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk) +extern const struct clk_ops clk_mux_ops; +u8 clk_mux_get_parent(struct clk *clk); + +struct clk_gate { + struct clk clk; + void __iomem *reg; + u8 bit_idx; + u8 flags; +#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) + u32 io_gate_val; +#endif +}; + +#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk) + +#define CLK_GATE_SET_TO_DISABLE BIT(0) +#define CLK_GATE_HIWORD_MASK BIT(1) + +extern const struct clk_ops clk_gate_ops; +struct clk *clk_register_gate(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); struct clk_div_table { unsigned int val; @@ -94,6 +118,11 @@ struct clk_divider { #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +extern const struct clk_ops clk_divider_ops; +unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate, + unsigned int val, + const struct clk_div_table *table, + unsigned long flags, unsigned long width); struct clk_fixed_factor { struct clk clk; @@ -104,6 +133,35 @@ struct clk_fixed_factor { #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\ clk) +struct clk_fixed_rate { + struct clk clk; + unsigned long fixed_rate; +}; + +#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev)) + +struct clk_composite { + struct clk clk; + struct clk_ops ops; + + struct clk *mux; + struct clk *rate; + struct clk *gate; + + const struct clk_ops *mux_ops; + const struct clk_ops *rate_ops; + const struct clk_ops *gate_ops; +}; + +#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk) + +struct clk *clk_register_composite(struct device *dev, const char *name, + const char * const *parent_names, int num_parents, + struct clk *mux_clk, const struct clk_ops *mux_ops, + struct clk *rate_clk, const struct clk_ops *rate_ops, + struct clk *gate_clk, const struct clk_ops *gate_ops, + unsigned long flags); + int clk_register(struct clk *clk, const char *drv_name, const char *name, const char *parent_name); diff --git a/include/menu.h b/include/menu.h index fbff429c89..2d227c20bd 100644 --- a/include/menu.h +++ b/include/menu.h @@ -19,7 +19,20 @@ int menu_destroy(struct menu *m); void menu_display_statusline(struct menu *m); int menu_default_choice(struct menu *m, void **choice); -#if defined(CONFIG_MENU_SHOW) +/** + * menu_show() Show a boot menu + * + * This shows a menu and lets the user select an option. The menu is defined by + * environment variables (see README.bootmenu). + * + * This function doesn't normally return, but if the users requests the command + * problem, it will. + * + * @bootdelay: Delay to wait before running the default menu option (0 to run + * the entry immediately) + * @return If it returns, it always returns -1 to indicate that the boot should + * be aborted and the command prompt should be provided + */ int menu_show(int bootdelay); -#endif + #endif /* __MENU_H__ */ diff --git a/include/sandbox-clk.h b/include/sandbox-clk.h index 37c9838f76..f449de1364 100644 --- a/include/sandbox-clk.h +++ b/include/sandbox-clk.h @@ -19,6 +19,7 @@ enum { SANDBOX_CLK_ECSPI1, SANDBOX_CLK_USDHC1_SEL, SANDBOX_CLK_USDHC2_SEL, + SANDBOX_CLK_I2C, }; enum sandbox_pllv3_type { diff --git a/include/virtex2.h b/include/virtex2.h index a48113060e..7e8d93f24d 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,7 +11,7 @@ #include <xilinx.h> /* - * Slave SelectMap Implementation function table. + * Slave SelectMap or Serial Implementation function table. */ typedef struct { xilinx_pre_fn pre; @@ -24,18 +24,11 @@ typedef struct { xilinx_wr_fn wr; xilinx_rdata_fn rdata; xilinx_wdata_fn wdata; + xilinx_bwr_fn wbulkdata; xilinx_busy_fn busy; xilinx_abort_fn abort; xilinx_post_fn post; -} xilinx_virtex2_slave_selectmap_fns; - -/* Slave Serial Implementation function table */ -typedef struct { - xilinx_pgm_fn pgm; - xilinx_clk_fn clk; - xilinx_rdata_fn rdata; - xilinx_wdata_fn wdata; -} xilinx_virtex2_slave_serial_fns; +} xilinx_virtex2_slave_fns; #if defined(CONFIG_FPGA_VIRTEX2) extern struct xilinx_fpga_op virtex2_op; diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index bcb24d1bc3..53db749a65 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -96,6 +96,7 @@ CONFIG_ATMEL_LEGACY CONFIG_ATMEL_MCI_8BIT CONFIG_ATMEL_SPI0 CONFIG_AT_TRANS +CONFIG_AUTOBOOT_MENU_SHOW CONFIG_AUTO_ZRELADDR CONFIG_BACKSIDE_L2_CACHE CONFIG_BAT_PAIR @@ -280,7 +281,6 @@ CONFIG_CTL_JTAG CONFIG_CTL_TBE CONFIG_CUSTOMER_BOARD_SUPPORT CONFIG_D2NET_V2 -CONFIG_DA850_AM18X_EVM CONFIG_DA850_EVM_MAX_CPU_CLK CONFIG_DBGU CONFIG_DB_784MP_GP @@ -1141,9 +1141,6 @@ CONFIG_MEMSIZE_MASK CONFIG_MEM_HOLE_16M CONFIG_MEM_INIT_VALUE CONFIG_MEM_REMAP -CONFIG_MENUKEY -CONFIG_MENUPROMPT -CONFIG_MENU_SHOW CONFIG_MFG_ENV_SETTINGS CONFIG_MIIM_ADDRESS CONFIG_MII_DEFAULT_TSEC @@ -1621,7 +1618,6 @@ CONFIG_SHARP_LQ035Q7DH06 CONFIG_SHEEVA_88SV131 CONFIG_SHEEVA_88SV331xV5 CONFIG_SHOW_ACTIVITY -CONFIG_SHOW_BOOT_PROGRESS CONFIG_SH_CMT_CLK_FREQ CONFIG_SH_DSP CONFIG_SH_ETHER_ALIGNE_SIZE @@ -4293,7 +4289,6 @@ CONFIG_USB_ATMEL_CLK_SEL_PLLB CONFIG_USB_ATMEL_CLK_SEL_UPLL CONFIG_USB_BIN_FIXUP CONFIG_USB_BOOTING -CONFIG_USB_CABLE_CHECK CONFIG_USB_DEVICE CONFIG_USB_DEV_BASE CONFIG_USB_DEV_PULLUP_GPIO diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index 8d397593a3..bbc4b500e8 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -56,6 +56,14 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) pclk = clk_get_parent(clk); ut_asserteq_str("pll3_80m", pclk->dev->name); + /* Test the composite of CCF */ + ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk); + ut_assertok(ret); + ut_asserteq_str("i2c", clk->dev->name); + + rate = clk_get_rate(clk); + ut_asserteq(rate, 60000000); + return 1; } diff --git a/test/py/tests/test_mmc_wr.py b/test/py/tests/test_mmc_wr.py new file mode 100644 index 0000000000..601279a6a4 --- /dev/null +++ b/test/py/tests/test_mmc_wr.py @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2019, Texas Instrument +# Author: Jean-Jacques Hiblot <jjhiblot@ti.com> + +# Test U-Boot's "mmc write" command. The test generates random data, writes it +# to the eMMC or SD card, then reads it back and performs a comparison. + +import pytest +import u_boot_utils + +""" +This test relies on boardenv_* to containing configuration values to define +which MMC devices should be tested. For example: + +env__mmc_wr_configs = ( + { + "fixture_id": "emmc-boot0", + "is_emmc": True, + "devid": 1, + "partid": 1, + "sector": 0x10, + "count": 100, + "test_iterations": 50, + }, + { + "fixture_id": "emmc-boot1", + "is_emmc": True, + "devid": 1, + "partid": 2, + "sector": 0x10, + "count": 100, + "test_iterations": 50, + }, +) + +""" + +@pytest.mark.buildconfigspec('cmd_mmc','cmd_memory') +def test_mmc_wr(u_boot_console, env__mmc_wr_config): + """Test the "mmc write" command. + + Args: + u_boot_console: A U-Boot console connection. + env__mmc_wr_config: The single MMC configuration on which + to run the test. See the file-level comment above for details + of the format. + + Returns: + Nothing. + """ + + is_emmc = env__mmc_wr_config['is_emmc'] + devid = env__mmc_wr_config['devid'] + partid = env__mmc_wr_config.get('partid', 0) + sector = env__mmc_wr_config.get('sector', 0) + count_sectors = env__mmc_wr_config.get('count', 1) + test_iterations = env__mmc_wr_config.get('test_iterations', 1) + + + count_bytes = count_sectors * 512 + bcfg = u_boot_console.config.buildconfig + ram_base = u_boot_utils.find_ram_base(u_boot_console) + src_addr = '0x%08x' % ram_base + dst_addr = '0x%08x' % (ram_base + count_bytes) + + + for i in range(test_iterations): + # Generate random data + cmd = 'random %s %x' % (src_addr, count_bytes) + response = u_boot_console.run_command(cmd) + good_response = '%d bytes filled with random data' % (count_bytes) + assert good_response in response + + # Select MMC device + cmd = 'mmc dev %d' % devid + if is_emmc: + cmd += ' %d' % partid + response = u_boot_console.run_command(cmd) + assert 'no card present' not in response + if is_emmc: + partid_response = "(part %d)" % partid + else: + partid_response = "" + good_response = 'mmc%d%s is current device' % (devid, partid_response) + assert good_response in response + + # Write data + cmd = 'mmc write %s %x %x' % (src_addr, sector, count_sectors) + response = u_boot_console.run_command(cmd) + good_response = 'MMC write: dev # %d, block # %d, count %d ... %d blocks written: OK' % ( + devid, sector, count_sectors, count_sectors) + assert good_response in response + + # Read data + cmd = 'mmc read %s %x %x' % (dst_addr, sector, count_sectors) + response = u_boot_console.run_command(cmd) + good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % ( + devid, sector, count_sectors, count_sectors) + assert good_response in response + + # Compare src and dst data + cmd = 'cmp.b %s %s %x' % (src_addr, dst_addr, count_bytes) + response = u_boot_console.run_command(cmd) + good_response = 'Total of %d byte(s) were the same' % (count_bytes) + assert good_response in response diff --git a/tools/zynqmp_pm_cfg_obj_convert.py b/tools/zynqmp_pm_cfg_obj_convert.py new file mode 100755 index 0000000000..dd27f47921 --- /dev/null +++ b/tools/zynqmp_pm_cfg_obj_convert.py @@ -0,0 +1,301 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net> + +import sys +import re +import struct +import logging +import argparse + +parser = argparse.ArgumentParser( + description='Convert a PMU configuration object from C source to a binary blob.') +parser.add_argument('-D', '--debug', action="store_true") +parser.add_argument( + "in_file", metavar='INPUT_FILE', + help='PMU configuration object (C source as produced by Xilinx XSDK)') +parser.add_argument( + "out_file", metavar='OUTPUT_FILE', + help='PMU configuration object binary blob') +args = parser.parse_args() + +logging.basicConfig(format='%(levelname)s:%(message)s', + level=(logging.DEBUG if args.debug else logging.WARNING)) + +pm_define = { + 'PM_CAP_ACCESS' : 0x1, + 'PM_CAP_CONTEXT' : 0x2, + 'PM_CAP_WAKEUP' : 0x4, + + 'NODE_UNKNOWN' : 0, + 'NODE_APU' : 1, + 'NODE_APU_0' : 2, + 'NODE_APU_1' : 3, + 'NODE_APU_2' : 4, + 'NODE_APU_3' : 5, + 'NODE_RPU' : 6, + 'NODE_RPU_0' : 7, + 'NODE_RPU_1' : 8, + 'NODE_PLD' : 9, + 'NODE_FPD' : 10, + 'NODE_OCM_BANK_0' : 11, + 'NODE_OCM_BANK_1' : 12, + 'NODE_OCM_BANK_2' : 13, + 'NODE_OCM_BANK_3' : 14, + 'NODE_TCM_0_A' : 15, + 'NODE_TCM_0_B' : 16, + 'NODE_TCM_1_A' : 17, + 'NODE_TCM_1_B' : 18, + 'NODE_L2' : 19, + 'NODE_GPU_PP_0' : 20, + 'NODE_GPU_PP_1' : 21, + 'NODE_USB_0' : 22, + 'NODE_USB_1' : 23, + 'NODE_TTC_0' : 24, + 'NODE_TTC_1' : 25, + 'NODE_TTC_2' : 26, + 'NODE_TTC_3' : 27, + 'NODE_SATA' : 28, + 'NODE_ETH_0' : 29, + 'NODE_ETH_1' : 30, + 'NODE_ETH_2' : 31, + 'NODE_ETH_3' : 32, + 'NODE_UART_0' : 33, + 'NODE_UART_1' : 34, + 'NODE_SPI_0' : 35, + 'NODE_SPI_1' : 36, + 'NODE_I2C_0' : 37, + 'NODE_I2C_1' : 38, + 'NODE_SD_0' : 39, + 'NODE_SD_1' : 40, + 'NODE_DP' : 41, + 'NODE_GDMA' : 42, + 'NODE_ADMA' : 43, + 'NODE_NAND' : 44, + 'NODE_QSPI' : 45, + 'NODE_GPIO' : 46, + 'NODE_CAN_0' : 47, + 'NODE_CAN_1' : 48, + 'NODE_EXTERN' : 49, + 'NODE_APLL' : 50, + 'NODE_VPLL' : 51, + 'NODE_DPLL' : 52, + 'NODE_RPLL' : 53, + 'NODE_IOPLL' : 54, + 'NODE_DDR' : 55, + 'NODE_IPI_APU' : 56, + 'NODE_IPI_RPU_0' : 57, + 'NODE_GPU' : 58, + 'NODE_PCIE' : 59, + 'NODE_PCAP' : 60, + 'NODE_RTC' : 61, + 'NODE_LPD' : 62, + 'NODE_VCU' : 63, + 'NODE_IPI_RPU_1' : 64, + 'NODE_IPI_PL_0' : 65, + 'NODE_IPI_PL_1' : 66, + 'NODE_IPI_PL_2' : 67, + 'NODE_IPI_PL_3' : 68, + 'NODE_PL' : 69, + 'NODE_ID_MA' : 70, + + 'XILPM_RESET_PCIE_CFG' : 1000, + 'XILPM_RESET_PCIE_BRIDGE' : 1001, + 'XILPM_RESET_PCIE_CTRL' : 1002, + 'XILPM_RESET_DP' : 1003, + 'XILPM_RESET_SWDT_CRF' : 1004, + 'XILPM_RESET_AFI_FM5' : 1005, + 'XILPM_RESET_AFI_FM4' : 1006, + 'XILPM_RESET_AFI_FM3' : 1007, + 'XILPM_RESET_AFI_FM2' : 1008, + 'XILPM_RESET_AFI_FM1' : 1009, + 'XILPM_RESET_AFI_FM0' : 1010, + 'XILPM_RESET_GDMA' : 1011, + 'XILPM_RESET_GPU_PP1' : 1012, + 'XILPM_RESET_GPU_PP0' : 1013, + 'XILPM_RESET_GPU' : 1014, + 'XILPM_RESET_GT' : 1015, + 'XILPM_RESET_SATA' : 1016, + 'XILPM_RESET_ACPU3_PWRON' : 1017, + 'XILPM_RESET_ACPU2_PWRON' : 1018, + 'XILPM_RESET_ACPU1_PWRON' : 1019, + 'XILPM_RESET_ACPU0_PWRON' : 1020, + 'XILPM_RESET_APU_L2' : 1021, + 'XILPM_RESET_ACPU3' : 1022, + 'XILPM_RESET_ACPU2' : 1023, + 'XILPM_RESET_ACPU1' : 1024, + 'XILPM_RESET_ACPU0' : 1025, + 'XILPM_RESET_DDR' : 1026, + 'XILPM_RESET_APM_FPD' : 1027, + 'XILPM_RESET_SOFT' : 1028, + 'XILPM_RESET_GEM0' : 1029, + 'XILPM_RESET_GEM1' : 1030, + 'XILPM_RESET_GEM2' : 1031, + 'XILPM_RESET_GEM3' : 1032, + 'XILPM_RESET_QSPI' : 1033, + 'XILPM_RESET_UART0' : 1034, + 'XILPM_RESET_UART1' : 1035, + 'XILPM_RESET_SPI0' : 1036, + 'XILPM_RESET_SPI1' : 1037, + 'XILPM_RESET_SDIO0' : 1038, + 'XILPM_RESET_SDIO1' : 1039, + 'XILPM_RESET_CAN0' : 1040, + 'XILPM_RESET_CAN1' : 1041, + 'XILPM_RESET_I2C0' : 1042, + 'XILPM_RESET_I2C1' : 1043, + 'XILPM_RESET_TTC0' : 1044, + 'XILPM_RESET_TTC1' : 1045, + 'XILPM_RESET_TTC2' : 1046, + 'XILPM_RESET_TTC3' : 1047, + 'XILPM_RESET_SWDT_CRL' : 1048, + 'XILPM_RESET_NAND' : 1049, + 'XILPM_RESET_ADMA' : 1050, + 'XILPM_RESET_GPIO' : 1051, + 'XILPM_RESET_IOU_CC' : 1052, + 'XILPM_RESET_TIMESTAMP' : 1053, + 'XILPM_RESET_RPU_R50' : 1054, + 'XILPM_RESET_RPU_R51' : 1055, + 'XILPM_RESET_RPU_AMBA' : 1056, + 'XILPM_RESET_OCM' : 1057, + 'XILPM_RESET_RPU_PGE' : 1058, + 'XILPM_RESET_USB0_CORERESET' : 1059, + 'XILPM_RESET_USB1_CORERESET' : 1060, + 'XILPM_RESET_USB0_HIBERRESET' : 1061, + 'XILPM_RESET_USB1_HIBERRESET' : 1062, + 'XILPM_RESET_USB0_APB' : 1063, + 'XILPM_RESET_USB1_APB' : 1064, + 'XILPM_RESET_IPI' : 1065, + 'XILPM_RESET_APM_LPD' : 1066, + 'XILPM_RESET_RTC' : 1067, + 'XILPM_RESET_SYSMON' : 1068, + 'XILPM_RESET_AFI_FM6' : 1069, + 'XILPM_RESET_LPD_SWDT' : 1070, + 'XILPM_RESET_FPD' : 1071, + 'XILPM_RESET_RPU_DBG1' : 1072, + 'XILPM_RESET_RPU_DBG0' : 1073, + 'XILPM_RESET_DBG_LPD' : 1074, + 'XILPM_RESET_DBG_FPD' : 1075, + 'XILPM_RESET_APLL' : 1076, + 'XILPM_RESET_DPLL' : 1077, + 'XILPM_RESET_VPLL' : 1078, + 'XILPM_RESET_IOPLL' : 1079, + 'XILPM_RESET_RPLL' : 1080, + 'XILPM_RESET_GPO3_PL_0' : 1081, + 'XILPM_RESET_GPO3_PL_1' : 1082, + 'XILPM_RESET_GPO3_PL_2' : 1083, + 'XILPM_RESET_GPO3_PL_3' : 1084, + 'XILPM_RESET_GPO3_PL_4' : 1085, + 'XILPM_RESET_GPO3_PL_5' : 1086, + 'XILPM_RESET_GPO3_PL_6' : 1087, + 'XILPM_RESET_GPO3_PL_7' : 1088, + 'XILPM_RESET_GPO3_PL_8' : 1089, + 'XILPM_RESET_GPO3_PL_9' : 1090, + 'XILPM_RESET_GPO3_PL_10' : 1091, + 'XILPM_RESET_GPO3_PL_11' : 1092, + 'XILPM_RESET_GPO3_PL_12' : 1093, + 'XILPM_RESET_GPO3_PL_13' : 1094, + 'XILPM_RESET_GPO3_PL_14' : 1095, + 'XILPM_RESET_GPO3_PL_15' : 1096, + 'XILPM_RESET_GPO3_PL_16' : 1097, + 'XILPM_RESET_GPO3_PL_17' : 1098, + 'XILPM_RESET_GPO3_PL_18' : 1099, + 'XILPM_RESET_GPO3_PL_19' : 1100, + 'XILPM_RESET_GPO3_PL_20' : 1101, + 'XILPM_RESET_GPO3_PL_21' : 1102, + 'XILPM_RESET_GPO3_PL_22' : 1103, + 'XILPM_RESET_GPO3_PL_23' : 1104, + 'XILPM_RESET_GPO3_PL_24' : 1105, + 'XILPM_RESET_GPO3_PL_25' : 1106, + 'XILPM_RESET_GPO3_PL_26' : 1107, + 'XILPM_RESET_GPO3_PL_27' : 1108, + 'XILPM_RESET_GPO3_PL_28' : 1109, + 'XILPM_RESET_GPO3_PL_29' : 1110, + 'XILPM_RESET_GPO3_PL_30' : 1111, + 'XILPM_RESET_GPO3_PL_31' : 1112, + 'XILPM_RESET_RPU_LS' : 1113, + 'XILPM_RESET_PS_ONLY' : 1114, + 'XILPM_RESET_PL' : 1115, + 'XILPM_RESET_GPIO5_EMIO_92' : 1116, + 'XILPM_RESET_GPIO5_EMIO_93' : 1117, + 'XILPM_RESET_GPIO5_EMIO_94' : 1118, + 'XILPM_RESET_GPIO5_EMIO_95' : 1119, + + 'PM_CONFIG_MASTER_SECTION_ID' : 0x101, + 'PM_CONFIG_SLAVE_SECTION_ID' : 0x102, + 'PM_CONFIG_PREALLOC_SECTION_ID' : 0x103, + 'PM_CONFIG_POWER_SECTION_ID' : 0x104, + 'PM_CONFIG_RESET_SECTION_ID' : 0x105, + 'PM_CONFIG_SHUTDOWN_SECTION_ID' : 0x106, + 'PM_CONFIG_SET_CONFIG_SECTION_ID' : 0x107, + 'PM_CONFIG_GPO_SECTION_ID' : 0x108, + + 'PM_SLAVE_FLAG_IS_SHAREABLE' : 0x1, + 'PM_MASTER_USING_SLAVE_MASK' : 0x2, + + 'PM_CONFIG_GPO1_MIO_PIN_34_MAP' : (1 << 10), + 'PM_CONFIG_GPO1_MIO_PIN_35_MAP' : (1 << 11), + 'PM_CONFIG_GPO1_MIO_PIN_36_MAP' : (1 << 12), + 'PM_CONFIG_GPO1_MIO_PIN_37_MAP' : (1 << 13), + + 'PM_CONFIG_GPO1_BIT_2_MASK' : (1 << 2), + 'PM_CONFIG_GPO1_BIT_3_MASK' : (1 << 3), + 'PM_CONFIG_GPO1_BIT_4_MASK' : (1 << 4), + 'PM_CONFIG_GPO1_BIT_5_MASK' : (1 << 5), + + 'SUSPEND_TIMEOUT' : 0xFFFFFFFF, + + 'PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK' : 0x00000001, + 'PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK' : 0x00000100, + 'PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK' : 0x00000200, +} + +in_file = open(args.in_file, mode='r') +out_file = open(args.out_file, mode='wb') + +num_re = re.compile(r"^([0-9]+)U?$") +const_re = re.compile(r"^([A-Z_][A-Z0-9_]*)$") + +def process_item(item): + logging.debug("* ITEM " + item) + + value = 0 + for item in item.split('|'): + item = item.strip() + + num_match = num_re .match(item) + const_match = const_re.match(item) + + if num_match: + num = int(num_match.group(1)) + logging.debug(" - num " + str(num)) + value |= num + elif const_match: + name = const_match.group(1) + if not name in pm_define: + sys.stderr.write("Unknown define " + name + "!\n") + exit(1) + num = pm_define[name] + logging.debug(" - def " + hex(num)) + value |= num + + logging.debug(" = res " + hex(value)) + out_file.write(struct.pack('<L', value)) + + +# Read all code +code = in_file.read() + +# remove comments +code = re.sub('//.*?\n|/\*.*?\*/', '', code, flags=re.DOTALL) + +# remove everything outside the XPm_ConfigObject array definition +code = re.search('const u32 XPm_ConfigObject.*= {\n(.*)};', + code, flags=re.DOTALL).group(1) + +# Process each comma-separated array item +for item in code.split(','): + item = item.strip() + if item: + process_item(item) + +print("Wrote %d bytes" % out_file.tell()) diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh new file mode 100755 index 0000000000..384bb56e1a --- /dev/null +++ b/tools/zynqmp_psu_init_minimize.sh @@ -0,0 +1,148 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com> +# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net> + +usage() +{ + cat <<EOF + +Transform a pair of psu_init_gpl.c and .h files produced by the Xilinx +Vivado tool for ZynqMP into a smaller psu_init_gpl.c file that is almost +checkpatch compliant. Minor coding style might still be needed. Must be +run from the top-level U-Boot source directory. + +Usage: zynqmp_psu_init_minimize.sh INPUT_DIR OUTPUT_DIR +Example: zynqmp_psu_init_minimize.sh \\ + /path/to/original/psu_init_gpl_c_and_h/ \\ + board/xilinx/zynqmp/<my_board>/ + +Notes: INPUT_DIR must contain both .c and .h files. + If INPUT_DIR and OUTPUT_DIR are the same directory, + psu_init_gpl.c will be overwritten. + +EOF +} + +set -o errexit -o errtrace +set -o nounset + +if [ $# -ne 2 ] +then + usage >&2 + exit 1 +fi + +IN="${1}/psu_init_gpl.c" +OUT="${2}/psu_init_gpl.c" +TMP=$(mktemp /tmp/psu_init_gpl.XXXXXX) +trap "rm ${TMP}" ERR + +# Step through a temp file to allow both $IN!=$OUT and $IN==$OUT +sed -e '/sleep.h/d' \ + -e '/xil_io.h/d' \ + ${IN} >${TMP} +cp ${TMP} ${OUT} + +# preprocess to expand defines, then remove cpp lines starting with '#' +gcc -I${1} -E ${OUT} -o ${TMP} +sed '/^#/d' ${TMP} >${OUT} + +# Remove trivial code before psu_pll_init_data() +sed -ni '/psu_pll_init_data/,$p' ${OUT} + +# Functions are lowercase in U-Boot, rename them +sed -i 's/PSU_Mask_Write/psu_mask_write/g' ${OUT} +sed -i 's/mask_pollOnValue/mask_pollonvalue/g' ${OUT} +sed -i 's/RegValue/regvalue/g' ${OUT} +sed -i 's/MaskStatus/maskstatus/g' ${OUT} + +sed -i '/&= psu_peripherals_powerdwn_data()/d' ${OUT} + +FUNCS_TO_REMOVE="psu_protection +psu_..._protection +psu_init_xppu_aper_ram +mask_delay(u32 +mask_read(u32 +dpll_prog +mask_poll(u32 +mask_pollonvalue(u32 +psu_ps_pl_reset_config_data +psu_ps_pl_isolation_removal_data +psu_apply_master_tz +psu_post_config_data +psu_post_config_data +psu_peripherals_powerdwn_data +psu_init_ddr_self_refresh +xmpu +xppu +" +for i in $FUNCS_TO_REMOVE; do +sed -i "/$i/,/^}$/d" ${OUT} +done + +scripts/Lindent ${OUT} + +# Prepend 'static' to internal functions +sed -i 's/^.*data(void)$/static &/g' ${OUT} +sed -i 's/^.*psu_afi_config(void)$/static &/g' ${OUT} +sed -i 's/^void init_peripheral/static &/g' ${OUT} +sed -i 's/^int serdes/static &/g' ${OUT} +sed -i 's/^int init_serdes/static &/g' ${OUT} +sed -i 's/^unsigned long /static &/g' ${OUT} + +sed -i 's/()$/(void)/g' ${OUT} +sed -i 's/0X/0x/g' ${OUT} + +# return (0) -> return 0 +sed -ri 's/return \(([0-9]+)\)/return \1/g' ${OUT} + +# Add header +cat << EOF >${TMP} +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +EOF + +cat ${OUT} >>${TMP} +cp ${TMP} ${OUT} + +# Temporarily convert newlines to do some mangling across lines +tr "\n" "\r" <${OUT} >${TMP} + +# Cleanup empty loops. E.g.: +# |while (e) {| +# | | ==> |while (e)| +# | } | | ; | +# | | +sed -i -r 's| \{\r+(\t*)\}\r\r|\n\1\t;\n|g' ${TMP} + +# Remove empty line between variable declaration +sed -i -r 's|\r(\r\t(unsigned )?int )|\1|g' ${TMP} + +# Remove empty lines at function beginning/end +sed -i -e 's|\r{\r\r|\r{\r|g' ${TMP} +sed -i -e 's|\r\r}\r|\r}\r|g' ${TMP} + +# Remove empty lines after '{' line +sed -i -e 's| {\r\r| {\r|g' ${TMP} + +# Remove braces {} around single statement blocks. E.g.: +# | while (e) { | | while (e) | +# | stg(); | => | stg();| +# | } | +sed -i -r 's| \{(\r[^\r]*;)\r\t*\}|\1|g' ${TMP} + +# Remove Unnecessary parentheses around 'n_code <= 0x3C' and similar. E.g.: +# if ((p_code >= 0x26) && ...) -> if (p_code >= 0x26 && ...) +sed -i -r 's|\((._code .= [x[:xdigit:]]+)\)|\1|g' ${TMP} + +# Convert back newlines +tr "\r" "\n" <${TMP} >${OUT} + +rm ${TMP} |