diff options
Diffstat (limited to 'arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts')
| -rw-r--r-- | arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 236 |
1 files changed, 236 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts new file mode 100644 index 0000000000..3fdfcc8a11 --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -0,0 +1,236 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm016-dc2 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm016-dc2 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + can0 = &can0; + can1 = &can1; + ethernet0 = &gem2; + gpio0 = &gpio; + i2c0 = &i2c0; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &spi0; + spi1 = &spi1; + usb0 = &usb1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem2 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@5 { + reg = <5>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u26: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* IRQ not connected */ + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&nand0 { + status = "okay"; + arasan,has-mdma; + num-cs = <2>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; + + partition@6 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x1 0x0 0x400000>; + }; + partition@7 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x1 0x400000 0x1400000>; + }; + partition@8 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x1 0x1800000 0x400000>; + }; + partition@9 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x1 0x1C00000 0x1400000>; + }; + partition@10 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x1 0x3000000 0x400000>; + }; + partition@11 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x1 0x3400000 0xFCC00000>; + }; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <1>; + spi0_flash0: spi0_flash0@0 { + compatible = "m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + spi0_flash0@00000000 { + label = "spi0_flash0"; + reg = <0x0 0x100000>; + }; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <1>; + spi1_flash0: spi1_flash0@0 { + compatible = "mtd_dataflash"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + + spi1_flash0@00000000 { + label = "spi1_flash0"; + reg = <0x0 0x84000>; + }; + }; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; |