3 files changed, 0 insertions, 43 deletions
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index cf0aadf03c..0461219ca3 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -12,7 +12,6 @@
 #include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/phy/phy.h>
-#include <include/dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Smartlynq+ DLC21 RevA";
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
deleted file mode 100644
index 467df9f23a..0000000000
--- a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * dts file for Xilinx ZynqMP K26/KV260 SD wiring
- *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-/* SD0 only supports 3.3V, no level shifter */
-&sdhci1 { /* on CC - MIO 39 - 51 */
-	status = "okay";
-	no-1-8-v;
-	disable-wp;
-	broken-cd;
-	xlnx,mio-bank = <1>;
-	/* Do not run SD in HS mode from bootloader */
-	sdhci-caps-mask = <0 0x200000>;
-	sdhci-caps = <0 0>;
-	max-frequency = <19000000>;
-};
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
deleted file mode 100644
index 34e6328fb6..0000000000
--- a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * dts file for Xilinx ZynqMP Z2-VSOM
- *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-/* SD0 only supports 3.3V, no level shifter */
-&sdhci1 { /* FIXME - on CC - MIO 39 - 51 */
-	status = "okay";
-	no-1-8-v;
-	disable-wp;
-	broken-cd;
-	xlnx,mio-bank = <1>;
-	/* Do not run SD in HS mode from bootloader */
-	sdhci-caps-mask = <0 0x200000>;
-	sdhci-caps = <0 0>;
-	max-frequency = <19000000>;
-};