diff options
Diffstat (limited to 'arch/arm/imx-common')
| -rw-r--r-- | arch/arm/imx-common/cpu.c | 2 | ||||
| -rw-r--r-- | arch/arm/imx-common/init.c | 2 | ||||
| -rw-r--r-- | arch/arm/imx-common/iomux-v3.c | 13 | ||||
| -rw-r--r-- | arch/arm/imx-common/timer.c | 7 |
4 files changed, 18 insertions, 6 deletions
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index a33aa16487..632facabd7 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -159,6 +159,8 @@ const char *get_imx_type(u32 imxtype) return "6SX"; /* SoloX version of the mx6 */ case MXC_CPU_MX6UL: return "6UL"; /* Ultra-Lite version of the mx6 */ + case MXC_CPU_MX6ULL: + return "6ULL"; /* ULL version of the mx6 */ case MXC_CPU_MX51: return "51"; case MXC_CPU_MX53: diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index 3d2ce3a82e..e5dbd93c3b 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -44,7 +44,7 @@ void init_aips(void) writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4); - if (is_mx6sx() || is_mx7()) { + if (is_mx6ull() || is_mx6sx() || is_mx7()) { /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 66137d148a..392f4bcb99 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -42,6 +42,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #ifdef CONFIG_IOMUX_LPSR u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT; +#ifdef CONFIG_MX7 if (lpsr == IOMUX_CONFIG_LPSR) { base = (void *)IOMUXC_LPSR_BASE_ADDR; mux_mode &= ~IOMUX_CONFIG_LPSR; @@ -49,9 +50,17 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS; } +#else + if (is_mx6ull()) { + if (lpsr == IOMUX_CONFIG_LPSR) { + base = (void *)IOMUXC_SNVS_BASE_ADDR; + mux_mode &= ~IOMUX_CONFIG_LPSR; + } + } +#endif #endif - if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs) + if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); if (sel_input_ofs) @@ -83,7 +92,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, #if defined(CONFIG_MX6QDL) stride = 2; - if (!is_mx6dq()) + if (!is_mx6dq() && !is_mx6dqp()) p += 1; #else stride = 1; diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index a01590ced2..fb1b693161 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -44,7 +44,8 @@ static inline int gpt_has_clk_source_osc(void) { #if defined(CONFIG_MX6) if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || - is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul()) + is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() || + is_mx6ull()) return 1; return 0; @@ -83,8 +84,8 @@ int timer_init(void) if (gpt_has_clk_source_osc()) { i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; - /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */ - if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) { + /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler */ + if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) { i |= GPTCR_24MEN; /* Produce 3Mhz clock */ |