diff options
Diffstat (limited to 'arch/arm')
28 files changed, 427 insertions, 16 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 629c5e8c2d..7b80630aa1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1631,6 +1631,13 @@ config ARCH_ASPEED select OF_CONTROL imply CMD_DM +config TARGET_DURIAN + bool "Support Phytium Durian Platform" + select ARM64 + help + Support for durian platform. + It has 2GB Sdram, uart and pcie. + endchoice config ARCH_SUPPORT_TFABOOT @@ -1830,6 +1837,7 @@ source "board/woodburn/Kconfig" source "board/xilinx/Kconfig" source "board/xilinx/zynq/Kconfig" source "board/xilinx/zynqmp/Kconfig" +source "board/phytium/durian/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 94fa68250d..b9511da3f3 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -50,8 +50,8 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config SECURE_BOOT - bool "Secure Boot" +config NXP_ESBC + bool "NXP_ESBC" help Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 24c606a232..f1578b10bc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,6 +45,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A050382 imply PANIC_HANG config ARCH_LS1043A @@ -375,8 +376,8 @@ config EMC2305 Enable the EMC2305 fan controller for configuration of fan speed. -config SECURE_BOOT - bool "Secure Boot" +config NXP_ESBC + bool "NXP_ESBC" help Enable Freescale Secure Boot feature @@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool +config SYS_FSL_ERRATUM_A050382 + bool config SYS_FSL_HAS_RGMII bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index efecbc07e7..e398aecd12 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -24,10 +24,12 @@ endif ifneq ($(CONFIG_ARCH_LX2160A),) obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +obj-y += icid.o lx2160_ids.o endif ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +obj-y += icid.o ls2088_ids.o endif ifneq ($(CONFIG_ARCH_LS1043A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 8fd6c751c6..83a3319321 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -1072,6 +1072,8 @@ static void config_core_prefetch(void) if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; + else + return; prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable", &arglen, buf); @@ -1221,7 +1223,7 @@ void __efi_runtime reset_cpu(ulong addr) #endif } -#ifdef CONFIG_EFI_LOADER +#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET) void __efi_runtime EFIAPI efi_reset_system( enum efi_reset_type reset_type, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index b3e67321b4..bbd550b036 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -64,7 +64,7 @@ void get_sys_info(struct sys_info *sys_info) }; uint i, cluster; -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) uint rcw_tmp; #endif uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -131,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) CONFIG_SYS_FSL_IFC_CLK_DIV; #endif -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) #define HWA_CGA_M2_CLK_SEL 0x00380000 #define HWA_CGA_M2_CLK_SHIFT 19 rcw_tmp = in_le32(&gur->rcwsr[5]); @@ -159,7 +159,7 @@ void get_sys_info(struct sys_info *sys_info) break; } #endif -#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) sys_info->freq_cga_m2 = sys_info->freq_systembus; #endif } @@ -176,10 +176,10 @@ int get_clocks(void) #endif #if defined(CONFIG_FSL_ESDHC) #if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; #endif -#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) gd->arch.sdhc_clk = sys_info.freq_cga_m2; #endif #else diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c index d9d125e8ba..9462298fbf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = { SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID), SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID), SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID), +#ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = { SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), +#endif }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c index 49e27553b1..23743ae10c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = { SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID), +#ifdef CONFIG_FSL_CAAM SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = { SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), +#endif }; int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c new file mode 100644 index 0000000000..e6403b7952 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_SATA1_STREAM_ID), + SET_SATA_ICID(2, "fsl,ls2080a-ahci", FSL_SATA2_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c new file mode 100644 index 0000000000..3a0ed1fa55 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID), + SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID), + SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID), + SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 1f1869e8cf..f0df88c565 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -341,7 +341,8 @@ void fsl_lsch3_early_init_f(void) bypass_smmu(); #endif -#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) +#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ + defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) set_icids(); #endif } @@ -828,6 +829,11 @@ int fsl_setenv_mcinitcmd(void) #endif #ifdef CONFIG_BOARD_LATE_INIT +__weak int fsl_board_late_init(void) +{ + return 0; +} + int board_late_init(void) { #ifdef CONFIG_CHAIN_OF_TRUST @@ -862,6 +868,6 @@ int board_late_init(void) qspi_ahb_init(); #endif - return 0; + return fsl_board_late_init(); } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 8eeeef199b..3f6a5f6a42 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -34,7 +34,7 @@ u32 spl_boot_device(void) void spl_board_init(void) { -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2) +#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2) /* * In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b90eb25595..5a64fcc5a7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -835,6 +835,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb +dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 4be1ab87d2..abc8b21a11 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -192,4 +192,9 @@ status = "disabled"; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + }; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 174d202306..5c110ef9dd 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -97,6 +97,13 @@ u-boot,dm-spl; }; + wkup_vtm0: wkup_vtm@42050000 { + compatible = "ti,am654-vtm", "ti,am654-avs"; + reg = <0x42050000 0x25c>; + power-domains = <&k3_pds 80>; + #thermal-sensor-cells = <1>; + }; + clk_200mhz: dummy_clock { compatible = "fixed-clock"; #clock-cells = <0>; @@ -131,6 +138,12 @@ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; +&wkup_vtm0 { + vdd-supply-3 = <&vdd_mpu>; + vdd-supply-4 = <&vdd_mpu>; + u-boot,dm-spl; +}; + &wkup_pmx0 { u-boot,dm-spl; wkup_uart0_pins_default: wkup_uart0_pins_default { @@ -211,4 +224,18 @@ pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; + u-boot,dm-spl; + + vdd_mpu: tps62363@60 { + compatible = "ti,tps62363"; + reg = <0x60>; + regulator-name = "VDD_MPU"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-always-on; + regulator-boot-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + u-boot,dm-spl; + }; }; diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi index 92beeea34d..5dd07ac4da 100644 --- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -57,6 +57,17 @@ clock-names = "fclk"; }; + wkup_i2c0: i2c@42120000 { + compatible = "ti,j721e-i2c", "ti,omap4-i2c"; + reg = <0x0 0x42120000 0x0 0x100>; + interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 197 0>; + power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; + }; + mcu_uart0: serial@40a00000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 54d7998d27..41af48214f 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -59,6 +59,13 @@ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; mbox-names = "tx", "rx"; }; + + wkup_vtm0: wkup_vtm@42040000 { + compatible = "ti,am654-vtm", "ti,j721e-avs"; + reg = <0x0 0x42040000 0x0 0x330>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; &dmsc { @@ -86,6 +93,13 @@ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; + + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ + >; + }; }; &main_pmx0 { @@ -140,4 +154,34 @@ ti,driver-strength-ohm = <50>; }; +&wkup_i2c0 { + u-boot,dm-spl; + tps659413a: tps659413a@48 { + reg = <0x48>; + compatible = "ti,tps659413"; + u-boot,dm-spl; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + regulators: regulators { + u-boot,dm-spl; + buck12_reg: buck12 { + /*VDD_MPU*/ + regulator-name = "buck12"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + u-boot,dm-spl; + }; + }; + }; +}; + +&wkup_vtm0 { + vdd-supply-2 = <&buck12_reg>; + u-boot,dm-spl; +}; + #include "k3-j721e-common-proc-board-u-boot.dtsi" diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi index 1abd9a3887..e5d9e4f1b1 100644 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi @@ -17,6 +17,26 @@ }; }; +&gpio1 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio2 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio3 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio5 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio6 { + /delete-property/ u-boot,dm-spl; +}; + &i2c1 { clock-frequency = <400000>; }; diff --git a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi index 976330f897..76f74326ae 100644 --- a/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi +++ b/arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi @@ -21,6 +21,26 @@ clock-frequency = <400000>; }; +&gpio1 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio2 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio3 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio5 { + /delete-property/ u-boot,dm-spl; +}; + +&gpio6 { + /delete-property/ u-boot,dm-spl; +}; + /delete-node/ &uart2; /delete-node/ &uart3; /delete-node/ &mmc2; diff --git a/arch/arm/dts/phytium-durian.dts b/arch/arm/dts/phytium-durian.dts new file mode 100644 index 0000000000..3b76949a26 --- /dev/null +++ b/arch/arm/dts/phytium-durian.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019, Phytium Ltd. + * shuyiqi <shuyiqi@phytium.com.cn> + */ + +/dts-v1/; + +/ { + model = "Phytium Durian"; + compatible = "phytium,durian"; + #address-cells = <2>; + #size-cells = <2>; + + pcie-controller@40000000 { + compatible = "phytium,pcie-host-1.0"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xF00000>, + <0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clock = <48000000>; + }; +}; + diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 37e2fe4e66..3c06a55cb8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -166,7 +166,7 @@ extern int fman_icid_tbl_sz; #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ - (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ + (CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \ (FSL_SEC_JR##jr_num##_OFFSET == \ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ ? NULL \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 4f050470dd..d46477d96e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -87,6 +87,8 @@ /* SATA */ #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) +#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000) +#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000) /* QDMA */ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) @@ -445,7 +447,9 @@ struct ccsr_gur { u8 res_538[0x550 - 0x538]; /* add more registers when needed */ u32 sata1_amqr; u32 sata2_amqr; - u8 res_558[0x570-0x558]; /* add more registers when needed */ + u32 sata3_amqr; + u32 sata4_amqr; + u8 res_560[0x570 - 0x560]; /* add more registers when needed */ u32 misc1_amqr; u8 res_574[0x590-0x574]; /* add more registers when needed */ u32 spare1_amqr; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 93bdcc4caa..94ea99a349 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -105,8 +105,25 @@ #define FSL_SEC_JR4_STREAM_ID 68 #define FSL_SDMMC2_STREAM_ID 69 + +/* + * Erratum A-050382 workaround + * + * Description: + * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not + * correctly forwarded to the SMMU. + * Workaround: + * Program eDMA ICID in the eDMA_AMQR register in DCFG to 40. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A050382 +#define FSL_EDMA_STREAM_ID 40 +#else #define FSL_EDMA_STREAM_ID 70 +#endif + #define FSL_GPU_STREAM_ID 71 #define FSL_DISPLAY_STREAM_ID 72 +#define FSL_SATA3_STREAM_ID 73 +#define FSL_SATA4_STREAM_ID 74 #endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 723f3cf497..8959749ad6 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -23,6 +23,7 @@ #ifdef __KERNEL__ #include <linux/types.h> +#include <linux/kernel.h> #include <asm/byteorder.h> #include <asm/memory.h> #include <asm/barriers.h> @@ -315,9 +316,105 @@ extern void _memset_io(unsigned long, int, size_t); extern void __readwrite_bug(const char *fn); +/* Optimized copy functions to read from/write to IO sapce */ +#ifdef CONFIG_ARM64 +/* + * Copy data from IO memory space to "real" memory space. + */ +static inline +void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) +{ + while (count && !IS_ALIGNED((unsigned long)from, 8)) { + *(u8 *)to = __raw_readb(from); + from++; + to++; + count--; + } + + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } + + while (count) { + *(u8 *)to = __raw_readb(from); + from++; + to++; + count--; + } +} + +/* + * Copy data from "real" memory space to IO memory space. + */ +static inline +void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) +{ + while (count && !IS_ALIGNED((unsigned long)to, 8)) { + __raw_writeb(*(u8 *)from, to); + from++; + to++; + count--; + } + + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } + + while (count) { + __raw_writeb(*(u8 *)from, to); + from++; + to++; + count--; + } +} + +/* + * "memset" on IO memory space. + */ +static inline +void __memset_io(volatile void __iomem *dst, int c, size_t count) +{ + u64 qc = (u8)c; + + qc |= qc << 8; + qc |= qc << 16; + qc |= qc << 32; + + while (count && !IS_ALIGNED((unsigned long)dst, 8)) { + __raw_writeb(c, dst); + dst++; + count--; + } + + while (count >= 8) { + __raw_writeq(qc, dst); + dst += 8; + count -= 8; + } + + while (count) { + __raw_writeb(c, dst); + dst++; + count--; + } +} +#endif /* CONFIG_ARM64 */ + +#ifdef CONFIG_ARM64 +#define memset_io(a, b, c) __memset_io((a), (b), (c)) +#define memcpy_fromio(a, b, c) __memcpy_fromio((a), (b), (c)) +#define memcpy_toio(a, b, c) __memcpy_toio((a), (b), (c)) +#else #define memset_io(a, b, c) memset((void *)(a), (b), (c)) #define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) #define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) +#endif /* * If this architecture has ISA IO, then define the isa_read/isa_write diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index b2913e8165..47c223917a 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -235,12 +235,18 @@ static void cache_disable(uint32_t cache_bit) /* if cache isn;t enabled no need to disable */ if ((reg & CR_C) != CR_C) return; +#ifdef CONFIG_SYS_ARM_MMU /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; +#endif } reg = get_cr(); +#ifdef CONFIG_SYS_ARM_MMU if (cache_bit == (CR_C | CR_M)) +#elif defined(CONFIG_SYS_ARM_MPU) + if (cache_bit == CR_C) +#endif flush_dcache_all(); set_cr(reg & ~cache_bit); } diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 0b564f7bd1..99edcd9a24 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -116,6 +116,13 @@ void board_init_f(ulong dummy) /* Perform EEPROM-based board detection */ do_board_detect(); +#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs), + &dev); + if (ret) + printf("AVS init failed: %d\n", ret); +#endif + #ifdef CONFIG_K3_AM654_DDRSS ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 5e3813252b..d0bf86abeb 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -118,6 +118,13 @@ void board_init_f(ulong dummy) preloader_console_init(); #endif +#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0) + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs), + &dev); + if (ret) + printf("AVS init failed: %d\n", ret); +#endif + #if defined(CONFIG_K3_J721E_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index fc0a54214f..3770e07258 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,5 +1,8 @@ if ARCH_SOCFPGA +config ERR_PTR_OFFSET + default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range + config NR_DRAM_BANKS default 1 |