diff options
Diffstat (limited to 'arch/arm')
67 files changed, 118 insertions, 287 deletions
diff --git a/arch/arm/cpu/arm920t/ep93xx/cpu.c b/arch/arm/cpu/arm920t/ep93xx/cpu.c index c9ea4e46a8..3435bdc748 100644 --- a/arch/arm/cpu/arm920t/ep93xx/cpu.c +++ b/arch/arm/cpu/arm920t/ep93xx/cpu.c @@ -14,7 +14,7 @@ #include <asm/io.h> /* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */ -extern void reset_cpu(ulong addr) +extern void reset_cpu(void) { struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; uint32_t value; diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c index e9d5577921..0cd3a03981 100644 --- a/arch/arm/cpu/arm920t/imx/timer.c +++ b/arch/arm/cpu/arm920t/imx/timer.c @@ -81,7 +81,7 @@ ulong get_tbclk(void) /* * Reset the cpu by setting up the watchdog timer and let him time out */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* Disable watchdog and set Time-Out field to 0 */ WCR = 0x00000000; diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c index ec73393d0f..6d77ad3b6d 100644 --- a/arch/arm/cpu/arm926ejs/armada100/timer.c +++ b/arch/arm/cpu/arm926ejs/armada100/timer.c @@ -142,7 +142,7 @@ int timer_init(void) * 2. Write key value to TMP_WSAR reg. * 3. Perform write operation. */ -void reset_cpu(unsigned long ignored) +void reset_cpu(void) { struct armd1mpmu_registers *mpmu = (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; diff --git a/arch/arm/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c index 38df1c9402..7844a99c16 100644 --- a/arch/arm/cpu/arm926ejs/mx25/reset.c +++ b/arch/arm/cpu/arm926ejs/mx25/reset.c @@ -23,7 +23,7 @@ /* * Reset the cpu by setting up the watchdog timer and let it time out */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c index 320b0a65e7..496fb30817 100644 --- a/arch/arm/cpu/arm926ejs/mx27/reset.c +++ b/arch/arm/cpu/arm926ejs/mx27/reset.c @@ -23,7 +23,7 @@ /* * Reset the cpu by setting up the watchdog timer and let it time out */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index c9362136fb..344b9b4e55 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -32,9 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; /* Lowlevel init isn't used on i.MX28, so just have a dummy here */ __weak void lowlevel_init(void) {} -void reset_cpu(ulong ignored) __attribute__((noreturn)); +void reset_cpu(void) __attribute__((noreturn)); -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE; diff --git a/arch/arm/cpu/arm926ejs/spear/reset.c b/arch/arm/cpu/arm926ejs/spear/reset.c index a316540d52..97a624e16c 100644 --- a/arch/arm/cpu/arm926ejs/spear/reset.c +++ b/arch/arm/cpu/arm926ejs/spear/reset.c @@ -11,7 +11,7 @@ #include <asm/arch/spr_syscntl.h> #include <linux/delay.h> -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct syscntl_regs *syscntl_regs_p = (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index fb0ea5e817..334bb54274 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -56,7 +56,7 @@ static void cache_flush (void) #ifndef CONFIG_ARCH_INTEGRATOR -__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +__attribute__((noreturn)) void reset_cpu(void) { writew(0x0, 0xfffece10); writew(0x8, 0xfffece10); diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c index fda5a9527e..1491e5c88b 100644 --- a/arch/arm/cpu/armv7/bcm281xx/reset.c +++ b/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -13,7 +13,7 @@ #define CLKS_SHIFT 20 /* Clock period shift */ #define LD_SHIFT 0 /* Reload value shift */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* * Set WD enable, RST enable, diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c b/arch/arm/cpu/armv7/bcmcygnus/reset.c index 3bfed34533..63992fd870 100644 --- a/arch/arm/cpu/armv7/bcmcygnus/reset.c +++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c @@ -10,7 +10,7 @@ #define CRMU_MAIL_BOX1 0x03024028 #define CRMU_SOFT_RESET_CMD 0xFFFFFFFF -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* Send soft reset command via Mailbox. */ writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1); diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c b/arch/arm/cpu/armv7/bcmnsp/reset.c index 675f99fe99..a3137752e8 100644 --- a/arch/arm/cpu/armv7/bcmnsp/reset.c +++ b/arch/arm/cpu/armv7/bcmnsp/reset.c @@ -9,7 +9,7 @@ #define CRU_RESET_OFFSET 0x1803F184 -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* Reset the cpu by setting software reset request bit */ writel(0x1, CRU_RESET_OFFSET); diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 146cf52608..19ff432352 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -176,9 +176,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) { } -void arm_init_domains(void) -{ -} #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index f26a5b22fd..d863c9625a 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -375,7 +375,7 @@ void smp_kick_all_cpus(void) } #endif -void reset_cpu(ulong addr) +void reset_cpu(void) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 3c71a37a74..3baa761ec7 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -88,7 +88,7 @@ int print_cpuinfo(void) } #endif -void reset_cpu(ulong ignored) +void reset_cpu(void) { void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR; const u32 sw_rst_enb_bitpos = 3; diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c index fb67de10f4..77d4477c8d 100644 --- a/arch/arm/cpu/armv7/stv0991/reset.c +++ b/arch/arm/cpu/armv7/stv0991/reset.c @@ -9,7 +9,7 @@ #include <asm/io.h> #include <asm/arch/stv0991_wdru.h> #include <linux/delay.h> -void reset_cpu(ulong ignored) +void reset_cpu(void) { puts("System is going to reboot ...\n"); /* diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index 7f827da033..63721018c1 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -47,7 +47,7 @@ int cleanup_before_linux(void) /* * Perform the low-level reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { /* * Perform reset but keep priority group unchanged. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 3a5bf77826..270a72e550 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1231,7 +1231,7 @@ int timer_init(void) __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; -void __efi_runtime reset_cpu(ulong addr) +void __efi_runtime reset_cpu(void) { #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) /* clear the RST_REQ_MSK and SW_RST_REQ */ @@ -1260,7 +1260,7 @@ void __efi_runtime EFIAPI efi_reset_system( case EFI_RESET_COLD: case EFI_RESET_WARM: case EFI_RESET_PLATFORM_SPECIFIC: - reset_cpu(0); + reset_cpu(); break; case EFI_RESET_SHUTDOWN: /* Nothing we can do */ diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c index 0fc9885222..d1ae10b1a7 100644 --- a/arch/arm/cpu/armv8/s32v234/generic.c +++ b/arch/arm/cpu/armv8/s32v234/generic.c @@ -319,7 +319,7 @@ static char *get_reset_cause(void) #define SRC_SCR_SW_RST (1<<12) -void reset_cpu(ulong addr) +void reset_cpu(void) { printf("Feature not supported.\n"); }; diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index ea91d8aaec..c7efb67754 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -267,9 +267,9 @@ void i2c_clk_enable(void) writel(readl(CKEN) | CKEN14_I2C, CKEN); } -void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn)); +void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn)); -void reset_cpu(ulong ignored) +void reset_cpu(void) { uint32_t tmp; diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c index 91e100af1b..6f67f7fc22 100644 --- a/arch/arm/cpu/sa1100/cpu.c +++ b/arch/arm/cpu/sa1100/cpu.c @@ -55,7 +55,7 @@ static void cache_flush (void) #define RSRR 0x00 #define RCSR 0x04 -__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +__attribute__((noreturn)) void reset_cpu(void) { /* repeat endlessly */ while (1) { diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index c20e05ec7f..b10edf805b 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -35,7 +35,6 @@ void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option); void arm_init_before_mmu(void); -void arm_init_domains(void); void cpu_cache_initialization(void); void dram_bank_mmu_setup(int bank); diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 5fe83699f4..11fceec4d2 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -397,20 +397,6 @@ static inline void set_cr(unsigned int val) isb(); } -static inline unsigned int get_dacr(void) -{ - unsigned int val; - asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); - return val; -} - -static inline void set_dacr(unsigned int val) -{ - asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" - : : "r" (val) : "cc"); - isb(); -} - #ifdef CONFIG_ARMV7_LPAE /* Long-Descriptor Translation Table Level 1/2 Bits */ #define TTB_SECT_XN_MASK (1ULL << 54) @@ -475,7 +461,7 @@ enum dcache_option { #define TTB_SECT_XN_MASK (1 << 4) #define TTB_SECT_C_MASK (1 << 3) #define TTB_SECT_B_MASK (1 << 2) -#define TTB_SECT (2 << 0) +#define TTB_SECT (2 << 0) /* * Short-descriptor format memory region attributes, without TEX remap @@ -489,7 +475,7 @@ enum dcache_option { */ enum dcache_option { DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, - DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, + DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), }; diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 24050e5bdd..aab1bf4360 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -22,10 +22,6 @@ __weak void arm_init_before_mmu(void) { } -__weak void arm_init_domains(void) -{ -} - static void set_section_phys(int section, phys_addr_t phys, enum dcache_option option) { @@ -203,11 +199,12 @@ static inline void mmu_setup(void) asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (gd->arch.tlb_addr) : "memory"); #endif - /* Set the access control to all-supervisor */ + /* + * initial value of Domain Access Control Register (DACR) + * Set the access control to client (1U) for each of the 16 domains + */ asm volatile("mcr p15, 0, %0, c3, c0, 0" - : : "r" (~0)); - - arm_init_domains(); + : : "r" (0x55555555)); /* and enable the mmu */ reg = get_cr(); /* get control reg. */ diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 05bb1a38b3..6dc27d1d58 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -53,7 +53,7 @@ int disable_interrupts(void) void bad_mode (void) { panic ("Resetting CPU ...\n"); - reset_cpu(0); + reset_cpu(); } static void show_efi_loaded_images(struct pt_regs *regs) diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c index 2ae1c5ba76..277854aa87 100644 --- a/arch/arm/lib/interrupts_m.c +++ b/arch/arm/lib/interrupts_m.c @@ -59,7 +59,7 @@ void dump_regs(struct autosave_regs *regs) void bad_mode(void) { panic("Resetting CPU ...\n"); - reset_cpu(0); + reset_cpu(); } void do_hard_fault(struct autosave_regs *autosave_regs) diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 4f1a768bfe..95169bae1c 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -39,7 +39,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) disable_interrupts(); reset_misc(); - reset_cpu(0); + reset_cpu(); /*NOTREACHED*/ return 0; diff --git a/arch/arm/mach-at91/arm920t/reset.c b/arch/arm/mach-at91/arm920t/reset.c index d92bc57d66..91e375146a 100644 --- a/arch/arm/mach-at91/arm920t/reset.c +++ b/arch/arm/mach-at91/arm920t/reset.c @@ -24,7 +24,7 @@ void __attribute__((weak)) board_reset(void) /* true empty function for defining weak symbol */ } -void reset_cpu(ulong ignored) +void reset_cpu(void) { at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST; diff --git a/arch/arm/mach-at91/arm926ejs/reset.c b/arch/arm/mach-at91/arm926ejs/reset.c index 56fbbd991e..6acbfa3301 100644 --- a/arch/arm/mach-at91/arm926ejs/reset.c +++ b/arch/arm/mach-at91/arm926ejs/reset.c @@ -12,7 +12,7 @@ #include <asm/arch/at91_rstc.h> /* Reset the cpu by telling the reset controller to do so */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; diff --git a/arch/arm/mach-at91/armv7/reset.c b/arch/arm/mach-at91/armv7/reset.c index 8f4c81d1af..1ea415ea9e 100644 --- a/arch/arm/mach-at91/armv7/reset.c +++ b/arch/arm/mach-at91/armv7/reset.c @@ -15,7 +15,7 @@ #include <asm/arch/at91_rstc.h> /* Reset the cpu by telling the reset controller to do so */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c index 2b4ccd4727..f13ac0c637 100644 --- a/arch/arm/mach-bcm283x/reset.c +++ b/arch/arm/mach-bcm283x/reset.c @@ -48,7 +48,7 @@ __reset_cpu(struct bcm2835_wdog_regs *wdog_regs, ulong ticks) writel(BCM2835_WDOG_PASSWORD | rstc, &wdog_regs->rstc); } -void reset_cpu(ulong ticks) +void reset_cpu(void) { struct bcm2835_wdog_regs *regs = (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR; diff --git a/arch/arm/mach-davinci/reset.c b/arch/arm/mach-davinci/reset.c index 4e6031a593..0d59eb6e3c 100644 --- a/arch/arm/mach-davinci/reset.c +++ b/arch/arm/mach-davinci/reset.c @@ -12,7 +12,7 @@ #include <asm/arch/timer_defs.h> #include <asm/arch/hardware.h> -void reset_cpu(unsigned long a) +void reset_cpu(void) { struct davinci_timer *const wdttimer = (struct davinci_timer *)DAVINCI_WDOG_BASE; diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index 810fa348ee..a07c87a2c8 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -20,7 +20,7 @@ extern void _main(void); void *secondary_boot_addr = (void *)_main; #endif /* CONFIG_TARGET_ESPRESSO7420 */ -void reset_cpu(ulong addr) +void reset_cpu(void) { #ifdef CONFIG_CPU_V7A writel(0x1, samsung_get_base_swreset()); diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5f37282ff1..e6bc977fc8 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -923,7 +923,7 @@ usb_modify_speed: #endif #if !CONFIG_IS_ENABLED(SYSRESET) -void reset_cpu(ulong addr) +void reset_cpu(void) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 8dd6b4d40e..320f24dd29 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -197,7 +197,7 @@ void s_init(void) #endif #ifndef CONFIG_ULP_WATCHDOG -void reset_cpu(ulong addr) +void reset_cpu(void) { setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET); while (1) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 4fbf14843e..9191f686f0 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -320,7 +320,7 @@ int fdt_disable_node(void *blob, char *node_path) #endif #ifndef CONFIG_SYSRESET -void reset_cpu(ulong ignored) +void reset_cpu(void) { } #endif diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 7dea600d50..9ee3284156 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -345,7 +345,7 @@ void ddr3_check_ecc_int(u32 base) if (!ecc_test) { puts("Reseting the device ...\n"); - reset_cpu(0); + reset_cpu(); } } @@ -445,7 +445,7 @@ void ddr3_err_reset_workaround(void) tmp &= ~KS2_RSTYPE_PLL_SOFT; __raw_writel(tmp, KS2_RSTCTRL_RSCFG); - reset_cpu(0); + reset_cpu(); } } #endif diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 4950f14655..5b95f60500 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -192,7 +192,7 @@ int arch_cpu_init(void) return 0; } -void reset_cpu(ulong addr) +void reset_cpu(void) { volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL); u32 tmp; diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 551c22a8ea..9c818fa45e 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -19,7 +19,7 @@ #include <asm/arch/soc.h> #include <mvebu_mmc.h> -void reset_cpu(unsigned long ignored) +void reset_cpu(void) { struct kwcpu_registers *cpureg = (struct kwcpu_registers *)KW_CPU_REG_BASE; diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index 32af620605..c2586d0929 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -17,28 +17,17 @@ static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; -void reset_cpu(ulong addr) +void reset_cpu(void) { /* Enable watchdog clock */ setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); - /* To be compatible with the original U-Boot code: - * addr: - 0: perform hard reset. - * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */ - if (addr == 0) { - /* Reset pulse length is 13005 peripheral clock frames */ - writel(13000, &wdt->pulse); + /* Reset pulse length is 13005 peripheral clock frames */ + writel(13000, &wdt->pulse); - /* Force WDOG_RESET2 and RESOUT_N signal active */ - writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 - | WDTIM_MCTRL_M_RES2, &wdt->mctrl); - } else { - /* Force match output active */ - writel(0x01, &wdt->emr); - - /* Internal reset on match output (no pulse on "RESOUT_N") */ - writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl); - } + /* Force WDOG_RESET2 and RESOUT_N signal active */ + writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2, + &wdt->mctrl); while (1) /* NOP */; diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c index 7f6ce80f37..e501907b53 100644 --- a/arch/arm/mach-mediatek/mt7622/init.c +++ b/arch/arm/mach-mediatek/mt7622/init.c @@ -27,7 +27,7 @@ int dram_init(void) } -void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index c14e7d22e6..b7050dfc39 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -43,7 +43,7 @@ int dram_init_banksize(void) return 0; } -void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *watchdog_dev = NULL; diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 3771152fb3..3460dcc249 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -85,7 +85,7 @@ int mtk_soc_early_init(void) return 0; } -void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c index 28b00c3dec..f7e03de365 100644 --- a/arch/arm/mach-mediatek/mt8518/init.c +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -42,7 +42,7 @@ int dram_init_banksize(void) return 0; } -void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c index 34b3c8f399..1690b6b1e6 100644 --- a/arch/arm/mach-meson/board-common.c +++ b/arch/arm/mach-meson/board-common.c @@ -167,7 +167,7 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) return 0; } -void reset_cpu(ulong addr) +void reset_cpu(void) { struct pt_regs regs; @@ -182,7 +182,7 @@ void reset_cpu(ulong addr) ; } #else -void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 70f76c7d70..0cf60d7cdd 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -314,7 +314,7 @@ int a3700_fdt_fix_pcie_regions(void *blob) return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len); } -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* * Write magic number of 0x1d1e to North Bridge Warm Reset register diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 529dac9059..474327a8e1 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -104,7 +104,7 @@ void enable_caches(void) dcache_enable(); } -void reset_cpu(ulong ignored) +void reset_cpu(void) { u32 reg; diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 7dce11e77f..0b935c46fb 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -42,7 +42,7 @@ void lowlevel_init(void) */ } -void reset_cpu(unsigned long ignored) +void reset_cpu(void) { struct mvebu_system_registers *reg = (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; diff --git a/arch/arm/mach-nexell/Makefile b/arch/arm/mach-nexell/Makefile index 10b3963ed1..dda16dbb8e 100644 --- a/arch/arm/mach-nexell/Makefile +++ b/arch/arm/mach-nexell/Makefile @@ -10,4 +10,3 @@ obj-y += nx_gpio.o obj-y += tieoff.o obj-$(CONFIG_ARCH_S5P4418) += reg-call.o obj-$(CONFIG_ARCH_S5P4418) += nx_sec_reg.o -obj-$(CONFIG_CMD_BOOTL) += cmd_boot_linux.o diff --git a/arch/arm/mach-nexell/cmd_boot_linux.c b/arch/arm/mach-nexell/cmd_boot_linux.c deleted file mode 100644 index 9b38d38ddb..0000000000 --- a/arch/arm/mach-nexell/cmd_boot_linux.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 nexell - * jhkim <jhkim@nexell.co.kr> - */ - -#include <common.h> -#include <bootm.h> -#include <command.h> -#include <environment.h> -#include <errno.h> -#include <image.h> -#include <fdt_support.h> -#include <asm/global_data.h> - -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_CLI_FRAMEWORK) - -DECLARE_GLOBAL_DATA_PTR; - -static bootm_headers_t linux_images; - -static void boot_go_set_os(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[], - bootm_headers_t *images) -{ - char * const img_addr = argv[0]; - - images->os.type = IH_TYPE_KERNEL; - images->os.comp = IH_COMP_NONE; - images->os.os = IH_OS_LINUX; - images->os.load = simple_strtoul(img_addr, NULL, 16); - images->ep = images->os.load; -#if defined(CONFIG_ARM) - images->os.arch = IH_ARCH_ARM; -#elif defined(CONFIG_ARM64) - images->os.arch = IH_ARCH_ARM64; -#else - #error "Not support architecture ..." -#endif - if (!IS_ENABLED(CONFIG_OF_LIBFDT) && !IS_ENABLED(CONFIG_SPL_BUILD)) { - /* set DTB address for linux kernel */ - if (argc > 2) { - unsigned long ft_addr; - - ft_addr = simple_strtol(argv[2], NULL, 16); - images->ft_addr = (char *)ft_addr; - - /* - * if not defined IMAGE_ENABLE_OF_LIBFDT, - * must be set to fdt address - */ - if (!IMAGE_ENABLE_OF_LIBFDT) - gd->bd->bi_boot_params = ft_addr; - - debug("## set ft:%08lx and boot params:%08lx [control of:%s]" - "...\n", ft_addr, gd->bd->bi_boot_params, - IMAGE_ENABLE_OF_LIBFDT ? "on" : "off"); - } - } -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_LMB) -static void boot_start_lmb(bootm_headers_t *images) -{ - ulong mem_start; - phys_size_t mem_size; - - lmb_init(&images->lmb); - - mem_start = getenv_bootm_low(); - mem_size = getenv_bootm_size(); - - lmb_add(&images->lmb, (phys_addr_t)mem_start, mem_size); - - arch_lmb_reserve(&images->lmb); - board_lmb_reserve(&images->lmb); -} -#else -#define lmb_reserve(lmb, base, size) -static inline void boot_start_lmb(bootm_headers_t *images) { } -#endif - -int do_boot_linux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - boot_os_fn *boot_fn; - bootm_headers_t *images = &linux_images; - int flags; - int ret; - - boot_start_lmb(images); - - flags = BOOTM_STATE_START; - - argc--; argv++; - boot_go_set_os(cmdtp, flag, argc, argv, images); - - if (IS_ENABLED(CONFIG_OF_LIBFDT)) { - /* find flattened device tree */ - ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, images, - &images->ft_addr, &images->ft_len); - if (ret) { - puts("Could not find a valid device tree\n"); - return 1; - } - set_working_fdt_addr((ulong)images->ft_addr); - } - - if (!IS_ENABLED(CONFIG_OF_LIBFDT)) - flags |= BOOTM_STATE_OS_GO; - - boot_fn = do_bootm_linux; - ret = boot_fn(flags, argc, argv, images); - - if (ret == BOOTM_ERR_UNIMPLEMENTED) - show_boot_progress(BOOTSTAGE_ID_DECOMP_UNIMPL); - else if (ret == BOOTM_ERR_RESET) - do_reset(cmdtp, flag, argc, argv); - - return ret; -} - -U_BOOT_CMD(bootl, CONFIG_SYS_MAXARGS, 1, do_boot_linux, - "boot linux image from memory", - "[addr [arg ...]]\n - boot linux image stored in memory\n" - "\tuse a '-' for the DTB address\n" -); -#endif - -#if defined(CONFIG_CMD_BOOTD) && !defined(CONFIG_CMD_BOOTM) -int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - return run_command(env_get("bootcmd"), flag); -} - -U_BOOT_CMD(boot, 1, 1, do_bootd, - "boot default, i.e., run 'bootcmd'", - "" -); - -/* keep old command name "bootd" for backward compatibility */ -U_BOOT_CMD(bootd, 1, 1, do_bootd, - "boot default, i.e., run 'bootcmd'", - "" -); -#endif diff --git a/arch/arm/mach-octeontx/cpu.c b/arch/arm/mach-octeontx/cpu.c index ce5f2b42d7..7bd74fe4f6 100644 --- a/arch/arm/mach-octeontx/cpu.c +++ b/arch/arm/mach-octeontx/cpu.c @@ -72,6 +72,6 @@ u64 get_page_table_size(void) return 0x80000; } -void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/arch/arm/mach-octeontx2/cpu.c b/arch/arm/mach-octeontx2/cpu.c index 87868152b7..afa458c09b 100644 --- a/arch/arm/mach-octeontx2/cpu.c +++ b/arch/arm/mach-octeontx2/cpu.c @@ -68,6 +68,6 @@ u64 get_page_table_size(void) return 0x80000; } -void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c index 1b246f844a..36db588243 100644 --- a/arch/arm/mach-omap2/omap-cache.c +++ b/arch/arm/mach-omap2/omap-cache.c @@ -41,9 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK #endif -#define ARMV7_DOMAIN_CLIENT 1 -#define ARMV7_DOMAIN_MASK (0x3 << 0) - void enable_caches(void) { @@ -67,17 +64,3 @@ void dram_bank_mmu_setup(int bank) for (i = start; i < end; i++) set_section_dcache(i, ARMV7_DCACHE_POLICY); } - -void arm_init_domains(void) -{ - u32 reg; - - reg = get_dacr(); - /* - * Set DOMAIN to client access so that all permissions - * set in pagetables are validated by the mmu. - */ - reg &= ~ARMV7_DOMAIN_MASK; - reg |= ARMV7_DOMAIN_CLIENT; - set_dacr(reg); -} diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 47ac8656bf..edab9a9298 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -417,7 +417,7 @@ void omap_die_id(unsigned int *die_id) die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); } -void reset_cpu(ulong ignored) +void reset_cpu(void) { u32 omap_rev = omap_revision(); diff --git a/arch/arm/mach-omap2/reset.c b/arch/arm/mach-omap2/reset.c index 2bbd5fcb9b..1fd79c2e8a 100644 --- a/arch/arm/mach-omap2/reset.c +++ b/arch/arm/mach-omap2/reset.c @@ -14,7 +14,7 @@ #include <asm/arch/cpu.h> #include <linux/compiler.h> -void __weak reset_cpu(unsigned long ignored) +void __weak reset_cpu(void) { writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); } diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index beae7b8484..ffae9a01e3 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -20,7 +20,7 @@ #define BUFLEN 16 -void reset_cpu(unsigned long ignored) +void reset_cpu(void) { struct orion5x_cpu_registers *cpureg = (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 4d2b9d0b0e..4baef2eed3 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -74,7 +74,7 @@ int board_init(void) return 0; } -void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 8c25325e45..1d68034cb5 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -8,7 +8,7 @@ phys_addr_t socfpga_get_rstmgr_addr(void); -void reset_cpu(ulong addr); +void reset_cpu(void); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index bc2db535be..897ec13ad8 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -212,6 +212,35 @@ u32 get_bootmode(void) } /* + * weak function overidde: set the DDR/SYSRAM executable before to enable the + * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc) + */ +void dram_bank_mmu_setup(int bank) +{ + struct bd_info *bd = gd->bd; + int i; + phys_addr_t start; + phys_size_t size; + + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); + size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); + } else if (gd->flags & GD_FLG_RELOC) { + /* bd->bi_dram is available only after relocation */ + start = bd->bi_dram[bank].start; + size = bd->bi_dram[bank].size; + } else { + /* mark cacheable and executable the beggining of the DDR */ + start = STM32_DDR_BASE; + size = CONFIG_DDR_CACHEABLE_SIZE; + } + + for (i = start >> MMU_SECTION_SHIFT; + i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +} +/* * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage * MMU/TLB is updated in enable_caches() for U-Boot after relocation * or is deactivated in U-Boot entry function start.S::cpu_init_cp15 @@ -228,17 +257,8 @@ static void early_enable_caches(void) gd->arch.tlb_addr = (unsigned long)&early_tlb; } + /* enable MMU (default configuration) */ dcache_enable(); - - if (IS_ENABLED(CONFIG_SPL_BUILD)) - mmu_set_region_dcache_behaviour( - ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), - ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), - DCACHE_DEFAULT_OPTION); - else - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, - CONFIG_DDR_CACHEABLE_SIZE, - DCACHE_DEFAULT_OPTION); } /* diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index ad6977fd44..66e81bacca 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -13,6 +13,7 @@ #include <log.h> #include <ram.h> #include <asm/global_data.h> +#include <asm/system.h> DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +42,7 @@ int dram_init(void) ulong board_get_usable_ram_top(ulong total_size) { + phys_size_t size; phys_addr_t reg; struct lmb lmb; @@ -48,10 +50,13 @@ ulong board_get_usable_ram_top(ulong total_size) lmb_init(&lmb); lmb_add(&lmb, gd->ram_base, gd->ram_size); boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); - reg = lmb_alloc(&lmb, CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K); + size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE), + reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE); - if (reg) - return ALIGN(reg + CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K); + if (!reg) + reg = gd->ram_top - size; - return gd->ram_top; + mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); + + return reg + size; } diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 0135575ca1..a29d11505a 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -816,13 +816,14 @@ config VIDEO_SUNXI depends on !MACH_SUN9I depends on !MACH_SUN50I depends on !SUN50I_GEN_H6 - select VIDEO + select DM_VIDEO + select DISPLAY imply VIDEO_DT_SIMPLEFB default y ---help--- - Say Y here to add support for using a cfb console on the HDMI, LCD - or VGA output found on most sunxi devices. See doc/README.video for - info on how to select the video output and mode. + Say Y here to add support for using a graphical console on the HDMI, + LCD or VGA output found on older sunxi devices. This will also provide + a simple_framebuffer device for Linux. config VIDEO_HDMI bool "HDMI output support" diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index fa2b6fcfd6..503538e26d 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -338,7 +338,7 @@ void board_init_f(ulong dummy) } #endif -void reset_cpu(ulong addr) +void reset_cpu(void) { #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) static const struct sunxi_wdog *wdog = diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index 25df31a3b8..92ff6cb1bf 100644 --- a/arch/arm/mach-tegra/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c @@ -40,7 +40,7 @@ static int do_enterrcm(struct cmd_tbl *cmdtp, int flag, int argc, tegra_pmc_writel(2, PMC_SCRATCH0); disable_interrupts(); - reset_cpu(0); + reset_cpu(); return 0; } diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index 93db63e104..8d617bee63 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -85,7 +85,7 @@ void tegra_pmc_writel(u32 value, unsigned long offset) writel(value, NV_PA_PMC_BASE + offset); } -void reset_cpu(ulong addr) +void reset_cpu(void) { u32 value; diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c index a4d260aece..fbb6ebca77 100644 --- a/arch/arm/mach-uniphier/arm32/psci.c +++ b/arch/arm/mach-uniphier/arm32/psci.c @@ -158,5 +158,5 @@ s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point, void __secure psci_system_reset(void) { - reset_cpu(0); + reset_cpu(); } diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c index 5fffd23e9a..dddb48ec4a 100644 --- a/arch/arm/mach-uniphier/reset.c +++ b/arch/arm/mach-uniphier/reset.c @@ -18,7 +18,7 @@ #define __SECURE #endif -void __SECURE reset_cpu(unsigned long ignored) +void __SECURE reset_cpu(void) { u32 tmp; diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 3befc12028..69b818f24b 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -78,7 +78,7 @@ unsigned int zynq_get_silicon_version(void) >> ZYNQ_SILICON_VER_SHIFT; } -void reset_cpu(ulong addr) +void reset_cpu(void) { zynq_slcr_cpu_reset(); while (1) diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c index d841c3a5b3..0d368443d8 100644 --- a/arch/arm/mach-zynqmp-r5/cpu.c +++ b/arch/arm/mach-zynqmp-r5/cpu.c @@ -30,7 +30,7 @@ int arch_cpu_init(void) /* * Perform the low-level reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { while (1) ; |