diff options
Diffstat (limited to 'arch/arm')
48 files changed, 913 insertions, 160 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8a23c76db8..0f8dd32bdd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -646,6 +646,12 @@ config ARCH_KEYSTONE imply CMD_SAVES imply FIT +config ARCH_K3 + bool "Texas Instruments' K3 Architecture" + select SPL + select SUPPORT_SPL + select FIT + config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7A @@ -1266,7 +1272,6 @@ config STM32 select CPU_V7M select DM select DM_SERIAL - select SYS_THUMB_BUILD imply CMD_DM config ARCH_STI @@ -1378,6 +1383,8 @@ source "arch/arm/mach-highbank/Kconfig" source "arch/arm/mach-integrator/Kconfig" +source "arch/arm/mach-k3/Kconfig" + source "arch/arm/mach-keystone/Kconfig" source "arch/arm/mach-kirkwood/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index cac58bdc4d..8f50560434 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -15,7 +15,7 @@ arch-$(CONFIG_CPU_PXA) = arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \ - $(call cc-option, -march=armv7, -march=armv5)) + $(call cc-option, -march=armv7)) arch-$(CONFIG_CPU_V7M) =-march=armv7-m arch-$(CONFIG_CPU_V7R) =-march=armv7-r arch-$(CONFIG_ARM64) =-march=armv8-a @@ -40,7 +40,7 @@ tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100 tune-$(CONFIG_CPU_PXA) =-mcpu=xscale tune-$(CONFIG_CPU_ARM1136) = tune-$(CONFIG_CPU_ARM1176) = -tune-$(CONFIG_CPU_V7A) = +tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a tune-$(CONFIG_CPU_V7R) = tune-$(CONFIG_ARM64) = @@ -58,6 +58,7 @@ machine-$(CONFIG_ARCH_BCMSTB) += bcmstb machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_EXYNOS) += exynos machine-$(CONFIG_ARCH_HIGHBANK) += highbank +machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 3b89391c37..22a55f52e0 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -65,3 +65,26 @@ __weak void l2_cache_disable(void) {} #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) __weak void invalidate_l2_cache(void) {} #endif + +#ifndef CONFIG_SYS_ICACHE_OFF +/* Invalidate entire I-cache and branch predictor array */ +void invalidate_icache_all(void) +{ + unsigned long i = 0; + + asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i)); +} +#else +void invalidate_icache_all(void) {} +#endif + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index e6eef36c0e..2795a5f22e 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -214,14 +214,6 @@ int print_cpuinfo(void) } #endif -void enable_caches(void) -{ -#ifndef CONFIG_SYS_DCACHE_OFF - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -#endif -} - #if defined(CONFIG_FEC_MXC) /* * Initializes on-chip ethernet controllers. diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c index a593283438..08b1b4de71 100644 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ b/arch/arm/cpu/arm926ejs/mx27/generic.c @@ -374,11 +374,3 @@ void mx27_sd2_init_pins(void) } #endif /* CONFIG_MMC_MXC */ - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif /* CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index f42f311cbc..85c65dcb44 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -49,16 +49,6 @@ void reset_cpu(ulong ignored) ; } -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - /* * This function will craft a jumptable at 0x0 which will redirect interrupt * vectoring to proper location of U-Boot in RAM. diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 0970aca2ef..88a40c6036 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -49,22 +49,15 @@ int arch_cpu_init(void) #if defined(CONFIG_USB_EHCI_SPEAR) periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2; #endif +#if defined(CONFIG_SPEAR_GPIO) + periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB; +#endif writel(periph1_clken, &misc_p->periph1_clken); return 0; } -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 31d9256a3e..44ebc50bfa 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \ - at91sam9g20-taurus.dtb \ - at91sam9g45-corvus.dtb \ - at91sam9g45-gurnard.dtb +dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb +dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb +dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb +dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb @@ -552,6 +552,8 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb +dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/at91-vinco.dts b/arch/arm/dts/at91-vinco.dts index ff6d2e3205..0ecb64e718 100644 --- a/arch/arm/dts/at91-vinco.dts +++ b/arch/arm/dts/at91-vinco.dts @@ -152,6 +152,8 @@ }; tcb2: timer@fc024000 { + #address-cells = <1>; + #size-cells = <0>; timer@0 { compatible = "atmel,tcb-timer"; reg = <0>; diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi index 69d9ceadaf..476ad1dad2 100644 --- a/arch/arm/dts/at91sam9260.dtsi +++ b/arch/arm/dts/at91sam9260.dtsi @@ -37,9 +37,6 @@ spi0 = &spi0; }; cpus { - #address-cells = <0>; - #size-cells = <0>; - cpu { compatible = "arm,arm926ej-s"; device_type = "cpu"; diff --git a/arch/arm/dts/at91sam9261.dtsi b/arch/arm/dts/at91sam9261.dtsi index 69c2d6e416..b6357d3cb3 100644 --- a/arch/arm/dts/at91sam9261.dtsi +++ b/arch/arm/dts/at91sam9261.dtsi @@ -34,9 +34,6 @@ }; cpus { - #address-cells = <0>; - #size-cells = <0>; - cpu { compatible = "arm,arm926ej-s"; device_type = "cpu"; diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi index 0b594be221..61b056266b 100644 --- a/arch/arm/dts/at91sam9263.dtsi +++ b/arch/arm/dts/at91sam9263.dtsi @@ -36,9 +36,6 @@ }; cpus { - #address-cells = <0>; - #size-cells = <0>; - cpu { compatible = "arm,arm926ej-s"; device_type = "cpu"; diff --git a/arch/arm/dts/at91sam9g45.dtsi b/arch/arm/dts/at91sam9g45.dtsi index 1be1270c57..c9b2e4698b 100644 --- a/arch/arm/dts/at91sam9g45.dtsi +++ b/arch/arm/dts/at91sam9g45.dtsi @@ -41,9 +41,6 @@ pwm0 = &pwm0; }; cpus { - #address-cells = <0>; - #size-cells = <0>; - cpu { compatible = "arm,arm926ej-s"; device_type = "cpu"; @@ -1042,8 +1039,6 @@ }; adc0: adc@fffb0000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9g45-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; @@ -1086,10 +1081,6 @@ clocks = <&isi_clk>; clock-names = "isi_clk"; status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; }; pwm0: pwm@fffb8000 { diff --git a/arch/arm/dts/at91sam9n12.dtsi b/arch/arm/dts/at91sam9n12.dtsi index 7ba7116e8f..024be13dab 100644 --- a/arch/arm/dts/at91sam9n12.dtsi +++ b/arch/arm/dts/at91sam9n12.dtsi @@ -38,9 +38,6 @@ spi0 = &spi0; }; cpus { - #address-cells = <0>; - #size-cells = <0>; - cpu { compatible = "arm,arm926ej-s"; device_type = "cpu"; diff --git a/arch/arm/dts/at91sam9rl.dtsi b/arch/arm/dts/at91sam9rl.dtsi index 4602cd21e1..6d6aee5524 100644 --- a/arch/arm/dts/at91sam9rl.dtsi +++ b/arch/arm/dts/at91sam9rl.dtsi @@ -38,9 +38,6 @@ }; cpus { - #address-cells = <0>; - #size-cells = <0>; - cpu { compatible = "arm,arm926ej-s"; device_type = "cpu"; @@ -253,8 +250,6 @@ }; adc0: adc@fffd0000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9rl-adc"; reg = <0xfffd0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi index a422c98706..ea319cc18b 100644 --- a/arch/arm/dts/at91sam9x5.dtsi +++ b/arch/arm/dts/at91sam9x5.dtsi @@ -41,9 +41,6 @@ }; cpus { - #address-cells = <0>; - #size-cells = <0>; - cpu { compatible = "arm,arm926ej-s"; device_type = "cpu"; @@ -1048,8 +1045,6 @@ }; adc0: adc@f804c000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9x5-adc"; reg = <0xf804c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi new file mode 100644 index 0000000000..2409344df4 --- /dev/null +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family Main Domain peripherals + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x01800000 0x10000>, /* GICD */ + <0x01880000 0x90000>; /* GICR */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: gic-its@18200000 { + compatible = "arm,gic-v3-its"; + reg = <0x01820000 0x10000>; + msi-controller; + #msi-cells = <1>; + }; + }; +}; diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi new file mode 100644 index 0000000000..cede1fa098 --- /dev/null +++ b/arch/arm/dts/k3-am65.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Texas Instruments K3 AM654 SoC"; + compatible = "ti,am654"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + cbass_main: interconnect@100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */ + <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */ + <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */ + <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */ + <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */ + /* MCUSS Range */ + <0x28380000 0x00 0x28380000 0x03880000>, + <0x40200000 0x00 0x40200000 0x00900100>, + <0x42040000 0x00 0x42040000 0x03ac2400>, + <0x45100000 0x00 0x45100000 0x00c24000>, + <0x46000000 0x00 0x46000000 0x00200000>, + <0x47000000 0x00 0x47000000 0x00068400>; + + cbass_mcu: interconnect@28380000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/ + <0x40200000 0x40200000 0x00900100>, /* First peripheral window */ + <0x42040000 0x42040000 0x03ac2400>, /* WKUP */ + <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x46000000 0x46000000 0x00200000>, /* CPSW */ + <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */ + + cbass_wakeup: interconnect@42040000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* WKUP Basic peripherals */ + ranges = <0x42040000 0x42040000 0x03ac2400>; + }; + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am65-main.dtsi" diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi new file mode 100644 index 0000000000..d4ecb3be10 --- /dev/null +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/pinctrl/k3-am65.h> + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + serial2 = &main_uart0; + }; +}; + +&cbass_main{ + u-boot,dm-spl; + secure_proxy: secure_proxy@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x32c00000 0x100000>, + <0x32400000 0x100000>, + <0x32800000 0x100000>; + interrupt-names = "rx_011"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + }; + + dmsc: dmsc { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* + * In case of rare platforms that does not use am6 as + * system master, use /delete-property/ + */ + ti,system-reboot-controller; + mbox-names = "rx", "tx"; + + mboxes= <&secure_proxy 11>, + <&secure_proxy 13>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <1>; + }; + + k3_clks: clocks { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + }; + }; + + main_pmx0: pinmux@11c000 { + compatible = "pinctrl-single"; + reg = <0x11c000 0x2e4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_pmx1: pinmux@11c2e8 { + compatible = "pinctrl-single"; + reg = <0x11c2e8 0x24>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am654-uart", "ti,omap4-uart", "ns16550a"; + reg = <0x02800000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + sdhci0: sdhci@04F80000 { + compatible = "arasan,sdhci-5.1"; + reg = <0x4F80000 0x1000>, + <0x4F90000 0x400>; + clocks = <&k3_clks 47 1>; + power-domains = <&k3_pds 47>; + max-frequency = <25000000>; + }; + + sdhci1: sdhci@04FA0000 { + compatible = "arasan,sdhci-5.1"; + reg = <0x4FA0000 0x1000>, + <0x4FB0000 0x400>; + clocks = <&k3_clks 48 1>; + power-domains = <&k3_pds 48>; + max-frequency = <25000000>; + }; + +}; + +&secure_proxy { + u-boot,dm-spl; +}; + +&dmsc { + u-boot,dm-spl; +}; + +&k3_pds { + u-boot,dm-spl; +}; + +&k3_clks { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&main_pmx0 { + u-boot,dm-spl; + main_uart0_pins_default: main_uart0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01e4, PIN_INPUT | MUX_MODE0) /* (AF11) UART0_RXD */ + AM65X_IOPAD(0x01e8, PIN_OUTPUT | MUX_MODE0) /* (AE11) UART0_TXD */ + AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */ + AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */ + >; + }; + + main_mmc0_pins_default: main_mmc0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B25) MMC0_CLK */ + AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP | MUX_MODE0) /* (B27) MMC0_CMD */ + AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* (A26) MMC0_DAT0 */ + AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP | MUX_MODE0) /* (E25) MMC0_DAT1 */ + AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C26) MMC0_DAT2 */ + AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP | MUX_MODE0) /* (A25) MMC0_DAT3 */ + AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP | MUX_MODE0) /* (E24) MMC0_DAT4 */ + AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP | MUX_MODE0) /* (A24) MMC0_DAT5 */ + AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP | MUX_MODE0) /* (B26) MMC0_DAT6 */ + AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */ + AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */ + >; + }; + + main_mmc1_pins_default: main_mmc1_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (C27) MMC1_CLK */ + AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP | MUX_MODE0) /* (C28) MMC1_CMD */ + AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP | MUX_MODE0) /* (D28) MMC1_DAT0 */ + AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP | MUX_MODE0) /* (E27) MMC1_DAT1 */ + AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP | MUX_MODE0) /* (D26) MMC1_DAT2 */ + AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP | MUX_MODE0) /* (D27) MMC1_DAT3 */ + AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */ + AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */ + >; + }; + +}; + +&main_pmx1 { + u-boot,dm-spl; +}; + +&main_uart0 { + u-boot,dm-spl; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&sdhci0 { + u-boot,dm-spl; + status = "okay"; + non-removable; + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; +}; + +&sdhci1 { + u-boot,dm-spl; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + sdhci-caps-mask = <0x7 0x0>; +}; diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts new file mode 100644 index 0000000000..af6956fdc1 --- /dev/null +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am654.dtsi" + +/ { + compatible = "ti,am654-evm", "ti,am654"; + model = "Texas Instruments AM654 Base Board"; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + secure_ddr: secure_ddr@9e800000 { + reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; +}; diff --git a/arch/arm/dts/k3-am654.dtsi b/arch/arm/dts/k3-am654.dtsi new file mode 100644 index 0000000000..2affa6f661 --- /dev/null +++ b/arch/arm/dts/k3-am654.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC family in Quad core configuration + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "k3-am65.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + + cpu3: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + L2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + }; +}; diff --git a/arch/arm/dts/sama5d27_som1.dtsi b/arch/arm/dts/sama5d27_som1.dtsi index 0c44a97f64..9efcf635ad 100644 --- a/arch/arm/dts/sama5d27_som1.dtsi +++ b/arch/arm/dts/sama5d27_som1.dtsi @@ -55,7 +55,6 @@ aliases { spi0 = &qspi1; - u-boot,dm-pre-reloc; }; ahb { diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi index ee0e14e516..ba707b0ddf 100644 --- a/arch/arm/dts/sama5d3.dtsi +++ b/arch/arm/dts/sama5d3.dtsi @@ -238,10 +238,6 @@ clocks = <&isi_clk>; clock-names = "isi_clk"; status = "disabled"; - port { - #address-cells = <1>; - #size-cells = <0>; - }; }; sfr: sfr@f0038000 { diff --git a/arch/arm/dts/sama5d3xmb_cmp.dtsi b/arch/arm/dts/sama5d3xmb_cmp.dtsi index 77f989ce3c..9792b2a9d0 100644 --- a/arch/arm/dts/sama5d3xmb_cmp.dtsi +++ b/arch/arm/dts/sama5d3xmb_cmp.dtsi @@ -221,8 +221,6 @@ compatible = "gpio-keys"; status = "okay"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; diff --git a/arch/arm/dts/usb_a9263.dts b/arch/arm/dts/usb_a9263.dts index bfc48a2724..9adc12af31 100644 --- a/arch/arm/dts/usb_a9263.dts +++ b/arch/arm/dts/usb_a9263.dts @@ -127,8 +127,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; user_pb { label = "user_pb"; diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index c906730699..65063fca51 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -144,6 +144,7 @@ struct misc_regs { #define MISC_USBDENB 0x01000000 #define MISC_ETHENB 0x00800000 #define MISC_SMIENB 0x00200000 +#define MISC_GPIO3ENB 0x00040000 #define MISC_GPT3ENB 0x00010000 #define MISC_GPIO4ENB 0x00002000 #define MISC_GPT2ENB 0x00000800 diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index 278f302cdb..ad67b4fa34 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -10,11 +10,6 @@ #ifndef ARMV7M_H #define ARMV7M_H -#if defined(__ASSEMBLY__) -.syntax unified -.thumb -#endif - /* armv7m fixed base addresses */ #define V7M_SCS_BASE 0xE000E000 #define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100) diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 1c5e87340c..3039e66bf9 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,4 +1,5 @@ -#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) +#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ + !defined(CONFIG_ARCH_K3) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index b9e8a4f5d5..e568af2561 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -8,7 +8,7 @@ #if defined(CONFIG_ARCH_OMAP2PLUS) \ || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ - || defined(CONFIG_EXYNOS4210) + || defined(CONFIG_EXYNOS4210) || defined(CONFIG_ARCH_K3) /* Platform-specific defines */ #include <asm/arch/spl.h> diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index 9af7353f08..900b2619a4 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -1,44 +1,15 @@ #ifndef __ASM_ARM_TYPES_H #define __ASM_ARM_TYPES_H -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; +#include <asm-generic/int-ll64.h> -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif +typedef unsigned short umode_t; /* * These aren't exported outside the kernel to avoid name space clashes */ #ifdef __KERNEL__ -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - #ifdef CONFIG_ARM64 #define BITS_PER_LONG 64 #else /* CONFIG_ARM64 */ diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 0decce2c5b..fe312db690 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -8,9 +8,7 @@ #include <config.h> #include <asm-offsets.h> #include <linux/linkage.h> -#ifdef CONFIG_CPU_V7M -#include <asm/armv7m.h> -#endif +#include <asm/assembler.h> /* * This file handles the target-independent stages of the U-Boot @@ -139,9 +137,6 @@ here: mov r2, #0x00000000 /* prepare zero to clear BSS */ clbss_l:cmp r0, r1 /* while not at end of BSS */ -#if defined(CONFIG_CPU_V7M) - itt lo -#endif strlo r2, [r0] /* clear 32-bit BSS word */ addlo r0, r0, #4 /* move to next */ blo clbss_l diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index c5b135db40..e5f7267be1 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -6,6 +6,7 @@ */ #include <asm-offsets.h> +#include <asm/assembler.h> #include <config.h> #include <elf.h> #include <linux/linkage.h> diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index d629cb1dc2..2ca6e2494a 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -19,7 +19,11 @@ * for the non-boot0 case or by a boot0-header. */ .macro ARM_VECTORS +#ifdef CONFIG_ARCH_K3 + ldr pc, _reset +#else b reset +#endif ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -94,6 +98,7 @@ _start: ************************************************************************* */ + .globl _reset .globl _undefined_instruction .globl _software_interrupt .globl _prefetch_abort @@ -102,6 +107,9 @@ _start: .globl _irq .globl _fiq +#ifdef CONFIG_ARCH_K3 +_reset: .word reset +#endif _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort diff --git a/arch/arm/lib/vectors_m.S b/arch/arm/lib/vectors_m.S index d75e47734b..7d2d55c7f9 100644 --- a/arch/arm/lib/vectors_m.S +++ b/arch/arm/lib/vectors_m.S @@ -5,7 +5,7 @@ */ #include <config.h> -#include <asm/armv7m.h> +#include <asm/assembler.h> #include <linux/linkage.h> .type __hard_fault_entry, %function diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index a8a49ca43f..0639d7ea1e 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o obj-$(CONFIG_AT91_EFLASH) += eflash.o obj-$(CONFIG_AT91_LED) += led.o -obj-y += cache.o obj-y += clock.o obj-y += cpu.o obj-y += reset.o diff --git a/arch/arm/mach-at91/arm926ejs/cache.c b/arch/arm/mach-at91/arm926ejs/cache.c deleted file mode 100644 index 024c8f5f3e..0000000000 --- a/arch/arm/mach-at91/arm926ejs/cache.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -#include <linux/types.h> -#include <common.h> - -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -} - -#ifndef CONFIG_SYS_ICACHE_OFF -/* Invalidate entire I-cache and branch predictor array */ -void invalidate_icache_all(void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i)); -} -#else -void invalidate_icache_all(void) -{ -} -#endif diff --git a/arch/arm/mach-bcmstb/Kconfig b/arch/arm/mach-bcmstb/Kconfig index 6c7952ffe5..0a56c3c7fa 100644 --- a/arch/arm/mach-bcmstb/Kconfig +++ b/arch/arm/mach-bcmstb/Kconfig @@ -7,8 +7,14 @@ config TARGET_BCM7445 Support for the Broadcom 7445 SoC. This port assumes BOLT is acting as the second stage bootloader, and U-Boot is acting as the third stage bootloader (TSBL), loaded by BOLT. - This port may work on other BCM7xxx boards with - configuration changes. + +config TARGET_BCM7260 + bool "Broadcom 7260 TSBL" + depends on ARCH_BCMSTB + help + Support for the Broadcom 7260 SoC. This port assumes BOLT + is acting as the second stage bootloader, and U-Boot is + acting as the third stage bootloader (TSBL), loaded by BOLT. config SYS_CPU default "armv7" @@ -23,7 +29,8 @@ config SYS_SOC default "bcmstb" config SYS_CONFIG_NAME - default "bcm7445" + default "bcm7445" if TARGET_BCM7445 + default "bcm7260" if TARGET_BCM7260 config SYS_FDT_SAVE_ADDRESS hex "Address to which the prior stage provided DTB will be copied" diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig new file mode 100644 index 0000000000..2df6197af7 --- /dev/null +++ b/arch/arm/mach-k3/Kconfig @@ -0,0 +1,51 @@ +if ARCH_K3 + +choice + prompt "Texas Instruments' K3 based SoC select" + optional + +config SOC_K3_AM6 + bool "TI's K3 based AM6 SoC Family Support" + +endchoice + +config SYS_SOC + default "k3" + +config SYS_K3_NON_SECURE_MSRAM_SIZE + hex + default 0x80000 + help + Describes the total size of the MCU MSRAM. This doesn't + specify the total size of SPL as ROM can use some part + of this RAM. Once ROM gives control to SPL then this + complete size can be usable. + +config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE + hex + default 0x58000 + help + Describes the maximum size of the image that ROM can download + from any boot media. + +config SYS_K3_MCU_SCRATCHPAD_BASE + hex + default 0x40280000 if SOC_K3_AM6 + help + Describes the base address of MCU Scratchpad RAM. + +config SYS_K3_MCU_SCRATCHPAD_SIZE + hex + default 0x200 if SOC_K3_AM6 + help + Describes the size of MCU Scratchpad RAM. + +config SYS_K3_BOOT_PARAM_TABLE_INDEX + hex + default 0x41c7fbfc if SOC_K3_AM6 + help + Address at which ROM stores the value which determines if SPL + is booted up by primary boot media or secondary boot media. + +source "board/ti/am65x/Kconfig" +endif diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile new file mode 100644 index 0000000000..e9b7ee5210 --- /dev/null +++ b/arch/arm/mach-k3/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +# Lokesh Vutla <lokeshvutla@ti.com> + +obj-$(CONFIG_SOC_K3_AM6) += am6_init.o +obj-$(CONFIG_ARM64) += arm64-mmu.o diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c new file mode 100644 index 0000000000..8a3a99f23a --- /dev/null +++ b/arch/arm/mach-k3/am6_init.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * K3: Architecture initialization + * + * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <spl.h> +#include <asm/arch/hardware.h> + +#ifdef CONFIG_SPL_BUILD +static void mmr_unlock(u32 base, u32 partition) +{ + /* Translate the base address */ + phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE; + + /* Unlock the requested partition if locked using two-step sequence */ + writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0); + writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1); +} + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 3); + mmr_unlock(CTRL_MMR0_BASE, 6); + mmr_unlock(CTRL_MMR0_BASE, 7); +} + +static void store_boot_index_from_rom(void) +{ + u32 *boot_index = (u32 *)K3_BOOT_PARAM_TABLE_INDEX_VAL; + + *boot_index = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); +} + +void board_init_f(ulong dummy) +{ + /* + * Cannot delay this further as there is a chance that + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. + */ + store_boot_index_from_rom(); + + /* Make all control module registers accessible */ + ctrl_mmr_unlock(); + + /* Init DM early in-order to invoke system controller */ + spl_early_init(); + + /* Prepare console output */ + preloader_console_init(); +} + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >> + CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT; + + switch (bkup_boot) { + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + case BACKUP_BOOT_DEVICE_MMC2: + return BOOT_DEVICE_MMC2; + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + case BACKUP_BOOT_DEVICE_HYPERFLASH: + return BOOT_DEVICE_HYPERFLASH; + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK; + + if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI) + bootmode = BOOT_DEVICE_SPI; + + return bootmode; +} + +u32 spl_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootindex = readl(K3_BOOT_PARAM_TABLE_INDEX_VAL); + + if (bootindex == K3_PRIMARY_BOOTMODE) + return __get_primary_bootmedia(devstat); + else + return __get_backup_bootmedia(devstat); +} +#endif + +#ifndef CONFIG_SYSRESET +void reset_cpu(ulong ignored) +{ +} +#endif diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c new file mode 100644 index 0000000000..f8b93fe458 --- /dev/null +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * K3: ARM64 MMU setup + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + * (This file is derived from arch/arm/cpu/armv8/zynqmp/cpu.c) + * + */ + +#include <common.h> +#include <asm/system.h> +#include <asm/armv8/mmu.h> + +/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) + +/* ToDo: Add 64bit IO */ +struct mm_region am654_mem_map[NR_MMU_REGIONS] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = am654_mem_map; diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk new file mode 100644 index 0000000000..9b86ddc715 --- /dev/null +++ b/arch/arm/mach-k3/config.mk @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +# Lokesh Vutla <lokeshvutla@ti.com> + +ifdef CONFIG_SPL_BUILD + +ifdef CONFIG_ARM64 +SPL_ITS := u-boot-spl-k3.its +$(SPL_ITS): FORCE + $(srctree)/tools/k3_fit_atf.sh \ + $(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(CONFIG_SPL_OF_LIST))) > $@ + +ALL-y += tispl.bin +endif + +else +ALL-y += u-boot.img +endif diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h new file mode 100644 index 0000000000..e4b78f8617 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: AM6 SoC definitions, structures etc. + * + * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ +#ifndef __ASM_ARCH_AM6_HARDWARE_H +#define __ASM_ARCH_AM6_HARDWARE_H + +#include <config.h> + +#define CTRL_MMR0_BASE 0x00100000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) + +#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0) +#define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0 +#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4) +#define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 4 + +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism + * shared register definitions. + */ +#define CTRLMMR_LOCK_KICK0 0x01008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) +#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 +#define CTRLMMR_LOCK_KICK1 0x0100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +/* MCU SCRATCHPAD usage */ +#define K3_BOOT_PARAM_TABLE_INDEX_VAL CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE + +#endif /* __ASM_ARCH_AM6_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am6_spl.h b/arch/arm/mach-k3/include/mach/am6_spl.h new file mode 100644 index 0000000000..e97d8143c6 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am6_spl.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + */ +#ifndef _ASM_ARCH_AM6_SPL_H_ +#define _ASM_ARCH_AM6_SPL_H_ + +#define BOOT_DEVICE_RAM 0x00 +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_HYPERFLASH 0x03 +#define BOOT_DEVICE_SPI 0x04 +#define BOOT_DEVICE_I2C 0x05 +#define BOOT_DEVICE_MMC2 0x06 +#define BOOT_DEVICE_ETHERNET 0x07 +#define BOOT_DEVICE_USB 0x08 +#define BOOT_DEVICE_PCIE 0x09 +#define BOOT_DEVICE_UART 0x0a +#define BOOT_DEVICE_NAND 0x0c +#define BOOT_DEVICE_MMC1 0x0d +#define BOOT_DEVICE_MMC2_2 0x0e + +#define BACKUP_BOOT_DEVICE_RAM 0x0 +#define BACKUP_BOOT_DEVICE_USB 0x1 +#define BACKUP_BOOT_DEVICE_UART 0x2 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x3 +#define BACKUP_BOOT_DEVICE_MMC2 0x4 +#define BACKUP_BOOT_DEVICE_SPI 0x5 +#define BACKUP_BOOT_DEVICE_HYPERFLASH 0x6 +#define BACKUP_BOOT_DEVICE_I2C 0x7 + +#define K3_PRIMARY_BOOTMODE 0x0 +#define K3_BACKUP_BOOTMODE 0x1 + +#endif diff --git a/arch/arm/mach-k3/include/mach/clock.h b/arch/arm/mach-k3/include/mach/clock.h new file mode 100644 index 0000000000..e3adbcd9de --- /dev/null +++ b/arch/arm/mach-k3/include/mach/clock.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: Common SoC clock definitions. + * + * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#include <config.h> + +/* Clock Defines */ +#define V_OSCK 24000000 +#define V_SCLK V_OSCK + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h new file mode 100644 index 0000000000..b39f780d26 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + */ +#ifndef _ASM_ARCH_HARDWARE_H_ +#define _ASM_ARCH_HARDWARE_H_ + +#ifdef CONFIG_SOC_K3_AM6 +#include "am6_hardware.h" +#endif +#endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h new file mode 100644 index 0000000000..2d435aec17 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#ifdef CONFIG_SOC_K3_AM6 +#include "am6_spl.h" +#endif +#endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S index e6e907d11f..2a05b5e521 100644 --- a/arch/arm/mach-omap2/omap3/lowlevel_init.S +++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S @@ -21,6 +21,7 @@ * R0 - Service ID * R1 - paramer list */ +/* TODO: Re-evaluate the comment at the end regarding armv5 vs armv7 */ ENTRY(do_omap3_emu_romcode_call) PUSH {r4-r12, lr} @ Save all registers from ROM code! MOV r12, r0 @ Copy the Secure Service ID in R12 |