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-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig71
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c38
-rw-r--r--arch/powerpc/cpu/mpc86xx/speed.c15
3 files changed, 76 insertions, 48 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 38ea4c1440..592b58171a 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -374,6 +374,7 @@ config ARCH_B4420
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_B4860
bool
@@ -398,6 +399,7 @@ config ARCH_B4860
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_BSC9131
bool
@@ -410,6 +412,7 @@ config ARCH_BSC9131
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_IFC
config ARCH_BSC9132
bool
@@ -426,6 +429,7 @@ config ARCH_BSC9132
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_IFC
config ARCH_C29X
bool
@@ -438,6 +442,7 @@ config ARCH_C29X
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_6
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_IFC
config ARCH_MPC8536
bool
@@ -450,6 +455,7 @@ config ARCH_MPC8536
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_MPC8540
bool
@@ -473,6 +479,7 @@ config ARCH_MPC8544
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_MPC8548
bool
@@ -519,6 +526,7 @@ config ARCH_MPC8569
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
+ select FSL_ELBC
config ARCH_MPC8572
bool
@@ -533,6 +541,7 @@ config ARCH_MPC8572
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1010
bool
@@ -553,6 +562,7 @@ config ARCH_P1010
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_IFC
config ARCH_P1011
bool
@@ -566,6 +576,7 @@ config ARCH_P1011
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1020
bool
@@ -579,6 +590,7 @@ config ARCH_P1020
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1021
bool
@@ -592,6 +604,7 @@ config ARCH_P1021
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1022
bool
@@ -607,6 +620,7 @@ config ARCH_P1022
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1023
bool
@@ -618,6 +632,7 @@ config ARCH_P1023
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P1024
bool
@@ -631,6 +646,7 @@ config ARCH_P1024
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P1025
bool
@@ -644,6 +660,7 @@ config ARCH_P1025
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P2020
bool
@@ -658,6 +675,7 @@ config ARCH_P2020
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
+ select FSL_ELBC
config ARCH_P2041
bool
@@ -679,6 +697,7 @@ config ARCH_P2041
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P3041
bool
@@ -702,6 +721,7 @@ config ARCH_P3041
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P4080
bool
@@ -736,6 +756,7 @@ config ARCH_P4080
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select FSL_ELBC
config ARCH_P5020
bool
@@ -756,6 +777,7 @@ config ARCH_P5020
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_ELBC
config ARCH_P5040
bool
@@ -776,6 +798,7 @@ config ARCH_P5040
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_ELBC
config ARCH_QEMU_E500
bool
@@ -795,6 +818,7 @@ config ARCH_T1023
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select FSL_IFC
config ARCH_T1024
bool
@@ -811,6 +835,7 @@ config ARCH_T1024
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select FSL_IFC
config ARCH_T1040
bool
@@ -828,6 +853,7 @@ config ARCH_T1040
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select FSL_IFC
config ARCH_T1042
bool
@@ -845,6 +871,7 @@ config ARCH_T1042
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select FSL_IFC
config ARCH_T2080
bool
@@ -866,6 +893,7 @@ config ARCH_T2080
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_T2081
bool
@@ -885,6 +913,7 @@ config ARCH_T2081
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_T4160
bool
@@ -905,6 +934,7 @@ config ARCH_T4160
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config ARCH_T4240
bool
@@ -928,6 +958,7 @@ config ARCH_T4240
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
+ select FSL_IFC
config BOOKE
bool
@@ -1260,6 +1291,12 @@ config SYS_PPC64
config SYS_PPC_E500_USE_DEBUG_TLB
bool
+config FSL_IFC
+ bool
+
+config FSL_ELBC
+ bool
+
config SYS_PPC_E500_DEBUG_TLB
int "Temporary TLB entry for external debugger"
depends on SYS_PPC_E500_USE_DEBUG_TLB
@@ -1284,6 +1321,40 @@ config SYS_PPC_E500_DEBUG_TLB
symbol should be set to the TLB1 entry to be used for this
purpose. If unsure, do not change.
+config SYS_FSL_IFC_CLK_DIV
+ int "Divider of platform clock"
+ depends on FSL_IFC
+ default 2 if ARCH_B4420 || \
+ ARCH_B4860 || \
+ ARCH_T1024 || \
+ ARCH_T1023 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T4160 || \
+ ARCH_T4240
+ default 1
+ help
+ Defines divider of platform clock(clock input to
+ IFC controller).
+
+config SYS_FSL_LBC_CLK_DIV
+ int "Divider of platform clock"
+ depends on FSL_ELBC || ARCH_MPC8540 || \
+ ARCH_MPC8548 || ARCH_MPC8541 || \
+ ARCH_MPC8555 || ARCH_MPC8560 || \
+ ARCH_MPC8568
+
+ default 2 if ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040
+ default 1
+
+ help
+ Defines divider of platform clock(clock input to
+ eLBC controller).
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index fcf5d92af5..cb8281e19e 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(sys_info_t *sys_info)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
- struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
- u32 ccr;
-#endif
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
@@ -611,39 +607,13 @@ void get_sys_info(sys_info_t *sys_info)
#endif /* CONFIG_FSL_CORENET */
#if defined(CONFIG_FSL_LBC)
- uint lcrr_div;
-#if defined(CONFIG_SYS_LBC_LCRR)
- /* We will program LCRR to this value later */
- lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
- lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
-#endif
- if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if defined(CONFIG_FSL_CORENET)
- /* If this is corenet based SoC, bit-representation
- * for four times the clock divider values.
- */
- lcrr_div *= 4;
-#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
- !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
- /*
- * Yes, the entire PQ38 family use the same
- * bit-representation for twice the clock divider values.
- */
- lcrr_div *= 2;
-#endif
- sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
- } else {
- /* In case anyone cares what the unknown value is */
- sys_info->freq_localbus = lcrr_div;
- }
+ sys_info->freq_localbus = sys_info->freq_systembus /
+ CONFIG_SYS_FSL_LBC_CLK_DIV;
#endif
#if defined(CONFIG_FSL_IFC)
- ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
- ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
- sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+ sys_info->freq_localbus = sys_info->freq_systembus /
+ CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif
}
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index 05f23db457..51b47b823b 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -24,7 +24,6 @@ void get_sys_info(sys_info_t *sys_info)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint plat_ratio, e600_ratio;
- uint lcrr_div;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
@@ -78,19 +77,7 @@ void get_sys_info(sys_info_t *sys_info)
break;
}
-#if defined(CONFIG_SYS_LBC_LCRR)
- /* We will program LCRR to this value later */
- lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
- lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
-#endif
- if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
- sys_info->freq_localbus = sys_info->freq_systembus
- / (lcrr_div * 2);
- } else {
- /* In case anyone cares what the unknown value is */
- sys_info->freq_localbus = lcrr_div;
- }
+ sys_info->freq_localbus = sys_info->freq_systembus;
}
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