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-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig10
-rw-r--r--arch/powerpc/cpu/mpc83xx/Makefile2
-rw-r--r--arch/powerpc/cpu/mpc83xx/ecc.c2
-rw-r--r--arch/powerpc/cpu/mpc83xx/pcie.c144
-rw-r--r--arch/powerpc/cpu/mpc83xx/spd_sdram.c10
-rw-r--r--arch/powerpc/cpu/mpc83xx/start.S7
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig16
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile1
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c8
-rw-r--r--arch/powerpc/cpu/mpc85xx/ether_fcc.c462
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c9
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S5
-rw-r--r--arch/powerpc/cpu/mpc8xx/Kconfig2
-rw-r--r--arch/powerpc/cpu/mpc8xx/start.S4
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c4
-rw-r--r--arch/powerpc/include/asm/cache.h7
-rw-r--r--arch/powerpc/include/asm/config.h9
-rw-r--r--arch/powerpc/include/asm/processor.h4
-rw-r--r--arch/powerpc/lib/bootm.c18
19 files changed, 39 insertions, 685 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 083febe5bb..fcf4ef2b36 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -119,7 +119,7 @@ config MPC83XX_PCIE2_SUPPORT
config MPC83XX_SDHC_SUPPORT
bool
-config MPC83XX_SATA_SUPPORT
+config MPC83XX_SATA
bool
config MPC83XX_SECOND_I2C
@@ -131,6 +131,7 @@ config MPC83XX_LDP_PIN
config ARCH_MPC830X
bool
select MPC83XX_SDHC_SUPPORT
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC8308
bool
@@ -154,6 +155,7 @@ config ARCH_MPC831X
select MPC83XX_PCI_SUPPORT
select MPC83XX_TSEC1_SUPPORT
select MPC83XX_TSEC2_SUPPORT
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC8313
bool
@@ -165,9 +167,11 @@ config ARCH_MPC832X
bool
select MPC83XX_QUICC_ENGINE
select MPC83XX_PCI_SUPPORT
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC834X
bool
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC8349
bool
@@ -184,6 +188,7 @@ config ARCH_MPC8360
select MPC83XX_PCI_SUPPORT
select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC837X
bool
@@ -193,9 +198,10 @@ config ARCH_MPC837X
select MPC83XX_PCIE1_SUPPORT
select MPC83XX_PCIE2_SUPPORT
select MPC83XX_SDHC_SUPPORT
- select MPC83XX_SATA_SUPPORT
+ select MPC83XX_SATA
select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C
+ select SYS_CACHE_SHIFT_5
select FSL_ELBC
config SYS_IMMR
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index aeb42b109d..7c4ef7657e 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -26,7 +26,7 @@ obj-y += cpu.o
obj-y += cpu_init.o
obj-y += speed.o
obj-y += interrupts.o
-obj-y += ecc.o
+obj-$(CONFIG_DDR_ECC_CMD) += ecc.o
ifndef CONFIG_PINCTRL
obj-$(CONFIG_QE) += qe_io.o
endif
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index 7a8ec7f42f..3e24752e2f 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -11,7 +11,6 @@
#include <mpc83xx.h>
#include <command.h>
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
void ecc_print_status(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
@@ -386,4 +385,3 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc,
" - writes pattern injecting errors with word access\n"
" - writes pattern with word access, generates error\n"
" - disables injects\n" " - re-inits memory");
-#endif
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 84797c871c..c386e4ed3f 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -34,148 +34,6 @@ static struct {
#endif
};
-#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
-
-/* private structure for mpc83xx pcie hose */
-static struct mpc83xx_pcie_priv {
- u8 index;
-} pcie_priv[PCIE_MAX_BUSES] = {
- {
- /* pcie controller 1 */
- .index = 0,
- },
- {
- /* pcie controller 2 */
- .index = 1,
- },
-};
-
-static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
-{
- int bus = PCI_BUS(dev) - hose->first_busno;
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
- pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
- struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
- u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
- u32 dev_base = bus << 24 | devfn << 16;
-
- if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
- return -1;
- /*
- * Workaround for the HW bug: for Type 0 configure transactions the
- * PCI-E controller does not check the device number bits and just
- * assumes that the device number bits are 0.
- */
- if (devfn & 0xf8)
- return -1;
-
- out_le32(&out_win->tarl, dev_base);
- return 0;
-}
-
-#define cfg_read(val, addr, type, op) \
- do { *val = op((type)(addr)); } while (0)
-#define cfg_write(val, addr, type, op) \
- do { op((type *)(addr), (val)); } while (0)
-
-#define cfg_read_err(val) do { *val = -1; } while (0)
-#define cfg_write_err(val) do { } while (0)
-
-#define PCIE_OP(rw, size, type, op) \
-static int pcie_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, int offset, \
- type val) \
-{ \
- int ret; \
- \
- ret = mpc83xx_pcie_remap_cfg(hose, dev); \
- if (ret) { \
- cfg_##rw##_err(val); \
- return ret; \
- } \
- cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
- return 0; \
-}
-
-PCIE_OP(read, byte, u8 *, in_8)
-PCIE_OP(read, word, u16 *, in_le16)
-PCIE_OP(read, dword, u32 *, in_le32)
-PCIE_OP(write, byte, u8, out_8)
-PCIE_OP(write, word, u16, out_le16)
-PCIE_OP(write, dword, u32, out_le32)
-
-static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
- u8 link)
-{
- extern void disable_addr_trans(void); /* start.S */
- static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
- struct pci_controller *hose = &pcie_hose[bus];
- int i;
-
- /*
- * There are no spare BATs to remap all PCI-E windows for U-Boot, so
- * disable translations. In general, this is not great solution, and
- * that's why we don't register PCI-E hoses by default.
- */
- disable_addr_trans();
-
- for (i = 0; i < 2; i++, reg++) {
- if (reg->size == 0)
- break;
-
- hose->regions[i] = *reg;
- hose->region_count++;
- }
-
- i = hose->region_count++;
- hose->regions[i].bus_start = 0;
- hose->regions[i].phys_start = 0;
- hose->regions[i].size = gd->ram_size;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
-
- i = hose->region_count++;
- hose->regions[i].bus_start = CONFIG_SYS_IMMR;
- hose->regions[i].phys_start = CONFIG_SYS_IMMR;
- hose->regions[i].size = 0x100000;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
-
- hose->first_busno = pci_last_busno() + 1;
- hose->last_busno = 0xff;
-
- hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
-
- hose->priv_data = &pcie_priv[bus];
-
- pci_set_ops(hose,
- pcie_read_config_byte,
- pcie_read_config_word,
- pcie_read_config_dword,
- pcie_write_config_byte,
- pcie_write_config_word,
- pcie_write_config_dword);
-
- if (!link)
- hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
-
- pci_register_hose(hose);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
-#endif
- /*
- * Hose scan.
- */
- hose->last_busno = pci_hose_scan(hose);
-}
-
-#else
-
-static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
- u8 link) {}
-
-#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
-
int get_pcie_clk(int index)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
@@ -340,8 +198,6 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
printf("link\n");
else
printf("No link\n");
-
- mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
}
/*
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index a861e8dd2d..e12043b260 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -834,12 +834,6 @@ long int spd_sdram()
#endif
debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
-#if defined(CONFIG_DDR_2T_TIMING)
- /*
- * Enable 2T timing by setting sdram_cfg[16].
- */
- sdram_cfg |= SDRAM_CFG_2T_EN;
-#endif
/* Enable controller, and GO! */
ddr->sdram_cfg = sdram_cfg;
sync();
@@ -914,16 +908,12 @@ void ddr_enable_ecc(unsigned int dram_size)
pattern[0] = 0xdeadbeef;
pattern[1] = 0xdeadbeef;
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
- dma_meminit(pattern[0], dram_size);
-#else
debug("ddr init: CPU FP write method\n");
size = dram_size;
for (p = 0; p < (u64*)(size); p++) {
ppcDWstore((u32*)p, pattern);
}
sync();
-#endif
t_end = get_tbms();
icache_disable();
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 9da22ce486..c4953df4a2 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -13,7 +13,6 @@
#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
-#include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
@@ -92,12 +91,6 @@
*/
.long 0x27051956 /* U-Boot Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
-
- .align 2
-
.globl enable_addr_trans
enable_addr_trans:
/* enable address translation */
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 66ebaf529f..836aeddbe2 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -48,6 +48,7 @@ config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
select ARCH_MPC8548
select FSL_VIA
+ select SYS_CACHE_SHIFT_5
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
@@ -316,6 +317,7 @@ config ARCH_MPC8540
config ARCH_MPC8544
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
@@ -350,6 +352,7 @@ config ARCH_MPC8560
config ARCH_P1010
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
@@ -395,6 +398,7 @@ config ARCH_P1011
config ARCH_P1020
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
@@ -490,6 +494,7 @@ config ARCH_P1025
config ARCH_P2020
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
@@ -510,6 +515,7 @@ config ARCH_P2041
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
select SYS_FSL_ERRATUM_A005275
@@ -534,6 +540,7 @@ config ARCH_P3041
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
@@ -563,6 +570,7 @@ config ARCH_P4080
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004580
@@ -601,6 +609,7 @@ config ARCH_P5040
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004699
@@ -624,11 +633,13 @@ config ARCH_P5040
config ARCH_QEMU_E500
bool
+ select SYS_CACHE_SHIFT_5
config ARCH_T1024
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
@@ -651,6 +662,7 @@ config ARCH_T1040
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
@@ -673,6 +685,7 @@ config ARCH_T1042
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
@@ -696,6 +709,7 @@ config ARCH_T2080
select E500MC
select E6500
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
@@ -718,12 +732,14 @@ config ARCH_T2080
imply CMD_NAND
imply CMD_REGINFO
imply FSL_SATA
+ imply ID_EEPROM
config ARCH_T4240
bool
select E500MC
select E6500
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
select SYS_FSL_ERRATUM_A005871
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 15248a4082..6f4ad1f9b7 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
endif
obj-$(CONFIG_CPM2) += commproc.o
-obj-$(CONFIG_CPM2) += ether_fcc.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_CORENET) += liodn.o
obj-$(CONFIG_MP) += mp.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 610a8ec43f..cd32290410 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -11,6 +11,7 @@
#include <config.h>
#include <common.h>
#include <cpu_func.h>
+#include <clock_legacy.h>
#include <init.h>
#include <irq_func.h>
#include <log.h>
@@ -52,7 +53,8 @@ int checkcpu (void)
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
+ defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
ccsr_gur_t __iomem *gur =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
@@ -70,12 +72,12 @@ int checkcpu (void)
>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#else /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
-#endif /* CONFIG_DDR_CLK_FREQ */
+#endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
#endif /* CONFIG_FSL_CORENET */
unsigned int i, core, nr_cores = cpu_numcores();
diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
deleted file mode 100644
index 5cf0a3fb22..0000000000
--- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
+++ /dev/null
@@ -1,462 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * MPC8560 FCC Fast Ethernet
- * Copyright (c) 2003 Motorola,Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
- *
- * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- */
-
-/*
- * MPC8560 FCC Fast Ethernet
- * Basic ET HW initialization and packet RX/TX routines
- *
- * This code will not perform the IO port configuration. This should be
- * done in the iop_conf_t structure specific for the board.
- *
- * TODO:
- * add a PHY driver to do the negotiation
- * reflect negotiation results in FPSMR
- * look for ways to configure the board specific stuff elsewhere, eg.
- * config_xxx.h or the board directory
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/cpm_85xx.h>
-#include <command.h>
-#include <config.h>
-#include <net.h>
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
-
-static struct ether_fcc_info_s
-{
- int ether_index;
- int proff_enet;
- ulong cpm_cr_enet_sblock;
- ulong cpm_cr_enet_page;
- ulong cmxfcr_mask;
- ulong cmxfcr_value;
-}
- ether_fcc_info[] =
-{
-#ifdef CONFIG_ETHER_ON_FCC1
-{
- 0,
- PROFF_FCC1,
- CPM_CR_FCC1_SBLOCK,
- CPM_CR_FCC1_PAGE,
- CONFIG_SYS_CMXFCR_MASK1,
- CONFIG_SYS_CMXFCR_VALUE1
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC2
-{
- 1,
- PROFF_FCC2,
- CPM_CR_FCC2_SBLOCK,
- CPM_CR_FCC2_PAGE,
- CONFIG_SYS_CMXFCR_MASK2,
- CONFIG_SYS_CMXFCR_VALUE2
-},
-#endif
-
-#ifdef CONFIG_ETHER_ON_FCC3
-{
- 2,
- PROFF_FCC3,
- CPM_CR_FCC3_SBLOCK,
- CPM_CR_FCC3_PAGE,
- CONFIG_SYS_CMXFCR_MASK3,
- CONFIG_SYS_CMXFCR_VALUE3
-},
-#endif
-};
-
-/*---------------------------------------------------------------------*/
-
-/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
-#define PKT_MAXDMA_SIZE 1520
-
-/* The FCC stores dest/src/type, data, and checksum for receive packets. */
-#define PKT_MAXBUF_SIZE 1518
-#define PKT_MINBUF_SIZE 64
-
-/* Maximum input buffer size. Must be a multiple of 32. */
-#define PKT_MAXBLR_SIZE 1536
-
-#define TOUT_LOOP 1000000
-
-#define TX_BUF_CNT 2
-
-static uint rxIdx; /* index of the current RX buffer */
-static uint txIdx; /* index of the current TX buffer */
-
-/*
- * FCC Ethernet Tx and Rx buffer descriptors.
- * Provide for Double Buffering
- * Note: PKTBUFSRX is defined in net.h
- */
-
-typedef volatile struct rtxbd {
- cbd_t rxbd[PKTBUFSRX];
- cbd_t txbd[TX_BUF_CNT];
-} RTXBD;
-
-/* Good news: the FCC supports external BDs! */
-#ifdef __GNUC__
-static RTXBD rtx __attribute__ ((aligned(8)));
-#else
-#error "rtx must be 64-bit aligned"
-#endif
-
-#undef ET_DEBUG
-
-static int fec_send(struct eth_device *dev, void *packet, int length)
-{
- int i = 0;
- int result = 0;
-
- if (length <= 0) {
- printf("fec: bad packet size: %d\n", length);
- goto out;
- }
-
- for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= TOUT_LOOP) {
- printf("fec: tx buffer not ready\n");
- goto out;
- }
- }
-
- rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
- rtx.txbd[txIdx].cbd_datlen = length;
- rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
- BD_ENET_TX_TC | BD_ENET_TX_PAD);
-
- for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= TOUT_LOOP) {
- printf("fec: tx error\n");
- goto out;
- }
- }
-
-#ifdef ET_DEBUG
- printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
- printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
- for(i=0;i<(length/16 + 1);i++) {
- printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
- *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
- *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
- }
-#endif
-
- /* return only status bits */
- result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
- txIdx = (txIdx + 1) % TX_BUF_CNT;
-
-out:
- return result;
-}
-
-static int fec_recv(struct eth_device* dev)
-{
- int length;
-
- for (;;)
- {
- if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
- length = -1;
- break; /* nothing received - leave for() loop */
- }
- length = rtx.rxbd[rxIdx].cbd_datlen;
-
- if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
- printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
- }
- else {
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[rxIdx], length - 4);
- }
-
-
- /* Give the buffer back to the FCC. */
- rtx.rxbd[rxIdx].cbd_datlen = 0;
-
- /* wrap around buffer index when necessary */
- if ((rxIdx + 1) >= PKTBUFSRX) {
- rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
- rxIdx = 0;
- }
- else {
- rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
- rxIdx++;
- }
- }
- return length;
-}
-
-
-static int fec_init(struct eth_device* dev, struct bd_info *bis)
-{
- struct ether_fcc_info_s * info = dev->priv;
- int i;
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
- volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
- fcc_enet_t *pram_ptr;
- unsigned long mem_addr;
-
-#if 0
- mii_discover_phy();
-#endif
-
- /* 28.9 - (1-2): ioports have been set up already */
-
- /* 28.9 - (3): connect FCC's tx and rx clocks */
- cpm->im_cpm_mux.cmxuar = 0; /* ATM */
- cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
- info->cmxfcr_value;
-
- /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
- } else if (info->ether_index == 1) {
- cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
- } else if (info->ether_index == 2) {
- cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
- }
-
- /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
- } else if (info->ether_index == 1){
- cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
- } else if (info->ether_index == 2){
- cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
- }
-
- /* 28.9 - (6): FDSR: Ethernet Syn */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.fdsr = 0xD555;
- } else if (info->ether_index == 1) {
- cpm->im_cpm_fcc2.fdsr = 0xD555;
- } else if (info->ether_index == 2) {
- cpm->im_cpm_fcc3.fdsr = 0xD555;
- }
-
- /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
- rxIdx = 0;
- txIdx = 0;
-
- /* Setup Receiver Buffer Descriptors */
- for (i = 0; i < PKTBUFSRX; i++)
- {
- rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
- rtx.rxbd[i].cbd_datlen = 0;
- rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
- }
- rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
- /* Setup Ethernet Transmitter Buffer Descriptors */
- for (i = 0; i < TX_BUF_CNT; i++)
- {
- rtx.txbd[i].cbd_sc = 0;
- rtx.txbd[i].cbd_datlen = 0;
- rtx.txbd[i].cbd_bufaddr = 0;
- }
- rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
- /* 28.9 - (7): initialize parameter ram */
- pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
-
- /* clear whole structure to make sure all reserved fields are zero */
- memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
-
- /*
- * common Parameter RAM area
- *
- * Allocate space in the reserved FCC area of DPRAM for the
- * internal buffers. No one uses this space (yet), so we
- * can do this. Later, we will add resource management for
- * this area.
- * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560
- * 0x9000 for MPC8541, MPC8555
- */
- mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
- pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
- pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
- /*
- * Set maximum bytes per receive buffer.
- * It must be a multiple of 32.
- */
- pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
- /* localbus SDRAM should be preferred */
- pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
- CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
- pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
- pram_ptr->fen_genfcc.fcc_rbdstat = 0;
- pram_ptr->fen_genfcc.fcc_rbdlen = 0;
- pram_ptr->fen_genfcc.fcc_rdptr = 0;
- /* localbus SDRAM should be preferred */
- pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
- CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
- pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
- pram_ptr->fen_genfcc.fcc_tbdstat = 0;
- pram_ptr->fen_genfcc.fcc_tbdlen = 0;
- pram_ptr->fen_genfcc.fcc_tdptr = 0;
-
- /* protocol-specific area */
- pram_ptr->fen_statbuf = 0x0;
- pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
- pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
- pram_ptr->fen_crcec = 0;
- pram_ptr->fen_alec = 0;
- pram_ptr->fen_disfc = 0;
- pram_ptr->fen_retlim = 15; /* Retry limit threshold */
- pram_ptr->fen_retcnt = 0;
- pram_ptr->fen_pper = 0;
- pram_ptr->fen_boffcnt = 0;
- pram_ptr->fen_gaddrh = 0;
- pram_ptr->fen_gaddrl = 0;
- pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
- /*
- * Set Ethernet station address.
- *
- * This is supplied in the board information structure, so we
- * copy that into the controller.
- * So far we have only been given one Ethernet address. We make
- * it unique by setting a few bits in the upper byte of the
- * non-static part of the address.
- */
-#define ea eth_get_ethaddr()
- pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
- pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
- pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
-#undef ea
- pram_ptr->fen_ibdcount = 0;
- pram_ptr->fen_ibdstart = 0;
- pram_ptr->fen_ibdend = 0;
- pram_ptr->fen_txlen = 0;
- pram_ptr->fen_iaddrh = 0; /* disable hash */
- pram_ptr->fen_iaddrl = 0;
- pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
- /* pad pointer. use tiptr since we don't need a specific padding char */
- pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
- pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */
- pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */
-
-#if defined(ET_DEBUG)
- printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
- printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
- pram_ptr->fen_genfcc.fcc_rbase);
- printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
- pram_ptr->fen_genfcc.fcc_tbase);
-#endif
-
- /* 28.9 - (8)(9): clear out events in FCCE */
- /* 28.9 - (9): FCCM: mask all events */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.fcce = ~0x0;
- cpm->im_cpm_fcc1.fccm = 0;
- } else if (info->ether_index == 1) {
- cpm->im_cpm_fcc2.fcce = ~0x0;
- cpm->im_cpm_fcc2.fccm = 0;
- } else if (info->ether_index == 2) {
- cpm->im_cpm_fcc3.fcce = ~0x0;
- cpm->im_cpm_fcc3.fccm = 0;
- }
-
- /* 28.9 - (10-12): we don't use ethernet interrupts */
-
- /* 28.9 - (13)
- *
- * Let's re-initialize the channel now. We have to do it later
- * than the manual describes because we have just now finished
- * the BD initialization.
- */
- cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
- info->cpm_cr_enet_sblock,
- 0x0c,
- CPM_CR_INIT_TRX) | CPM_CR_FLG;
- do {
- __asm__ __volatile__ ("eieio");
- } while (cp->cpcr & CPM_CR_FLG);
-
- /* 28.9 - (14): enable tx/rx in gfmr */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
- } else if (info->ether_index == 1) {
- cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
- } else if (info->ether_index == 2) {
- cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
- }
-
- return 1;
-}
-
-static void fec_halt(struct eth_device* dev)
-{
- struct ether_fcc_info_s * info = dev->priv;
- volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
-
- /* write GFMR: disable tx/rx */
- if(info->ether_index == 0) {
- cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
- } else if(info->ether_index == 1) {
- cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
- } else if(info->ether_index == 2) {
- cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
- }
-}
-
-int fec_initialize(struct bd_info *bis)
-{
- struct eth_device* dev;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
- {
- dev = (struct eth_device*) malloc(sizeof *dev);
- memset(dev, 0, sizeof *dev);
-
- sprintf(dev->name, "FCC%d",
- ether_fcc_info[i].ether_index + 1);
- dev->priv = &ether_fcc_info[i];
- dev->init = fec_init;
- dev->halt = fec_halt;
- dev->send = fec_send;
- dev->recv = fec_recv;
-
- eth_register(dev);
-
-#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
- && defined(CONFIG_BITBANGMII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0) {
- mdio_free(mdiodev);
- return retval;
- }
-#endif
- }
-
- return 1;
-}
-
-#endif
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e229a5c5a7..1fe914a4e4 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <cpu_func.h>
+#include <clock_legacy.h>
#include <ppc_asm.tmpl>
#include <asm/global_data.h>
#include <linux/compiler.h>
@@ -104,8 +105,8 @@ void get_sys_info(sys_info_t *sys_info)
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
else
#endif
-#ifdef CONFIG_DDR_CLK_FREQ
- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
+ sys_info->freq_ddrbus = get_board_ddr_clk();
#else
sys_info->freq_ddrbus = sysclk;
#endif
@@ -538,12 +539,12 @@ void get_sys_info(sys_info_t *sys_info)
/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
sys_info->freq_ddrbus = sys_info->freq_systembus;
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
{
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
- sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk();
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index f41e82ad18..aca31b24c0 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -14,7 +14,6 @@
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
-#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@@ -1138,11 +1137,7 @@ switch_as:
.globl _start
_start:
.long 0x27051956 /* U-BOOT Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
- .align 4
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index f112317376..936cbda11b 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -19,9 +19,11 @@ choice
config MPC866
bool "MPC866"
+ select SYS_CACHE_SHIFT_4
config MPC885
bool "MPC885"
+ select SYS_CACHE_SHIFT_4
endchoice
diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S
index ed735cdee0..0ebb7b33a8 100644
--- a/arch/powerpc/cpu/mpc8xx/start.S
+++ b/arch/powerpc/cpu/mpc8xx/start.S
@@ -23,7 +23,6 @@
#include <asm-offsets.h>
#include <config.h>
#include <mpc8xx.h>
-#include <version.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@@ -62,9 +61,6 @@
*/
.text
.long 0x27051956 /* U-Boot Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
. = EXC_OFF_SYS_RESET
.globl _start
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index eda64861ee..0985fb2d05 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -351,10 +351,6 @@ int fixup_cpu(void)
*/
int cpu_eth_init(struct bd_info *bis)
{
-#if defined(CONFIG_ETHER_ON_FCC)
- fec_initialize(bis);
-#endif
-
#if defined(CONFIG_UEC_ETH)
uec_standard_init(bis);
#endif
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index ac8eeb4caa..f753ddf799 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -25,13 +25,6 @@
*/
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-/*
- * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
- */
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
-#endif
-
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 2c96378efe..a97b72de1b 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -26,15 +26,6 @@
#endif
#endif
-/* Check if boards need to enable FSL DMA engine for SDRAM init */
-#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
-#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
- ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
-#define CONFIG_FSL_DMA
-#endif
-#endif
-
/*
* Provide a default boot page translation virtual address that lines up with
* Freescale's default e500 reset page.
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index e03ab21f59..b6944d88eb 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -46,11 +46,7 @@
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
-#ifdef CONFIG_APUS_FAST_EXCEPT
-#define MSR_ MSR_ME|MSR_IP|MSR_RI
-#else
#define MSR_ MSR_ME|MSR_RI
-#endif
#ifndef CONFIG_E500
#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
#else
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 31c17b5bb3..8d65047aa4 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -119,7 +119,7 @@ static void boot_jump_linux(bootm_headers_t *images)
void arch_lmb_reserve(struct lmb *lmb)
{
phys_size_t bootm_size;
- ulong size, sp, bootmap_base;
+ ulong size, bootmap_base;
bootmap_base = env_get_bootm_low();
bootm_size = env_get_bootm_size();
@@ -141,21 +141,7 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, base, bootm_size - size);
}
- /*
- * Booting a (Linux) kernel image
- *
- * Allocate space for command line and board info - the
- * address should be as high as possible within the reach of
- * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
- * memory, which means far enough below the current stack
- * pointer.
- */
- sp = get_sp();
- debug("## Current stack ends at 0x%08lx\n", sp);
-
- /* adjust sp by 4K to be safe */
- sp -= 4096;
- lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp));
+ arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
#ifdef CONFIG_MP
cpu_mp_lmb_reserve(lmb);
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