12 files changed, 146 insertions, 11 deletions
diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h
index ab5860c0fd..762160da88 100644
--- a/arch/x86/include/asm/arch-apollolake/gpio.h
+++ b/arch/x86/include/asm/arch-apollolake/gpio.h
@@ -485,4 +485,22 @@
 /* This is needed by ACPI */
 #define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
 
+#ifndef __ASSEMBLY__
+
+#include <dt-structs.h>
+
+/**
+ * struct apl_gpio_plat - platform data for each device
+ *
+ * @dtplat: of-platdata data from C struct
+ */
+struct apl_gpio_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	/* Put this first since driver model will copy the data here */
+	struct dtd_intel_apl_pinctrl dtplat;
+#endif
+};
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* _ASM_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-apollolake/hostbridge.h b/arch/x86/include/asm/arch-apollolake/hostbridge.h
new file mode 100644
index 0000000000..f4dce0d522
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/hostbridge.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef _ASM_ARCH_HOSTBRIDGE_H_
+#define _ASM_ARCH_HOSTBRIDGE_H_
+
+/**
+ * struct apl_hostbridge_plat - platform data for hostbridge
+ *
+ * @dtplat: Platform data for of-platdata
+ * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
+ * @early_pads_count: Number of pads to process
+ * @pciex_region_size: BAR length in bytes
+ * @bdf: Bus/device/function of hostbridge
+ */
+struct apl_hostbridge_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_intel_apl_hostbridge dtplat;
+#endif
+	u32 *early_pads;
+	int early_pads_count;
+	uint pciex_region_size;
+	pci_dev_t bdf;
+};
+
+#endif /* _ASM_ARCH_HOSTBRIDGE_H_ */
diff --git a/arch/x86/include/asm/arch-apollolake/pmc.h b/arch/x86/include/asm/arch-apollolake/pmc.h
new file mode 100644
index 0000000000..23ac8fe7e2
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/pmc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef ASM_ARCH_PMC_H
+#define ASM_ARCH_PMC_H
+
+struct apl_pmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_intel_apl_pmc dtplat;
+#endif
+	pci_dev_t bdf;
+};
+
+#endif	/* ASM_ARCH_PMC_H */
diff --git a/arch/x86/include/asm/arch-apollolake/uart.h b/arch/x86/include/asm/arch-apollolake/uart.h
index d4fffe6525..38335b0490 100644
--- a/arch/x86/include/asm/arch-apollolake/uart.h
+++ b/arch/x86/include/asm/arch-apollolake/uart.h
@@ -6,6 +6,23 @@
 #ifndef _ASM_ARCH_UART_H
 #define _ASM_ARCH_UART_H
 
+#include <ns16550.h>
+
+/**
+ * struct apl_ns16550_plat - platform data for the APL UART
+ *
+ * Note that when of-platdata is in use, apl_ns16550_of_to_plat() actually
+ * copies the ns16550_plat contents to the start of this struct, meaning that
+ * dtplat is no-longer valid. This is done so that the ns16550 driver can use
+ * dev_get_plat() without any offsets or adjustments.
+ */
+struct apl_ns16550_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_intel_apl_ns16550 dtplat;
+#endif
+	struct ns16550_plat ns16550;
+};
+
 /**
  * apl_uart_init() - Set up the APL UART device and clock
  *
@@ -15,6 +32,6 @@
  * The UART won't actually work unless the GPIO settings are correct and the
  * signals actually exit the SoC. See board_debug_uart_init() for that.
  */
-int apl_uart_init(pci_dev_t bdf, ulong base);
+void apl_uart_init(pci_dev_t bdf, ulong base);
 
 #endif
diff --git a/arch/x86/include/asm/arch-broadwell/gpio.h b/arch/x86/include/asm/arch-broadwell/gpio.h
index a32e2db47e..393230e52b 100644
--- a/arch/x86/include/asm/arch-broadwell/gpio.h
+++ b/arch/x86/include/asm/arch-broadwell/gpio.h
@@ -11,7 +11,7 @@
 #define GPIO_PER_BANK	32
 #define GPIO_BANKS	3
 
-struct broadwell_bank_platdata {
+struct broadwell_bank_plat {
 	uint16_t base_addr;
 	const char *bank_name;
 	int bank;
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 58e4d7b831..a45ae3463c 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -8,7 +8,7 @@
 
 #include <asm-generic/gpio.h>
 
-struct ich6_bank_platdata {
+struct ich6_bank_plat {
 	uint16_t base_addr;
 	const char *bank_name;
 	int offset;
diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h
index 00868d1725..44eedc205c 100644
--- a/arch/x86/include/asm/intel_pinctrl.h
+++ b/arch/x86/include/asm/intel_pinctrl.h
@@ -162,16 +162,15 @@ extern const struct pinctrl_ops intel_pinctrl_ops;
 int intel_pinctrl_probe(struct udevice *dev);
 
 /**
- * intel_pinctrl_ofdata_to_platdata() - Handle common platdata setup
+ * intel_pinctrl_of_to_plat() - Handle common plat setup
  *
  * @dev: Pinctrl device
  * @comm: Pad community for this device
  * @num_cfgs: Number of configuration words for each pad
  * @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error
  */
-int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
-				     const struct pad_community *comm,
-				     int num_cfgs);
+int intel_pinctrl_of_to_plat(struct udevice *dev,
+			     const struct pad_community *comm, int num_cfgs);
 
 /**
  * pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks
diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h
index f7d3240384..6d4793277e 100644
--- a/arch/x86/include/asm/itss.h
+++ b/arch/x86/include/asm/itss.h
@@ -11,6 +11,8 @@
 #ifndef _ASM_ARCH_ITSS_H
 #define _ASM_ARCH_ITSS_H
 
+#include <irq.h>
+
 #define GPIO_IRQ_START	50
 #define GPIO_IRQ_END	ITSS_MAX_IRQ
 
@@ -42,4 +44,23 @@
 /* ITSS Power reduction control */
 #define PCR_ITSS_ITSSPRC	0x3300
 
+struct itss_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	/* Put this first since driver model will copy the data here */
+	struct dtd_intel_itss dtplat;
+#endif
+};
+
+/* struct pmc_route - Routing for PMC to GPIO */
+struct pmc_route {
+	u32 pmc;
+	u32 gpio;
+};
+
+struct itss_priv {
+	struct pmc_route *route;
+	uint route_count;
+	u32 irq_snapshot[NUM_IPC_REGS];
+};
+
 #endif /* _ASM_ARCH_ITSS_H */
diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h
index 5f9b8c6564..1e4e35321d 100644
--- a/arch/x86/include/asm/mp.h
+++ b/arch/x86/include/asm/mp.h
@@ -114,7 +114,7 @@ typedef void (*mp_run_func)(void *arg);
  * Running on anything other than the boot CPU is only supported if
  * CONFIG_SMP_AP_WORK is enabled
  *
- * @cpu_select: CPU to run on (its dev->req_seq value), or MP_SELECT_ALL for
+ * @cpu_select: CPU to run on (its dev_seq() value), or MP_SELECT_ALL for
  *	all, or MP_SELECT_BSP for BSP
  * @func: Function to run
  * @arg: Argument to pass to the function
diff --git a/arch/x86/include/asm/p2sb.h b/arch/x86/include/asm/p2sb.h
new file mode 100644
index 0000000000..6f63eae8e2
--- /dev/null
+++ b/arch/x86/include/asm/p2sb.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef ASM_P2SB_H
+#define ASM_P2SB_H
+
+/* Platform data for the P2SB */
+struct p2sb_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_intel_p2sb dtplat;
+#endif
+	ulong mmio_base;
+	pci_dev_t bdf;
+};
+
+#endif	/* ASM_P2SB_H */
diff --git a/arch/x86/include/asm/pmu.h b/arch/x86/include/asm/pmu.h
index b76bdf64a3..818e80881e 100644
--- a/arch/x86/include/asm/pmu.h
+++ b/arch/x86/include/asm/pmu.h
@@ -2,9 +2,9 @@
 /*
  * Copyright (c) 2017 Intel Corporation
  */
-#ifndef _X86_ASM_PMU_IPC_H_
-#define _X86_ASM_PMU_IPC_H_
+#ifndef _X86_ASM_PMU_H_
+#define _X86_ASM_PMU_H_
 
 int pmu_turn_power(unsigned int lss, bool on);
 
-#endif	/* _X86_ASM_PMU_IPC_H_ */
+#endif	/* _X86_ASM_PMU_H_ */
diff --git a/arch/x86/include/asm/sysreset.h b/arch/x86/include/asm/sysreset.h
new file mode 100644
index 0000000000..5e586f51c0
--- /dev/null
+++ b/arch/x86/include/asm/sysreset.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+#ifndef _X86_ASM_SYSRESET_H_
+#define _X86_ASM_SYSRESET_H_
+
+#include <dt-structs.h>
+
+struct x86_sysreset_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_x86_reset dtplat;
+#endif
+
+	struct udevice *pch;
+};
+
+#endif	/* _X86_ASM_SYSRESET_H_ */