diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/firewall.h | 6 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 10 |
2 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index adab65bc96..5cb7f23f8f 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -115,10 +115,16 @@ struct socfpga_firwall_l4_sys { /* Firewall MPU DDR SCR registers */ #define FW_MPU_DDR_SCR_EN 0x00 #define FW_MPU_DDR_SCR_EN_SET 0x04 +#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10 +#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c + +#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90 +#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c +#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff #define MPUREGION0_ENABLE BIT(0) #define NONMPUREGION0_ENABLE BIT(8) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index fc4e17821b..a8009664fe 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2021 Intel Corporation <www.intel.com> */ #ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -28,8 +28,12 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_FPGAINTF_EN2 0x6c #define SYSMGR_SOC64_FPGAINTF_EN3 0x70 #define SYSMGR_SOC64_DMA_L3MASTER 0x74 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#define SYSMGR_SOC64_DDR_MODE 0xb8 +#else #define SYSMGR_SOC64_HMC_CLK 0xb4 #define SYSMGR_SOC64_IO_PA_CTRL 0xb8 +#endif #define SYSMGR_SOC64_NOC_TIMEOUT 0xc0 #define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 #define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 @@ -143,4 +147,8 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#define SYSMGR_SOC64_DDR_MODE_MSK BIT(0) +#endif + #endif /* _SYSTEM_MANAGER_SOC64_H_ */ |