diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/cpu.c | 28 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/psu_spl_init.c | 80 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/spl.c | 8 | ||||
| -rw-r--r-- | arch/arm/dts/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/dts/zynq-7000.dtsi | 3 | ||||
| -rw-r--r-- | arch/arm/dts/zynq-cc108.dts | 1 | ||||
| -rw-r--r-- | arch/arm/dts/zynq-topic-miami.dts | 1 | ||||
| l--------- | arch/arm/dts/zynq-zc770-xm011-x16.dts | 1 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-mini-emmc.dts | 76 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-mini-nand.dts | 109 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h | 27 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/ddrc.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/lowlevel_init.S | 2 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/ps7_spl_init.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/slcr.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/spl.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/timer.c | 2 |
21 files changed, 334 insertions, 35 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a423aa9629..b730bcb9af 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -803,18 +803,16 @@ config ARCH_ZYNQ select SPL_BOARD_INIT if SPL select SPL_OF_CONTROL if SPL select DM - select DM_ETH - select DM_GPIO + select DM_ETH if NET select SPL_DM if SPL - select DM_MMC + select DM_MMC if MMC select DM_SPI select DM_SERIAL select DM_SPI_FLASH select SPL_SEPARATE_BSS if SPL select DM_USB if USB - select BLK select CLK - select SPL_CLK + select SPL_CLK if SPL select CLK_ZYNQ imply CMD_CLK imply FAT_WRITE diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index 3f922b4097..9e521ed874 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -68,6 +68,12 @@ config PMUFW_INIT_FILE config ZYNQMP_USB bool "Configure ZynqMP USB" +config ZYNQMP_NO_DDR + bool "Disable DDR MMU mapping" + help + This option configures MMU with no DDR to avoid speculative + access to DDR memory where DDR is not present. + config SYS_MALLOC_F_LEN default 0x600 @@ -107,7 +113,7 @@ config SPL_ZYNQMP_ALT_BOOTMODE choice prompt "Boot mode" depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED - default JTAG + default JTAG_MODE config JTAG_MODE bool "JTAG_MODE" diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile index 72dee3ded4..dde1a0f658 100644 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -9,3 +9,4 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o +obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index f026cb4511..bc77dd03c3 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -17,20 +17,24 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region zynqmp_mem_map[] = { +#if !defined(CONFIG_ZYNQMP_NO_DDR) { .virt = 0x0UL, .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { + }, +#endif + { .virt = 0x80000000UL, .phys = 0x80000000UL, .size = 0x70000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, + { .virt = 0xf8000000UL, .phys = 0xf8000000UL, .size = 0x07e00000UL, @@ -48,20 +52,24 @@ static struct mm_region zynqmp_mem_map[] = { #endif .virt = 0x400000000UL, .phys = 0x400000000UL, - .size = 0x200000000UL, + .size = 0x400000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x600000000UL, - .phys = 0x600000000UL, + }, +#if !defined(CONFIG_ZYNQMP_NO_DDR) + { + .virt = 0x800000000UL, + .phys = 0x800000000UL, .size = 0x800000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe00000000UL, - .phys = 0xe00000000UL, - .size = 0xf200000000UL, + }, +#endif + { + .virt = 0x1000000000UL, + .phys = 0x1000000000UL, + .size = 0xf000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN diff --git a/arch/arm/cpu/armv8/zynqmp/psu_spl_init.c b/arch/arm/cpu/armv8/zynqmp/psu_spl_init.c new file mode 100644 index 0000000000..28d39570b3 --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/psu_spl_init.c @@ -0,0 +1,80 @@ +/* + * Copyright 2018 Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/psu_init_gpl.h> + +#define PSU_MASK_POLL_TIME 1100000 + +int __maybe_unused mask_pollonvalue(unsigned long add, u32 mask, u32 value) +{ + int i = 0; + + while ((__raw_readl(add) & mask) != value) { + if (i == PSU_MASK_POLL_TIME) + return 0; + i++; + } + return 1; +} + +__weak int mask_poll(u32 add, u32 mask) +{ + int i = 0; + unsigned long addr = add; + + while (!(__raw_readl(addr) & mask)) { + if (i == PSU_MASK_POLL_TIME) + return 0; + i++; + } + return 1; +} + +__weak u32 mask_read(u32 add, u32 mask) +{ + unsigned long addr = add; + + return __raw_readl(addr) & mask; +} + +__weak void mask_delay(u32 delay) +{ + udelay(delay); +} + +__weak void psu_mask_write(unsigned long offset, unsigned long mask, + unsigned long val) +{ + unsigned long regval = 0; + + regval = readl(offset); + regval &= ~(mask); + regval |= (val & mask); + writel(regval, offset); +} + +__weak void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, unsigned long value) +{ + int rdata = 0; + + rdata = readl(addr); + rdata = rdata & (~mask); + rdata = rdata | (value << shift); + writel(rdata, addr); +} + +__weak int psu_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists. + */ + return -1; +} diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 41b0070a5e..bc7313a88b 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -129,14 +129,6 @@ u32 spl_boot_mode(const u32 boot_device) } } -__weak void psu_init(void) -{ - /* - * This function is overridden by the one in - * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists. - */ -} - #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index da0ae0d242..ebbc0ca51e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -147,6 +147,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zybo.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-ep108.dtb \ + zynqmp-mini-emmc.dtb \ + zynqmp-mini-nand.dtb \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ zynqmp-zcu102-rev1.0.dtb \ diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index d9774d85d1..7ef102ad05 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -50,7 +50,8 @@ compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; - reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; + reg = <0xf8891000 0x1000>, + <0xf8893000 0x1000>; }; regulator_vccpint: fixedregulator { diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts index a55e82b210..4804da5235 100644 --- a/arch/arm/dts/zynq-cc108.dts +++ b/arch/arm/dts/zynq-cc108.dts @@ -100,6 +100,7 @@ }; &uart0 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts index 79a3671a8e..bf421f6653 100644 --- a/arch/arm/dts/zynq-topic-miami.dts +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -13,7 +13,6 @@ compatible = "topic,miami", "xlnx,zynq-7000"; aliases { - ethernet0 = &gem0; serial0 = &uart0; spi0 = &qspi; i2c0 = &i2c0; diff --git a/arch/arm/dts/zynq-zc770-xm011-x16.dts b/arch/arm/dts/zynq-zc770-xm011-x16.dts new file mode 120000 index 0000000000..5bd6af39a4 --- /dev/null +++ b/arch/arm/dts/zynq-zc770-xm011-x16.dts @@ -0,0 +1 @@ +zynq-zc770-xm011.dts
\ No newline at end of file diff --git a/arch/arm/dts/zynqmp-mini-emmc.dts b/arch/arm/dts/zynqmp-mini-emmc.dts new file mode 100644 index 0000000000..e65934046b --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-emmc.dts @@ -0,0 +1,76 @@ +/* + * dts file for Xilinx ZynqMP Mini Configuration + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/ { + model = "ZynqMP MINI EMMC"; + compatible = "xlnx,zynqmp"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &dcc; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdhci0: sdhci@ff160000 { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + status = "disabled"; + reg = <0x0 0xff160000 0x0 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + xlnx,device_id = <0>; + }; + + sdhci1: sdhci@ff170000 { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + status = "disabled"; + reg = <0x0 0xff170000 0x0 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + xlnx,device_id = <1>; + }; + }; +}; + +&dcc { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts new file mode 100644 index 0000000000..16e5f55ebc --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -0,0 +1,109 @@ +/* + * dts file for Xilinx ZynqMP Mini Configuration + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/ { + model = "ZynqMP MINI NAND"; + compatible = "xlnx,zynqmp"; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + serial0 = &dcc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x40000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + nand0: nand@ff100000 { + compatible = "arasan,nfc-v3p10"; + status = "okay"; + reg = <0x0 0xff100000 0x1000>; + clock-names = "clk_sys", "clk_flash"; + #address-cells = <2>; + #size-cells = <1>; + arasan,has-mdma; + num-cs = <2>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; + partition@6 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x1 0x0 0x400000>; + }; + partition@7 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x1 0x400000 0x1400000>; + }; + partition@8 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x1 0x1800000 0x400000>; + }; + partition@9 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x1 0x1C00000 0x1400000>; + }; + partition@10 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x1 0x3000000 0x400000>; + }; + partition@11 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x1 0x3400000 0xFCC00000>; + }; + }; + }; +}; + +&dcc { + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h b/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h new file mode 100644 index 0000000000..1f7d4f7659 --- /dev/null +++ b/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h @@ -0,0 +1,27 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PSU_INIT_GPL_H_ /* prevent circular inclusions */ +#define _PSU_INIT_GPL_H_ + +#include <asm/io.h> +#include <common.h> + +int mask_pollonvalue(unsigned long add, u32 mask, u32 value); + +int mask_poll(u32 add, u32 mask); + +u32 mask_read(u32 add, u32 mask); + +void mask_delay(u32 delay); + +void psu_mask_write(unsigned long offset, unsigned long mask, + unsigned long val); + +void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, unsigned long value); + +int psu_init(void); + +#endif /* _PSU_INIT_GPL_H_ */ diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index ad28568633..084d55a2b0 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -33,8 +33,6 @@ enum { int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); unsigned int zynqmp_get_silicon_version(void); -void psu_init(void); - void handoff_setup(void); void zynqmp_pmufw_version(void); diff --git a/arch/arm/mach-zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c index bde52d6562..047a7b4d9c 100644 --- a/arch/arm/mach-zynq/ddrc.c +++ b/arch/arm/mach-zynq/ddrc.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu> - * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved. + * Copyright (C) 2012 - 2017 Xilinx, Inc. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/mach-zynq/lowlevel_init.S b/arch/arm/mach-zynq/lowlevel_init.S index 6d714b711c..e5ec9bea55 100644 --- a/arch/arm/mach-zynq/lowlevel_init.S +++ b/arch/arm/mach-zynq/lowlevel_init.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Xilinx, Inc. All rights reserved. + * Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/mach-zynq/ps7_spl_init.c b/arch/arm/mach-zynq/ps7_spl_init.c index 6dc4e0364d..ba2dad759c 100644 --- a/arch/arm/mach-zynq/ps7_spl_init.c +++ b/arch/arm/mach-zynq/ps7_spl_init.c @@ -58,7 +58,7 @@ static void perf_start_clock(void) } /* Compute mask for given delay in miliseconds*/ -static int get_number_of_cycles_for_delay(unsigned int delay) +static unsigned long get_number_of_cycles_for_delay(unsigned long delay) { return (APU_FREQ / (2 * 1000)) * delay; } @@ -92,7 +92,7 @@ int __weak ps7_config(unsigned long *ps7_config_init) unsigned long mask; unsigned int numargs; int i; - int delay; + unsigned long delay; for (;;) { opcode = ptr[0]; diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index ba453a7024..0b263fac58 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 Xilinx Inc. + * Copyright (c) 2013 - 2017 Xilinx Inc. * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 1672fa05c2..b7e6d98f08 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 Xilinx, Inc. Michal Simek + * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index b1bb3b80e1..493d608a5b 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c @@ -3,7 +3,7 @@ * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> * * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> - * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. + * Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved. * * (C) Copyright 2008 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> |