diff options
Diffstat (limited to 'board/amcc/katmai')
| -rw-r--r-- | board/amcc/katmai/Kconfig | 12 | ||||
| -rw-r--r-- | board/amcc/katmai/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/amcc/katmai/Makefile | 10 | ||||
| -rw-r--r-- | board/amcc/katmai/chip_config.c | 38 | ||||
| -rw-r--r-- | board/amcc/katmai/config.mk | 20 | ||||
| -rw-r--r-- | board/amcc/katmai/init.S | 103 | ||||
| -rw-r--r-- | board/amcc/katmai/katmai.c | 270 |
7 files changed, 0 insertions, 459 deletions
diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig deleted file mode 100644 index fc606cff1c..0000000000 --- a/board/amcc/katmai/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KATMAI - -config SYS_BOARD - default "katmai" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "katmai" - -endif diff --git a/board/amcc/katmai/MAINTAINERS b/board/amcc/katmai/MAINTAINERS deleted file mode 100644 index f0893522cc..0000000000 --- a/board/amcc/katmai/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KATMAI BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/katmai/ -F: include/configs/katmai.h -F: configs/katmai_defconfig diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile deleted file mode 100644 index b738defc1e..0000000000 --- a/board/amcc/katmai/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := katmai.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/board/amcc/katmai/chip_config.c b/board/amcc/katmai/chip_config.c deleted file mode 100644 index 5e711c43b7..0000000000 --- a/board/amcc/katmai/chip_config.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "400-133","CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "500-166","CPU: 500 PLB: 166 OPB: 83 EBC: 83", - { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "533-133","CPU: 533 PLB: 133 OPB: 66 EBC: 66", - { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "667-133","CPU: 667 PLB: 133 OPB: 66 EBC: 66", - { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "667-166","CPU: 667 PLB: 166 OPB: 83 EBC: 83", - { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "800-160","CPU: 800 PLB: 160 OPB: 53 EBC: 17", - { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/amcc/katmai/config.mk b/board/amcc/katmai/config.mk deleted file mode 100644 index 6108f79979..0000000000 --- a/board/amcc/katmai/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 440SPe Evaluation (Katmai) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S deleted file mode 100644 index 32f26672e2..0000000000 --- a/board/amcc/katmai/init.S +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - -/************************************************************************** - * TLB table for revA - *************************************************************************/ - .globl tlbtabA -tlbtabA: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG) - tlbtab_end - -/************************************************************************** - * TLB table for revB - * - * Notice: revB of the 440SPe chip is very strict about PLB real addresses - * and ranges to be mapped for config space: it seems to only work with - * d_nnnn_nnnn range (hangs the core upon config transaction attempts when - * set otherwise) while revA uses c_nnnn_nnnn. - *************************************************************************/ - .globl tlbtabB -tlbtabB: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG) - tlbtab_end diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c deleted file mode 100644 index 7582d40ad1..0000000000 --- a/board/amcc/katmai/katmai.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * (C) Copyright 2007-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <i2c.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <netdev.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/4xx_pcie.h> -#include <linux/errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f (void) -{ - unsigned long mfr; - - /*----------------------------------------------------------------------+ - * Interrupt controller setup for the Katmai 440SPe Evaluation board. - *-----------------------------------------------------------------------+ - *-----------------------------------------------------------------------+ - * Interrupt | Source | Pol. | Sensi.| Crit. | - *-----------+-----------------------------------+-------+-------+-------+ - * IRQ 00 | UART0 | High | Level | Non | - * IRQ 01 | UART1 | High | Level | Non | - * IRQ 02 | IIC0 | High | Level | Non | - * IRQ 03 | IIC1 | High | Level | Non | - * IRQ 04 | PCI0X0 MSG IN | High | Level | Non | - * IRQ 05 | PCI0X0 CMD Write | High | Level | Non | - * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | - * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | - * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | - * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | - * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | - * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | - * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | - * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | - * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | - * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | - * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | - * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | - * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | - * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | - * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | - * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | - * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | - * IRQ 23 | I2O Inbound Doorbell | High | Level | Non | - * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | - * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | - * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | - * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | - * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | - * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | - * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | - * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | - *------------------------------------------------------------------------ - * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | - * IRQ 33 | MAL Serr | High | Level | Non | - * IRQ 34 | MAL Txde | High | Level | Non | - * IRQ 35 | MAL Rxde | High | Level | Non | - * IRQ 36 | DMC CE or DMC UE | High | Level | Non | - * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | - * IRQ 38 | MAL TX EOB | High | Level | Non | - * IRQ 39 | MAL RX EOB | High | Level | Non | - * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | - * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | - * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | - * IRQ 43 | L2 Cache | Risin | Edge | Non | - * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | - * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | - * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | - * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | - * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | - * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | - * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | - * IRQ 54 | DMA Error | High | Level | Non | - * IRQ 55 | DMA I2O Error | High | Level | Non | - * IRQ 56 | Serial ROM | High | Level | Non | - * IRQ 57 | PCIX0 Error | High | Edge | Non | - * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | - * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | - * IRQ 60 | EMAC0 Interrupt | High | Level | Non | - * IRQ 61 | EMAC0 Wake-up | High | Level | Non | - * IRQ 62 | Reserved | High | Level | Non | - * IRQ 63 | XOR | High | Level | Non | - *----------------------------------------------------------------------- - * IRQ 64 | PE0 AL | High | Level | Non | - * IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - * IRQ 68 | PE0 TCR | High | Level | Non | - * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - * IRQ 70 | PE0 DCR Error | High | Level | Non | - * IRQ 71 | Reserved | N/A | N/A | Non | - * IRQ 72 | PE1 AL | High | Level | Non | - * IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - * IRQ 76 | PE1 TCR | High | Level | Non | - * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - * IRQ 78 | PE1 DCR Error | High | Level | Non | - * IRQ 79 | Reserved | N/A | N/A | Non | - * IRQ 80 | PE2 AL | High | Level | Non | - * IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - * IRQ 84 | PE2 TCR | High | Level | Non | - * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - * IRQ 86 | PE2 DCR Error | High | Level | Non | - * IRQ 87 | Reserved | N/A | N/A | Non | - * IRQ 88 | External IRQ(5) | Progr | Progr | Non | - * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - * IRQ 94 | Reserved | N/A | N/A | Non | - * IRQ 95 | Reserved | N/A | N/A | Non | - *----------------------------------------------------------------------- - * IRQ 96 | PE0 INTA | High | Level | Non | - * IRQ 97 | PE0 INTB | High | Level | Non | - * IRQ 98 | PE0 INTC | High | Level | Non | - * IRQ 99 | PE0 INTD | High | Level | Non | - * IRQ 100 | PE1 INTA | High | Level | Non | - * IRQ 101 | PE1 INTB | High | Level | Non | - * IRQ 102 | PE1 INTC | High | Level | Non | - * IRQ 103 | PE1 INTD | High | Level | Non | - * IRQ 104 | PE2 INTA | High | Level | Non | - * IRQ 105 | PE2 INTB | High | Level | Non | - * IRQ 106 | PE2 INTC | High | Level | Non | - * IRQ 107 | PE2 INTD | Risin | Edge | Non | - * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | - * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | - * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | - * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | - * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | - * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | - * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | - * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | - * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | - * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | - * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | - * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | - * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | - * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | - * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | - * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | - * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | - * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | - * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | - * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | - *-----------+-----------------------------------+-------+-------+-------+ */ - /*-------------------------------------------------------------------------+ - * Put UICs in PowerPC440SPemode. - * Initialise UIC registers. Clear all interrupts. Disable all interrupts. - * Set critical interrupt values. Set interrupt polarities. Set interrupt - * trigger levels. Make bit 0 High priority. Clear all interrupts again. - *------------------------------------------------------------------------*/ - mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */ - mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/ - mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/ - - - mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/ - mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ - mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/ - mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/ - mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ - mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/ - mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/ - - mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */ - mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/ - mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/ - mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/ - - mfsdr(SDR0_MFR, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(SDR0_MFR, mfr); - - mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); - - out32(GPIO0_OR, CONFIG_SYS_GPIO_OR); - out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR); - out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR); - - return 0; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Katmai - AMCC 440SPe Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -u32 ddr_wrdtr(u32 default_val) { - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); -} - -u32 ddr_clktr(u32 default_val) { - return (SDRAM_CLKTR_CLKP_90_DEG_ADV); -} - -#if defined(CONFIG_PCI) -int board_pcie_card_present(int port) -{ - u32 val; - - val = in32(GPIO0_IR); - switch (port) { - case 0: - return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0)); - case 1: - return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1)); - case 2: - return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2)); - default: - return 0; - } -} -#endif /* defined(CONFIG_PCI) */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} |