diff options
Diffstat (limited to 'board/esd/cpci2dp')
| -rw-r--r-- | board/esd/cpci2dp/cpci2dp.c | 12 | ||||
| -rw-r--r-- | board/esd/cpci2dp/flash.c | 10 |
2 files changed, 11 insertions, 11 deletions
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index cd57ed4598..00c7024a85 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -31,13 +31,13 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * Setup GPIO pins */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); @@ -72,7 +72,7 @@ int board_early_init_f (void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -81,8 +81,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c index 56c822ec97..224dde4ee0 100644 --- a/board/esd/cpci2dp/flash.c +++ b/board/esd/cpci2dp/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, |