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-rw-r--r--board/gdsys/405ep/io.c13
-rw-r--r--board/gdsys/405ep/iocon.c27
-rw-r--r--board/gdsys/405ex/io64.c25
-rw-r--r--board/gdsys/mpc8308/hrcon.c27
-rw-r--r--board/gdsys/mpc8308/strider.c27
-rw-r--r--board/nvidia/p2771-0000/p2771-0000.c48
-rw-r--r--board/nvidia/venice2/as3722_init.c13
-rw-r--r--board/nvidia/venice2/as3722_init.h4
8 files changed, 164 insertions, 20 deletions
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index 03d796cdb8..81b49659ff 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -172,8 +172,17 @@ int last_stage_init(void)
print_fpga_info();
- miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
- bb_miiphy_read, bb_miiphy_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
for (k = 0; k < 32; ++k)
configure_gbit_phy(k);
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 7484624d13..7db0e29ea6 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -405,8 +405,17 @@ int last_stage_init(void)
}
if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
- miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
- bb_miiphy_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
if ((mux_ch == 1) && !ch0_rgmii2_present)
continue;
@@ -437,8 +446,18 @@ int last_stage_init(void)
print_fpga_info(k, false);
osd_probe(k);
if (feature_carrier_speed == CARRIER_SPEED_1G) {
- miiphy_register(bb_miiphy_buses[k].name,
- bb_miiphy_read, bb_miiphy_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, bb_miiphy_buses[k].name,
+ MDIO_NAME_LEN);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
setup_88e1518(bb_miiphy_buses[k].name, 0);
}
}
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index 3a075c471f..848cdde5e6 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -246,8 +246,17 @@ int last_stage_init(void)
/* setup Gbit PHYs */
puts("TRANS: ");
puts(str_phys);
- miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
- bb_miiphy_read, bb_miiphy_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
for (k = 0; k < 32; ++k) {
configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
@@ -255,8 +264,16 @@ int last_stage_init(void)
putc(slash[k % 8]);
}
- miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
- bb_miiphy_read, bb_miiphy_write);
+ mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
for (k = 0; k < 32; ++k) {
configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
index 880b6387de..f55893f79c 100644
--- a/board/gdsys/mpc8308/hrcon.c
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -162,8 +162,17 @@ int last_stage_init(void)
}
if (hw_type_cat) {
- miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
- bb_miiphy_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
if ((mux_ch == 1) && !ch0_rgmii2_present)
continue;
@@ -199,8 +208,18 @@ int last_stage_init(void)
osd_probe(k + 4);
#endif
if (hw_type_cat) {
- miiphy_register(bb_miiphy_buses[k].name,
- bb_miiphy_read, bb_miiphy_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, bb_miiphy_buses[k].name,
+ MDIO_NAME_LEN);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
setup_88e1514(bb_miiphy_buses[k].name, 0);
}
}
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
index 121977d315..b8dde5f1ba 100644
--- a/board/gdsys/mpc8308/strider.c
+++ b/board/gdsys/mpc8308/strider.c
@@ -179,8 +179,17 @@ int last_stage_init(void)
}
if (hw_type_cat) {
- miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
- bb_miiphy_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
if ((mux_ch == 1) && !ch0_sgmii2_present)
continue;
@@ -252,8 +261,18 @@ int last_stage_init(void)
dp501_probe(k, false);
#endif
if (hw_type_cat) {
- miiphy_register(bb_miiphy_buses[k].name,
- bb_miiphy_read, bb_miiphy_write);
+ int retval;
+ struct mii_dev *mdiodev = mdio_alloc();
+ if (!mdiodev)
+ return -ENOMEM;
+ strncpy(mdiodev->name, bb_miiphy_buses[k].name,
+ MDIO_NAME_LEN);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
setup_88e1514(bb_miiphy_buses[k].name, 0);
}
}
diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c
index 4ba8ebc0dc..529ed9d454 100644
--- a/board/nvidia/p2771-0000/p2771-0000.c
+++ b/board/nvidia/p2771-0000/p2771-0000.c
@@ -5,3 +5,51 @@
*/
#include <common.h>
+#include <i2c.h>
+#include "../p2571/max77620_init.h"
+
+int tegra_board_init(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO3 to 3.3V for SD card power */
+ debug("%s: Set LDO3 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+ return ret;
+ }
+ /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ val = 0xF2;
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1);
+ if (ret) {
+ printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int tegra_pcie_board_init(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO7 to 1.05V for PEX power */
+ debug("%s: Set LDO7 for PEX power to 1.05V\n", __func__);
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+ return -1;
+ }
+ /* 0xC5 for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ val = 0xC5;
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L7_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x31 failed: %d\n", ret);
+
+ return 0;
+}
diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c
index 960fea7ee7..1770ec2468 100644
--- a/board/nvidia/venice2/as3722_init.c
+++ b/board/nvidia/venice2/as3722_init.c
@@ -32,7 +32,18 @@ void pmic_enable_cpu_vdd(void)
{
debug("%s entry\n", __func__);
- /* Don't need to set up VDD_CORE - already done - by OTP */
+#ifdef AS3722_SD1VOLTAGE_DATA
+ /* Set up VDD_CORE, for boards where OTP is incorrect*/
+ debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
+ /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ /*
+ * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+ * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
+ */
+ udelay(10 * 1000);
+#endif
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
/*
diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h
index 992b11f643..c6b1247149 100644
--- a/board/nvidia/venice2/as3722_init.h
+++ b/board/nvidia/venice2/as3722_init.h
@@ -25,8 +25,10 @@
#endif
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
-#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
+#ifdef CONFIG_TARGET_JETSON_TK1
+#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG)
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
+#endif
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
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