diff options
Diffstat (limited to 'drivers/clk/at91/compat.c')
| -rw-r--r-- | drivers/clk/at91/compat.c | 86 |
1 files changed, 41 insertions, 45 deletions
diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index 9563285674..e514f26656 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; -struct pmc_platdata { +struct pmc_plat { struct at91_pmc *reg_base; struct regmap *regmap_sfr; }; @@ -45,7 +45,7 @@ U_BOOT_DRIVER(at91_pmc) = { static int at91_pmc_core_probe(struct udevice *dev) { - struct pmc_platdata *plat = dev_get_platdata(dev); + struct pmc_plat *plat = dev_get_plat(dev); dev = dev_get_parent(dev); @@ -62,34 +62,30 @@ static int at91_pmc_core_probe(struct udevice *dev) */ int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name) { - const void *fdt = gd->fdt_blob; - int offset = dev_of_offset(dev); + ofnode parent = dev_ofnode(dev); + ofnode node; bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC); const char *name; int ret; - for (offset = fdt_first_subnode(fdt, offset); - offset > 0; - offset = fdt_next_subnode(fdt, offset)) { - if (pre_reloc_only && - !ofnode_pre_reloc(offset_to_ofnode(offset))) + ofnode_for_each_subnode(node, parent) { + if (pre_reloc_only && !ofnode_pre_reloc(node)) continue; /* * If this node has "compatible" property, this is not * a clock sub-node, but a normal device. skip. */ - fdt_get_property(fdt, offset, "compatible", &ret); - if (ret >= 0) + if (ofnode_read_prop(node, "compatible", NULL)) continue; if (ret != -FDT_ERR_NOTFOUND) return ret; - name = fdt_get_name(fdt, offset, NULL); + name = ofnode_get_name(node); if (!name) return -EINVAL; - ret = device_bind_driver_to_node(dev, drv_name, name, - offset_to_ofnode(offset), NULL); + ret = device_bind_driver_to_node(dev, drv_name, name, node, + NULL); if (ret) return ret; } @@ -119,7 +115,7 @@ int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) int at91_clk_probe(struct udevice *dev) { struct udevice *dev_periph_container, *dev_pmc; - struct pmc_platdata *plat = dev_get_platdata(dev); + struct pmc_plat *plat = dev_get_plat(dev); dev_periph_container = dev_get_parent(dev); dev_pmc = dev_get_parent(dev_periph_container); @@ -195,7 +191,7 @@ U_BOOT_DRIVER(at91_master_clk) = { /* Main osc clock specific code. */ static int main_osc_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; if (readl(&pmc->sr) & AT91_PMC_MOSCSELS) @@ -229,14 +225,14 @@ U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = { .id = UCLASS_CLK, .of_match = main_osc_clk_match, .probe = main_osc_clk_probe, - .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &main_osc_clk_ops, }; /* PLLA clock specific code. */ static int plla_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; if (readl(&pmc->sr) & AT91_PMC_LOCKA) @@ -270,7 +266,7 @@ U_BOOT_DRIVER(at91_plla_clk) = { .id = UCLASS_CLK, .of_match = plla_clk_match, .probe = plla_clk_probe, - .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &plla_clk_ops, }; @@ -282,7 +278,7 @@ static int at91_plladiv_clk_enable(struct clk *clk) static ulong at91_plladiv_clk_get_rate(struct clk *clk) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk source; ulong clk_rate; @@ -301,7 +297,7 @@ static ulong at91_plladiv_clk_get_rate(struct clk *clk) static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk source; ulong parent_rate; @@ -344,7 +340,7 @@ U_BOOT_DRIVER(at91_plladiv_clk) = { .id = UCLASS_CLK, .of_match = at91_plladiv_clk_match, .probe = at91_plladiv_clk_probe, - .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &at91_plladiv_clk_ops, }; @@ -405,7 +401,7 @@ static ulong system_clk_set_rate(struct clk *clk, ulong rate) static int system_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; u32 mask; @@ -441,7 +437,7 @@ U_BOOT_DRIVER(system_clk) = { .name = "system-clk", .id = UCLASS_CLK, .probe = at91_clk_probe, - .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &system_clk_ops, }; @@ -487,7 +483,7 @@ U_BOOT_DRIVER(sam9x5_periph_clk) = { static int periph_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; enum periph_clk_type clk_type; void *addr; @@ -540,7 +536,7 @@ static struct clk_ops periph_clk_ops = { U_BOOT_DRIVER(clk_periph) = { .name = "periph-clk", .id = UCLASS_CLK, - .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .probe = at91_clk_probe, .ops = &periph_clk_ops, }; @@ -556,7 +552,7 @@ U_BOOT_DRIVER(clk_periph) = { static int utmi_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk clk_dev; ulong clk_rate; @@ -642,9 +638,9 @@ static struct clk_ops utmi_clk_ops = { .get_rate = utmi_clk_get_rate, }; -static int utmi_clk_ofdata_to_platdata(struct udevice *dev) +static int utmi_clk_of_to_plat(struct udevice *dev) { - struct pmc_platdata *plat = dev_get_platdata(dev); + struct pmc_plat *plat = dev_get_plat(dev); struct udevice *syscon; uclass_get_device_by_phandle(UCLASS_SYSCON, dev, @@ -671,8 +667,8 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = { .id = UCLASS_CLK, .of_match = utmi_clk_match, .probe = utmi_clk_probe, - .ofdata_to_platdata = utmi_clk_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .of_to_plat = utmi_clk_of_to_plat, + .plat_auto = sizeof(struct pmc_plat), .ops = &utmi_clk_ops, }; @@ -685,7 +681,7 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = { static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; ulong rate = gd->arch.mck_rate_hz; @@ -717,7 +713,7 @@ U_BOOT_DRIVER(sama5d4_h32mx_clk) = { .id = UCLASS_CLK, .of_match = sama5d4_h32mx_clk_match, .probe = sama5d4_h32mx_clk_probe, - .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &sama5d4_h32mx_clk_ops, }; @@ -758,7 +754,7 @@ struct generic_clk_priv { static ulong generic_clk_get_rate(struct clk *clk) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk parent; ulong clk_rate; @@ -786,7 +782,7 @@ static ulong generic_clk_get_rate(struct clk *clk) static ulong generic_clk_set_rate(struct clk *clk, ulong rate) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct generic_clk_priv *priv = dev_get_priv(clk->dev); struct clk parent, best_parent; @@ -857,7 +853,7 @@ static struct clk_ops generic_clk_ops = { .set_rate = generic_clk_set_rate, }; -static int generic_clk_ofdata_to_platdata(struct udevice *dev) +static int generic_clk_of_to_plat(struct udevice *dev) { struct generic_clk_priv *priv = dev_get_priv(dev); u32 cells[GENERATED_SOURCE_MAX]; @@ -879,9 +875,9 @@ U_BOOT_DRIVER(generic_clk) = { .name = "generic-clk", .id = UCLASS_CLK, .probe = at91_clk_probe, - .ofdata_to_platdata = generic_clk_ofdata_to_platdata, - .priv_auto_alloc_size = sizeof(struct generic_clk_priv), - .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .of_to_plat = generic_clk_of_to_plat, + .priv_auto = sizeof(struct generic_clk_priv), + .plat_auto = sizeof(struct pmc_plat), .ops = &generic_clk_ops, }; @@ -899,7 +895,7 @@ struct at91_usb_clk_priv { static ulong at91_usb_clk_get_rate(struct clk *clk) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk source; u32 tmp, usbdiv; @@ -920,7 +916,7 @@ static ulong at91_usb_clk_get_rate(struct clk *clk) static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate) { - struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev); struct clk source, best_source; @@ -981,7 +977,7 @@ static struct clk_ops at91_usb_clk_ops = { .set_rate = at91_usb_clk_set_rate, }; -static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev) +static int at91_usb_clk_of_to_plat(struct udevice *dev) { struct at91_usb_clk_priv *priv = dev_get_priv(dev); u32 cells[AT91_USB_CLK_SOURCE_MAX]; @@ -1015,9 +1011,9 @@ U_BOOT_DRIVER(at91_usb_clk) = { .id = UCLASS_CLK, .of_match = at91_usb_clk_match, .probe = at91_usb_clk_probe, - .ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata, - .priv_auto_alloc_size = sizeof(struct at91_usb_clk_priv), - .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .of_to_plat = at91_usb_clk_of_to_plat, + .priv_auto = sizeof(struct at91_usb_clk_priv), + .plat_auto = sizeof(struct pmc_plat), .ops = &at91_usb_clk_ops, }; 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