1 files changed, 42 insertions, 6 deletions

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 8543679108..0bfcd3413c 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -317,7 +317,24 @@ static void set_timing_cfg_0(const unsigned int ctrl_num,
 
 	/* for faster clock, need more time for data setup */
 	trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
-	twrt_mclk = 1;
+
+	/*
+	 * for single quad-rank DIMM and two-slot DIMMs
+	 * to avoid ODT overlap
+	 */
+	switch (avoid_odt_overlap(dimm_params)) {
+	case 2:
+		twrt_mclk = 2;
+		twwt_mclk = 2;
+		trrt_mclk = 2;
+		break;
+	default:
+		twrt_mclk = 1;
+		twwt_mclk = 1;
+		trrt_mclk = 0;
+		break;
+	}
+
 	act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 	pre_pd_exit_mclk = act_pd_exit_mclk;
 	/*
@@ -1117,10 +1134,18 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
 	unsigned short esdmode4 = 0;	/* Extended SDRAM mode 4 */
 	unsigned short esdmode5;	/* Extended SDRAM mode 5 */
 	int rtt_park = 0;
-
+	bool four_cs = false;
+
+#if CONFIG_CHIP_SELECTS_PER_CTRL == 4
+	if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
+	    (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
+	    (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
+	    (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
+		four_cs = true;
+#endif
 	if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
 		esdmode5 = 0x00000500;	/* Data mask enable, RTT_PARK CS0 */
-		rtt_park = 1;
+		rtt_park = four_cs ? 0 : 1;
 	} else {
 		esdmode5 = 0x00000400;	/* Data mask enabled */
 	}
@@ -1130,7 +1155,10 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
 				 | ((esdmode5 & 0xffff) << 0)
 				);
 
-	/* only mode_9 use 0x500, others use 0x400 */
+	/* Normally only the first enabled CS use 0x500, others use 0x400
+	 * But when four chip-selects are all enabled, all mode registers
+	 * need 0x500 to park.
+	 */
 
 	debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
 	if (unq_mrs_en) {	/* unique mode registers are supported */
@@ -1138,7 +1166,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
 			if (!rtt_park &&
 			    (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
 				esdmode5 |= 0x00000500;	/* RTT_PARK */
-				rtt_park = 1;
+				rtt_park = four_cs ? 0 : 1;
 			} else {
 				esdmode5 = 0x00000400;
 			}
@@ -1186,6 +1214,9 @@ static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
 
 	esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
 
+	if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
+		esdmode6 |= 1 << 6;	/* Range 2 */
+
 	ddr->ddr_sdram_mode_10 = (0
 				 | ((esdmode6 & 0xffff) << 16)
 				 | ((esdmode7 & 0xffff) << 0)
@@ -1808,6 +1839,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
 	unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
 	unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
+	unsigned int trwt_mclk = 0;	/* ext_rwt */
 	unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
 
 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
@@ -1821,17 +1853,21 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
 		wwt = 2;	/* BL/2 + 2 clocks */
 	}
 #endif
-
 #ifdef CONFIG_SYS_FSL_DDR4
 	dll_lock = 2;	/* tDLLK = 1024 clocks */
 #elif defined(CONFIG_SYS_FSL_DDR3)
 	dll_lock = 1;	/* tDLLK = 512 clocks from spec */
 #endif
+
+	if (popts->trwt_override)
+		trwt_mclk = popts->trwt;
+
 	ddr->timing_cfg_4 = (0
 			     | ((rwt & 0xf) << 28)
 			     | ((wrt & 0xf) << 24)
 			     | ((rrt & 0xf) << 20)
 			     | ((wwt & 0xf) << 16)
+			     | ((trwt_mclk & 0xc) << 12)
 			     | (dll_lock & 0x3)
 			     );
 	debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);