11 files changed, 738 insertions, 143 deletions

diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 6b761b453d..f8be9bf1ea 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -6,15 +6,16 @@
 #
 
 ifneq ($(CONFIG_DM_PCI),)
-obj-$(CONFIG_PCI) += pci-uclass.o
+obj-y += pci_rom.o
+obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
 obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
 obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
 obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
 obj-$(CONFIG_X86) += pci_x86.o
 else
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
 endif
-obj-$(CONFIG_PCI) +=  pci_auto_common.o pci_auto_old.o pci_common.o pci_rom.o
+obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
 
 obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
 obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 5fe30723c2..685df9d274 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -11,12 +11,14 @@
 #include <fdtdec.h>
 #include <inttypes.h>
 #include <pci.h>
+#include <asm/io.h>
 #include <dm/lists.h>
 #include <dm/root.h>
 #include <dm/device-internal.h>
 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
 #include <asm/fsp/fsp_support.h>
 #endif
+#include "pci_internal.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -61,7 +63,7 @@ struct udevice *pci_get_controller(struct udevice *dev)
 	return dev;
 }
 
-pci_dev_t pci_get_bdf(struct udevice *dev)
+pci_dev_t dm_pci_get_bdf(struct udevice *dev)
 {
 	struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
 	struct udevice *bus = dev->parent;
@@ -128,7 +130,7 @@ int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
 	return -ENODEV;
 }
 
-int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
+int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
 {
 	struct udevice *bus;
 	int ret;
@@ -194,6 +196,65 @@ int pci_find_device_id(struct pci_device_id *ids, int index,
 	return -ENODEV;
 }
 
+static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
+				  unsigned int device, int *indexp,
+				  struct udevice **devp)
+{
+	struct pci_child_platdata *pplat;
+	struct udevice *dev;
+
+	for (device_find_first_child(bus, &dev);
+	     dev;
+	     device_find_next_child(&dev)) {
+		pplat = dev_get_parent_platdata(dev);
+		if (pplat->vendor == vendor && pplat->device == device) {
+			if (!(*indexp)--) {
+				*devp = dev;
+				return 0;
+			}
+		}
+	}
+
+	return -ENODEV;
+}
+
+int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
+		       struct udevice **devp)
+{
+	struct udevice *bus;
+
+	/* Scan all known buses */
+	for (uclass_first_device(UCLASS_PCI, &bus);
+	     bus;
+	     uclass_next_device(&bus)) {
+		if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
+			return device_probe(*devp);
+	}
+	*devp = NULL;
+
+	return -ENODEV;
+}
+
+int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
+{
+	struct udevice *dev;
+
+	/* Scan all known buses */
+	for (pci_find_first_device(&dev);
+	     dev;
+	     pci_find_next_device(&dev)) {
+		struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
+
+		if (pplat->class == find_class && !index--) {
+			*devp = dev;
+			return device_probe(*devp);
+		}
+	}
+	*devp = NULL;
+
+	return -ENODEV;
+}
+
 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
 			 unsigned long value, enum pci_size_t size)
 {
@@ -225,7 +286,8 @@ int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
 
 	for (bus = dev; device_is_on_pci_bus(bus);)
 		bus = bus->parent;
-	return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
+	return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
+				    size);
 }
 
 
@@ -290,7 +352,7 @@ int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
 
 	for (bus = dev; device_is_on_pci_bus(bus);)
 		bus = bus->parent;
-	return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
+	return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
 				   size);
 }
 
@@ -403,7 +465,7 @@ int pci_auto_config_devices(struct udevice *bus)
 		int ret;
 
 		debug("%s: device %s\n", __func__, dev->name);
-		ret = pciauto_config_device(hose, pci_get_bdf(dev));
+		ret = dm_pciauto_config_device(dev);
 		if (ret < 0)
 			return ret;
 		max_bus = ret;
@@ -418,26 +480,16 @@ int pci_auto_config_devices(struct udevice *bus)
 	return sub_bus;
 }
 
-int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
+int dm_pci_hose_probe_bus(struct udevice *bus)
 {
-	struct udevice *parent, *bus;
 	int sub_bus;
 	int ret;
 
 	debug("%s\n", __func__);
-	parent = hose->bus;
-
-	/* Find the bus within the parent */
-	ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
-	if (ret) {
-		debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
-		      bdf, parent->name, ret);
-		return ret;
-	}
 
 	sub_bus = pci_get_bus_max() + 1;
 	debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
-	pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
+	dm_pciauto_prescan_setup_bridge(bus, sub_bus);
 
 	ret = device_probe(bus);
 	if (ret) {
@@ -451,7 +503,7 @@ int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
 		return -EPIPE;
 	}
 	sub_bus = pci_get_bus_max();
-	pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
+	dm_pciauto_postscan_setup_bridge(bus, sub_bus);
 
 	return sub_bus;
 }
@@ -622,9 +674,7 @@ int pci_bind_bus_devices(struct udevice *bus)
 		/* Find this device in the device tree */
 		ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
 
-		/* Search for a driver */
-
-		/* If nothing in the device tree, bind a generic device */
+		/* If nothing in the device tree, bind a device */
 		if (ret == -ENODEV) {
 			struct pci_device_id find_id;
 			ulong val;
@@ -1004,6 +1054,154 @@ int pci_get_regions(struct udevice *dev, struct pci_region **iop,
 	return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
 }
 
+u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
+{
+	u32 addr;
+	int bar;
+
+	bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+	dm_pci_read_config32(dev, bar, &addr);
+	if (addr & PCI_BASE_ADDRESS_SPACE_IO)
+		return addr & PCI_BASE_ADDRESS_IO_MASK;
+	else
+		return addr & PCI_BASE_ADDRESS_MEM_MASK;
+}
+
+static int _dm_pci_bus_to_phys(struct udevice *ctlr,
+			       pci_addr_t bus_addr, unsigned long flags,
+			       unsigned long skip_mask, phys_addr_t *pa)
+{
+	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+	struct pci_region *res;
+	int i;
+
+	for (i = 0; i < hose->region_count; i++) {
+		res = &hose->regions[i];
+
+		if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
+			continue;
+
+		if (res->flags & skip_mask)
+			continue;
+
+		if (bus_addr >= res->bus_start &&
+		    (bus_addr - res->bus_start) < res->size) {
+			*pa = (bus_addr - res->bus_start + res->phys_start);
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
+			       unsigned long flags)
+{
+	phys_addr_t phys_addr = 0;
+	struct udevice *ctlr;
+	int ret;
+
+	/* The root controller has the region information */
+	ctlr = pci_get_controller(dev);
+
+	/*
+	 * if PCI_REGION_MEM is set we do a two pass search with preference
+	 * on matches that don't have PCI_REGION_SYS_MEMORY set
+	 */
+	if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
+		ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
+					  flags, PCI_REGION_SYS_MEMORY,
+					  &phys_addr);
+		if (!ret)
+			return phys_addr;
+	}
+
+	ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
+
+	if (ret)
+		puts("pci_hose_bus_to_phys: invalid physical address\n");
+
+	return phys_addr;
+}
+
+int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
+			unsigned long flags, unsigned long skip_mask,
+			pci_addr_t *ba)
+{
+	struct pci_region *res;
+	struct udevice *ctlr;
+	pci_addr_t bus_addr;
+	int i;
+	struct pci_controller *hose;
+
+	/* The root controller has the region information */
+	ctlr = pci_get_controller(dev);
+	hose = dev_get_uclass_priv(ctlr);
+
+	for (i = 0; i < hose->region_count; i++) {
+		res = &hose->regions[i];
+
+		if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
+			continue;
+
+		if (res->flags & skip_mask)
+			continue;
+
+		bus_addr = phys_addr - res->phys_start + res->bus_start;
+
+		if (bus_addr >= res->bus_start &&
+		    (bus_addr - res->bus_start) < res->size) {
+			*ba = bus_addr;
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
+			      unsigned long flags)
+{
+	pci_addr_t bus_addr = 0;
+	int ret;
+
+	/*
+	 * if PCI_REGION_MEM is set we do a two pass search with preference
+	 * on matches that don't have PCI_REGION_SYS_MEMORY set
+	 */
+	if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
+		ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
+					  PCI_REGION_SYS_MEMORY, &bus_addr);
+		if (!ret)
+			return bus_addr;
+	}
+
+	ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
+
+	if (ret)
+		puts("pci_hose_phys_to_bus: invalid physical address\n");
+
+	return bus_addr;
+}
+
+void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
+{
+	pci_addr_t pci_bus_addr;
+	u32 bar_response;
+
+	/* read BAR address */
+	dm_pci_read_config32(dev, bar, &bar_response);
+	pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
+
+	/*
+	 * Pass "0" as the length argument to pci_bus_to_virt.  The arg
+	 * isn't actualy used on any platform because u-boot assumes a static
+	 * linear mapping.  In the future, this could read the BAR size
+	 * and pass that as the size if needed.
+	 */
+	return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
+}
+
 UCLASS_DRIVER(pci) = {
 	.id		= UCLASS_PCI,
 	.name		= "pci",
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 645ecd423f..461908941d 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -9,7 +9,10 @@
  */
 
 /*
- * PCI routines
+ * Old PCI routines
+ *
+ * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
+ * and change pci-uclass.c.
  */
 
 #include <common.h>
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
new file mode 100644
index 0000000000..842eafc4f8
--- /dev/null
+++ b/drivers/pci/pci_auto.c
@@ -0,0 +1,386 @@
+/*
+ * PCI autoconfiguration library
+ *
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pci.h>
+
+/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8
+#endif
+
+void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
+			     struct pci_region *mem,
+			     struct pci_region *prefetch, struct pci_region *io,
+			     bool enum_only)
+{
+	u32 bar_response;
+	pci_size_t bar_size;
+	u16 cmdstat = 0;
+	int bar, bar_nr = 0;
+	u8 header_type;
+	int rom_addr;
+	pci_addr_t bar_value;
+	struct pci_region *bar_res;
+	int found_mem64 = 0;
+	u16 class;
+
+	dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+	cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
+			PCI_COMMAND_MASTER;
+
+	for (bar = PCI_BASE_ADDRESS_0;
+	     bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
+		/* Tickle the BAR and get the response */
+		if (!enum_only)
+			dm_pci_write_config32(dev, bar, 0xffffffff);
+		dm_pci_read_config32(dev, bar, &bar_response);
+
+		/* If BAR is not implemented go to the next BAR */
+		if (!bar_response)
+			continue;
+
+		found_mem64 = 0;
+
+		/* Check the BAR type and set our address mask */
+		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
+			bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
+				   & 0xffff) + 1;
+			if (!enum_only)
+				bar_res = io;
+
+			debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
+			      bar_nr, (unsigned long long)bar_size);
+		} else {
+			if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+			     PCI_BASE_ADDRESS_MEM_TYPE_64) {
+				u32 bar_response_upper;
+				u64 bar64;
+
+				if (!enum_only) {
+					dm_pci_write_config32(dev, bar + 4,
+							      0xffffffff);
+				}
+				dm_pci_read_config32(dev, bar + 4,
+						     &bar_response_upper);
+
+				bar64 = ((u64)bar_response_upper << 32) |
+						bar_response;
+
+				bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
+						+ 1;
+				if (!enum_only)
+					found_mem64 = 1;
+			} else {
+				bar_size = (u32)(~(bar_response &
+						PCI_BASE_ADDRESS_MEM_MASK) + 1);
+			}
+			if (!enum_only) {
+				if (prefetch && (bar_response &
+					    PCI_BASE_ADDRESS_MEM_PREFETCH)) {
+					bar_res = prefetch;
+				} else {
+					bar_res = mem;
+				}
+			}
+
+			debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
+			      bar_nr, bar_res == prefetch ? "Prf" : "Mem",
+			      (unsigned long long)bar_size);
+		}
+
+		if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
+							  &bar_value) == 0) {
+			/* Write it out and update our limit */
+			dm_pci_write_config32(dev, bar, (u32)bar_value);
+
+			if (found_mem64) {
+				bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+				dm_pci_write_config32(dev, bar,
+						      (u32)(bar_value >> 32));
+#else
+				/*
+				 * If we are a 64-bit decoder then increment to
+				 * the upper 32 bits of the bar and force it to
+				 * locate in the lower 4GB of memory.
+				 */
+				dm_pci_write_config32(dev, bar, 0x00000000);
+#endif
+			}
+		}
+
+		cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
+			PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
+
+		debug("\n");
+
+		bar_nr++;
+	}
+
+	if (!enum_only) {
+		/* Configure the expansion ROM address */
+		dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+		header_type &= 0x7f;
+		if (header_type != PCI_HEADER_TYPE_CARDBUS) {
+			rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
+				PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
+			dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
+			dm_pci_read_config32(dev, rom_addr, &bar_response);
+			if (bar_response) {
+				bar_size = -(bar_response & ~1);
+				debug("PCI Autoconfig: ROM, size=%#x, ",
+				      (unsigned int)bar_size);
+				if (pciauto_region_allocate(mem, bar_size,
+							    &bar_value) == 0) {
+					dm_pci_write_config32(dev, rom_addr,
+							      bar_value);
+				}
+				cmdstat |= PCI_COMMAND_MEMORY;
+				debug("\n");
+			}
+		}
+	}
+
+	/* PCI_COMMAND_IO must be set for VGA device */
+	dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+	if (class == PCI_CLASS_DISPLAY_VGA)
+		cmdstat |= PCI_COMMAND_IO;
+
+	dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
+	dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
+			     CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+	dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
+}
+
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+	struct pci_region *pci_mem;
+	struct pci_region *pci_prefetch;
+	struct pci_region *pci_io;
+	u16 cmdstat, prefechable_64;
+	/* The root controller has the region information */
+	struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+	pci_mem = ctlr_hose->pci_mem;
+	pci_prefetch = ctlr_hose->pci_prefetch;
+	pci_io = ctlr_hose->pci_io;
+
+	dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
+	dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
+	prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+	/* Configure bus number registers */
+	dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
+			     PCI_BUS(dm_pci_get_bdf(dev)));
+	dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus);
+	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
+
+	if (pci_mem) {
+		/* Round memory allocator to 1MB boundary */
+		pciauto_region_align(pci_mem, 0x100000);
+
+		/*
+		 * Set up memory and I/O filter limits, assume 32-bit
+		 * I/O space
+		 */
+		dm_pci_write_config16(dev, PCI_MEMORY_BASE,
+				      (pci_mem->bus_lower & 0xfff00000) >> 16);
+
+		cmdstat |= PCI_COMMAND_MEMORY;
+	}
+
+	if (pci_prefetch) {
+		/* Round memory allocator to 1MB boundary */
+		pciauto_region_align(pci_prefetch, 0x100000);
+
+		/*
+		 * Set up memory and I/O filter limits, assume 32-bit
+		 * I/O space
+		 */
+		dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
+				(pci_prefetch->bus_lower & 0xfff00000) >> 16);
+		if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+			dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
+					      pci_prefetch->bus_lower >> 32);
+#else
+			dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
+#endif
+
+		cmdstat |= PCI_COMMAND_MEMORY;
+	} else {
+		/* We don't support prefetchable memory for now, so disable */
+		dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
+		dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+		if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
+			dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
+			dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+		}
+	}
+
+	if (pci_io) {
+		/* Round I/O allocator to 4KB boundary */
+		pciauto_region_align(pci_io, 0x1000);
+
+		dm_pci_write_config8(dev, PCI_IO_BASE,
+				     (pci_io->bus_lower & 0x0000f000) >> 8);
+		dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
+				      (pci_io->bus_lower & 0xffff0000) >> 16);
+
+		cmdstat |= PCI_COMMAND_IO;
+	}
+
+	/* Enable memory and I/O accesses, enable bus master */
+	dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
+}
+
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
+{
+	struct pci_region *pci_mem;
+	struct pci_region *pci_prefetch;
+	struct pci_region *pci_io;
+
+	/* The root controller has the region information */
+	struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+	pci_mem = ctlr_hose->pci_mem;
+	pci_prefetch = ctlr_hose->pci_prefetch;
+	pci_io = ctlr_hose->pci_io;
+
+	/* Configure bus number registers */
+	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus);
+
+	if (pci_mem) {
+		/* Round memory allocator to 1MB boundary */
+		pciauto_region_align(pci_mem, 0x100000);
+
+		dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
+				      (pci_mem->bus_lower - 1) >> 16);
+	}
+
+	if (pci_prefetch) {
+		u16 prefechable_64;
+
+		dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
+				     &prefechable_64);
+		prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+		/* Round memory allocator to 1MB boundary */
+		pciauto_region_align(pci_prefetch, 0x100000);
+
+		dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
+				      (pci_prefetch->bus_lower - 1) >> 16);
+		if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+			dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
+					(pci_prefetch->bus_lower - 1) >> 32);
+#else
+			dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+#endif
+	}
+
+	if (pci_io) {
+		/* Round I/O allocator to 4KB boundary */
+		pciauto_region_align(pci_io, 0x1000);
+
+		dm_pci_write_config8(dev, PCI_IO_LIMIT,
+				((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
+		dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
+				((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
+	}
+}
+
+/*
+ * HJF: Changed this to return int. I think this is required
+ * to get the correct result when scanning bridges
+ */
+int dm_pciauto_config_device(struct udevice *dev)
+{
+	struct pci_region *pci_mem;
+	struct pci_region *pci_prefetch;
+	struct pci_region *pci_io;
+	unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
+	unsigned short class;
+	bool enum_only = false;
+	int n;
+
+#ifdef CONFIG_PCI_ENUM_ONLY
+	enum_only = true;
+#endif
+	/* The root controller has the region information */
+	struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+	pci_mem = ctlr_hose->pci_mem;
+	pci_prefetch = ctlr_hose->pci_prefetch;
+	pci_io = ctlr_hose->pci_io;
+
+	dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
+
+	switch (class) {
+	case PCI_CLASS_BRIDGE_PCI:
+		debug("PCI Autoconfig: Found P2P bridge, device %d\n",
+		      PCI_DEV(dm_pci_get_bdf(dev)));
+
+		dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,
+					enum_only);
+
+		n = dm_pci_hose_probe_bus(dev);
+		if (n < 0)
+			return n;
+		sub_bus = (unsigned int)n;
+		break;
+
+	case PCI_CLASS_BRIDGE_CARDBUS:
+		/*
+		 * just do a minimal setup of the bridge,
+		 * let the OS take care of the rest
+		 */
+		dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,
+					enum_only);
+
+		debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
+		      PCI_DEV(dm_pci_get_bdf(dev)));
+
+		break;
+
+#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
+	case PCI_CLASS_BRIDGE_OTHER:
+		debug("PCI Autoconfig: Skipping bridge device %d\n",
+		      PCI_DEV(dm_pci_get_bdf(dev)));
+		break;
+#endif
+#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+	case PCI_CLASS_BRIDGE_OTHER:
+		/*
+		 * The host/PCI bridge 1 seems broken in 8349 - it presents
+		 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
+		 * device claiming resources io/mem/irq.. we only allow for
+		 * the PIMMR window to be allocated (BAR0 - 1MB size)
+		 */
+		debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
+		dm_pciauto_setup_device(dev, 0, hose->pci_mem,
+					hose->pci_prefetch, hose->pci_io,
+					enum_only);
+		break;
+#endif
+
+	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+		debug("PCI AutoConfig: Found PowerPC device\n");
+
+	default:
+		dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,
+					enum_only);
+		break;
+	}
+
+	return sub_bus;
+}
diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c
index 932eab85bf..9126f78b89 100644
--- a/drivers/pci/pci_auto_old.c
+++ b/drivers/pci/pci_auto_old.c
@@ -1,7 +1,5 @@
 /*
- * arch/powerpc/kernel/pci_auto.c
- *
- * PCI autoconfiguration library
+ * PCI autoconfiguration library (legacy version, do not change)
  *
  * Author: Matt Porter <mporter@mvista.com>
  *
@@ -14,6 +12,11 @@
 #include <errno.h>
 #include <pci.h>
 
+/*
+ * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
+ * and change pci_auto.c.
+ */
+
 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8
@@ -177,18 +180,9 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 	struct pci_region *pci_io;
 	u16 cmdstat, prefechable_64;
 
-#ifdef CONFIG_DM_PCI
-	/* The root controller has the region information */
-	struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
-	pci_mem = ctlr_hose->pci_mem;
-	pci_prefetch = ctlr_hose->pci_prefetch;
-	pci_io = ctlr_hose->pci_io;
-#else
 	pci_mem = hose->pci_mem;
 	pci_prefetch = hose->pci_prefetch;
 	pci_io = hose->pci_io;
-#endif
 
 	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 	pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
@@ -196,15 +190,10 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 	prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 
 	/* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
-	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
-	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
-#else
 	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 				   PCI_BUS(dev) - hose->first_busno);
 	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 				   sub_bus - hose->first_busno);
-#endif
 	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 
 	if (pci_mem) {
@@ -271,26 +260,13 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 	struct pci_region *pci_prefetch;
 	struct pci_region *pci_io;
 
-#ifdef CONFIG_DM_PCI
-	/* The root controller has the region information */
-	struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
-	pci_mem = ctlr_hose->pci_mem;
-	pci_prefetch = ctlr_hose->pci_prefetch;
-	pci_io = ctlr_hose->pci_io;
-#else
 	pci_mem = hose->pci_mem;
 	pci_prefetch = hose->pci_prefetch;
 	pci_io = hose->pci_io;
-#endif
 
 	/* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
-	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
-#else
 	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 				   sub_bus - hose->first_busno);
-#endif
 
 	if (pci_mem) {
 		/* Round memory allocator to 1MB boundary */
@@ -350,18 +326,9 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 	unsigned short class;
 	int n;
 
-#ifdef CONFIG_DM_PCI
-	/* The root controller has the region information */
-	struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
-	pci_mem = ctlr_hose->pci_mem;
-	pci_prefetch = ctlr_hose->pci_prefetch;
-	pci_io = ctlr_hose->pci_io;
-#else
 	pci_mem = hose->pci_mem;
 	pci_prefetch = hose->pci_prefetch;
 	pci_io = hose->pci_io;
-#endif
 
 	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 
@@ -373,12 +340,6 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 		pciauto_setup_device(hose, dev, 2, pci_mem,
 				     pci_prefetch, pci_io);
 
-#ifdef CONFIG_DM_PCI
-		n = dm_pci_hose_probe_bus(hose, dev);
-		if (n < 0)
-			return n;
-		sub_bus = (unsigned int)n;
-#else
 		/* Passing in current_busno allows for sibling P2P bridges */
 		hose->current_busno++;
 		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
@@ -393,7 +354,6 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 		pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 
 		sub_bus = hose->current_busno;
-#endif
 		break;
 
 	case PCI_CLASS_BRIDGE_CARDBUS:
@@ -407,9 +367,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 		debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 		      PCI_DEV(dev));
 
-#ifndef CONFIG_DM_PCI
 		hose->current_busno++;
-#endif
 		break;
 
 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
index 2a149022e2..1755914b4e 100644
--- a/drivers/pci/pci_common.c
+++ b/drivers/pci/pci_common.c
@@ -79,48 +79,6 @@ const char *pci_class_str(u8 class)
 	};
 }
 
-pci_dev_t pci_find_class(uint find_class, int index)
-{
-	int bus;
-	int devnum;
-	pci_dev_t bdf;
-	uint32_t class;
-
-	for (bus = 0; bus <= pci_last_busno(); bus++) {
-		for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
-			pci_read_config_dword(PCI_BDF(bus, devnum, 0),
-					      PCI_CLASS_REVISION, &class);
-			if (class >> 16 == 0xffff)
-				continue;
-
-			for (bdf = PCI_BDF(bus, devnum, 0);
-					bdf <= PCI_BDF(bus, devnum,
-						PCI_MAX_PCI_FUNCTIONS - 1);
-					bdf += PCI_BDF(0, 0, 1)) {
-				pci_read_config_dword(bdf, PCI_CLASS_REVISION,
-						      &class);
-				class >>= 8;
-
-				if (class != find_class)
-					continue;
-				/*
-				 * Decrement the index. We want to return the
-				 * correct device, so index is 0 for the first
-				 * matching device, 1 for the second, etc.
-				 */
-				if (index) {
-					index--;
-					continue;
-				}
-				/* Return index'th controller. */
-				return bdf;
-			}
-		}
-	}
-
-	return -ENODEV;
-}
-
 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 {
 	/*
@@ -141,6 +99,7 @@ __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 	return 0;
 }
 
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
 /* Get a virtual address associated with a BAR region */
 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 {
@@ -363,3 +322,46 @@ pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
 
 	return -1;
 }
+
+pci_dev_t pci_find_class(uint find_class, int index)
+{
+	int bus;
+	int devnum;
+	pci_dev_t bdf;
+	uint32_t class;
+
+	for (bus = 0; bus <= pci_last_busno(); bus++) {
+		for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
+			pci_read_config_dword(PCI_BDF(bus, devnum, 0),
+					      PCI_CLASS_REVISION, &class);
+			if (class >> 16 == 0xffff)
+				continue;
+
+			for (bdf = PCI_BDF(bus, devnum, 0);
+					bdf <= PCI_BDF(bus, devnum,
+						PCI_MAX_PCI_FUNCTIONS - 1);
+					bdf += PCI_BDF(0, 0, 1)) {
+				pci_read_config_dword(bdf, PCI_CLASS_REVISION,
+						      &class);
+				class >>= 8;
+
+				if (class != find_class)
+					continue;
+				/*
+				 * Decrement the index. We want to return the
+				 * correct device, so index is 0 for the first
+				 * matching device, 1 for the second, etc.
+				 */
+				if (index) {
+					index--;
+					continue;
+				}
+				/* Return index'th controller. */
+				return bdf;
+			}
+		}
+	}
+
+	return -ENODEV;
+}
+#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c
index 712c48f28f..dd15eb19f8 100644
--- a/drivers/pci/pci_compat.c
+++ b/drivers/pci/pci_compat.c
@@ -34,5 +34,5 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 
 	if (pci_find_device_id(ids, index, &dev))
 		return -1;
-	return pci_get_bdf(dev);
+	return dm_pci_get_bdf(dev);
 }
diff --git a/drivers/pci/pci_internal.h b/drivers/pci/pci_internal.h
new file mode 100644
index 0000000000..0867575a58
--- /dev/null
+++ b/drivers/pci/pci_internal.h
@@ -0,0 +1,50 @@
+/*
+ * Internal PCI functions, not exported outside drivers/pci
+ *
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __pci_internal_h
+#define __pci_internal_h
+
+/**
+ * dm_pciauto_prescan_setup_bridge() - Set up a bridge for scanning
+ *
+ * This gets a bridge ready so that its downstream devices can be scanned.
+ * It sets up the bus number and memory range registers. Once the scan is
+ * completed, dm_pciauto_postscan_setup_bridge() should be called.
+ *
+ * @dev:	Bridge device to be scanned
+ * @sub_bus:	Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_postscan_setup_bridge() - Finish set up of a bridge after scanning
+ *
+ * This should be called after a bus scan is complete. It adjusts the memory
+ * ranges to fit with the devices actually found on the other side (downstream)
+ * of the bridge.
+ *
+ * @dev:	Bridge device that was scanned
+ * @sub_bus:	Bus number of the 'other side' of the bridge
+ */
+void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus);
+
+/**
+ * dm_pciauto_config_device() - Configure a PCI device ready for use
+ *
+ * If the device is a bridge, downstream devices will be probed.
+ *
+ * @dev:	Device to configure
+ * @return the maximum PCI bus number found by this device. If there are no
+ * bridges, this just returns the device's bus number. If the device is a
+ * bridge then it will return a larger number, depending on the devices on
+ * that bridge. On error, returns a -ve error number.
+ */
+int dm_pciauto_config_device(struct udevice *dev);
+
+#endif
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index ad1167e2b6..2cb81b66b7 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -25,6 +25,7 @@
 
 #include <common.h>
 #include <bios_emul.h>
+#include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <pci.h>
@@ -33,12 +34,12 @@
 #include <video_fb.h>
 #include <linux/screen_info.h>
 
-__weak bool board_should_run_oprom(pci_dev_t dev)
+__weak bool board_should_run_oprom(struct udevice *dev)
 {
 	return true;
 }
 
-static bool should_load_oprom(pci_dev_t dev)
+static bool should_load_oprom(struct udevice *dev)
 {
 	if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
 		return 1;
@@ -53,21 +54,18 @@ __weak uint32_t board_map_oprom_vendev(uint32_t vendev)
 	return vendev;
 }
 
-static int pci_rom_probe(pci_dev_t dev, uint class,
-			 struct pci_rom_header **hdrp)
+static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
 {
+	struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
 	struct pci_rom_header *rom_header;
 	struct pci_rom_data *rom_data;
-	u16 vendor, device;
 	u16 rom_vendor, rom_device;
 	u32 rom_class;
 	u32 vendev;
 	u32 mapped_vendev;
 	u32 rom_address;
 
-	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
-	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
-	vendev = vendor << 16 | device;
+	vendev = pplat->vendor << 16 | pplat->device;
 	mapped_vendev = board_map_oprom_vendev(vendev);
 	if (vendev != mapped_vendev)
 		debug("Device ID mapped to %#08x\n", mapped_vendev);
@@ -76,15 +74,15 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 	rom_address = CONFIG_VGA_BIOS_ADDR;
 #else
 
-	pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
+	dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
 	if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
 		debug("%s: rom_address=%x\n", __func__, rom_address);
 		return -ENOENT;
 	}
 
 	/* Enable expansion ROM address decoding. */
-	pci_write_config_dword(dev, PCI_ROM_ADDRESS,
-			       rom_address | PCI_ROM_ADDRESS_ENABLE);
+	dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
+			      rom_address | PCI_ROM_ADDRESS_ENABLE);
 #endif
 	debug("Option ROM address %x\n", rom_address);
 	rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
@@ -98,7 +96,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 		       le16_to_cpu(rom_header->signature));
 #ifndef CONFIG_VGA_BIOS_ADDR
 		/* Disable expansion ROM address decoding */
-		pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address);
+		dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
 #endif
 		return -EINVAL;
 	}
@@ -111,7 +109,7 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 	      rom_vendor, rom_device);
 
 	/* If the device id is mapped, a mismatch is expected */
-	if ((vendor != rom_vendor || device != rom_device) &&
+	if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
 	    (vendev == mapped_vendev)) {
 		printf("ID mismatch: vendor ID %04x, device ID %04x\n",
 		       rom_vendor, rom_device);
@@ -122,9 +120,9 @@ static int pci_rom_probe(pci_dev_t dev, uint class,
 	debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
 	      rom_class, rom_data->type);
 
-	if (class != rom_class) {
+	if (pplat->class != rom_class) {
 		debug("Class Code mismatch ROM %06x, dev %06x\n",
-		      rom_class, class);
+		      rom_class, pplat->class);
 	}
 	*hdrp = rom_header;
 
@@ -251,27 +249,26 @@ void setup_video(struct screen_info *screen_info)
 	screen_info->rsvd_pos = vesa->reserved_mask_pos;
 }
 
-int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method)
+int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
+			int exec_method)
 {
+	struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
 	struct pci_rom_header *rom, *ram;
 	int vesa_mode = -1;
-	uint class;
 	bool emulate;
 	int ret;
 
 	/* Only execute VGA ROMs */
-	pci_read_config_dword(dev, PCI_REVISION_ID, &class);
-	if (((class >> 16) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
-		debug("%s: Class %#x, should be %#x\n", __func__, class,
+	if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
+		debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
 		      PCI_CLASS_DISPLAY_VGA);
 		return -ENODEV;
 	}
-	class >>= 8;
 
 	if (!should_load_oprom(dev))
 		return -ENXIO;
 
-	ret = pci_rom_probe(dev, class, &rom);
+	ret = pci_rom_probe(dev, &rom);
 	if (ret)
 		return ret;
 
@@ -314,12 +311,12 @@ int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method)
 #ifdef CONFIG_BIOSEMU
 		BE_VGAInfo *info;
 
-		ret = biosemu_setup(dev, &info);
+		ret = biosemu_setup(dm_pci_get_bdf(dev), &info);
 		if (ret)
 			return ret;
 		biosemu_set_interrupt_handler(0x15, int15_handler);
-		ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true,
-				  vesa_mode, &mode_info);
+		ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16,
+				  info, true, vesa_mode, &mode_info);
 		if (ret)
 			return ret;
 #endif
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index f1e189edd5..c14bb0aa82 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -381,7 +381,7 @@ static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
 	ret = imx_pcie_addr_valid(d);
 	if (ret) {
 		*val = 0xffffffff;
-		return ret;
+		return 0;
 	}
 
 	va_address = get_bus_address(d, where);
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 58e88ae45e..99f9c83fa4 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -314,7 +314,7 @@ static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
 
 	if (ls_pcie_addr_valid(hose, d)) {
 		*val = 0xffffffff;
-		return -EINVAL;
+		return 0;
 	}
 
 	if (PCI_BUS(d) == hose->first_busno) {