summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/clk-ti-sci.c5
-rw-r--r--drivers/misc/Kconfig9
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/k3_avs.c388
-rw-r--r--drivers/pci/Kconfig14
-rw-r--r--drivers/pci/Makefile2
-rw-r--r--drivers/pci/pci_mpc85xx.c158
-rw-r--r--drivers/pci/pcie_phytium.c200
-rw-r--r--drivers/power/pmic/Kconfig7
-rw-r--r--drivers/power/pmic/Makefile1
-rw-r--r--drivers/power/pmic/tps65941.c83
-rw-r--r--drivers/power/regulator/Kconfig20
-rw-r--r--drivers/power/regulator/Makefile2
-rw-r--r--drivers/power/regulator/tps62360_regulator.c123
-rw-r--r--drivers/power/regulator/tps65941_regulator.c407
15 files changed, 1420 insertions, 0 deletions
diff --git a/drivers/clk/clk-ti-sci.c b/drivers/clk/clk-ti-sci.c
index c25415d410..478349f22f 100644
--- a/drivers/clk/clk-ti-sci.c
+++ b/drivers/clk/clk-ti-sci.c
@@ -13,6 +13,7 @@
#include <errno.h>
#include <clk-uclass.h>
#include <linux/soc/ti/ti_sci_protocol.h>
+#include <k3-avs.h>
/**
* struct ti_sci_clk_data - clock controller information structure
@@ -101,6 +102,10 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate)
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
+#ifdef CONFIG_K3_AVS0
+ k3_avs_notify_freq(clk->id, clk->data, rate);
+#endif
+
/* Ask for exact frequency by using same value for min/target/max */
ret = cops->set_freq(sci, clk->id, clk->data, rate, rate, rate);
if (ret)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4985ea033b..7a8ba587da 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -421,4 +421,13 @@ config MICROCHIP_FLEXCOM
Only one function can be used at a time and is chosen at boot time
according to the device tree.
+config K3_AVS0
+ depends on ARCH_K3 && SPL_DM_REGULATOR
+ bool "AVS class 0 support for K3 devices"
+ help
+ K3 devices have the optimized voltage values for the main voltage
+ domains stored in efuse within the VTM IP. This driver reads the
+ optimized voltage from the efuse, so that it can be programmed
+ to the PMIC on board.
+
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f61263640b..870655e802 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -66,3 +66,4 @@ obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
+obj-$(CONFIG_K3_AVS0) += k3_avs.o
diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c
new file mode 100644
index 0000000000..c19c3c0646
--- /dev/null
+++ b/drivers/misc/k3_avs.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' K3 Clas 0 Adaptive Voltage Scaling driver
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <k3-avs.h>
+#include <power/regulator.h>
+
+#define AM6_VTM_DEVINFO(i) (priv->base + 0x100 + 0x20 * (i))
+#define AM6_VTM_OPPVID_VD(i) (priv->base + 0x104 + 0x20 * (i))
+
+#define AM6_VTM_AVS0_SUPPORTED BIT(12)
+
+#define AM6_VTM_OPP_SHIFT(opp) (8 * (opp))
+#define AM6_VTM_OPP_MASK 0xff
+
+#define VD_FLAG_INIT_DONE BIT(0)
+
+struct k3_avs_privdata {
+ void *base;
+ struct vd_config *vd_config;
+};
+
+struct opp {
+ u32 freq;
+ u32 volt;
+};
+
+struct vd_data {
+ int id;
+ u8 opp;
+ u8 flags;
+ int dev_id;
+ int clk_id;
+ struct opp opps[NUM_OPPS];
+ struct udevice *supply;
+};
+
+struct vd_config {
+ struct vd_data *vds;
+ u32 (*efuse_xlate)(struct k3_avs_privdata *priv, int idx, int opp);
+};
+
+static struct k3_avs_privdata *k3_avs_priv;
+
+/**
+ * am6_efuse_voltage: read efuse voltage from VTM
+ * @priv: driver private data
+ * @idx: VD to read efuse for
+ * @opp: opp id to read
+ *
+ * Reads efuse value for the specified OPP, and converts the register
+ * value to a voltage. Returns the voltage in uV, or 0 if nominal voltage
+ * should be used.
+ *
+ * Efuse val to volt conversion logic:
+ *
+ * val > 171 volt increments in 20mV steps with base 171 => 1.66V
+ * val between 115 to 11 increments in 10mV steps with base 115 => 1.1V
+ * val between 15 to 115 increments in 5mV steps with base 15 => .6V
+ * val between 1 to 15 increments in 20mv steps with base 0 => .3V
+ * val 0 is invalid
+ */
+static u32 am6_efuse_xlate(struct k3_avs_privdata *priv, int idx, int opp)
+{
+ u32 val = readl(AM6_VTM_OPPVID_VD(idx));
+
+ val >>= AM6_VTM_OPP_SHIFT(opp);
+ val &= AM6_VTM_OPP_MASK;
+
+ if (!val)
+ return 0;
+
+ if (val > 171)
+ return 1660000 + 20000 * (val - 171);
+
+ if (val > 115)
+ return 1100000 + 10000 * (val - 115);
+
+ if (val > 15)
+ return 600000 + 5000 * (val - 15);
+
+ return 300000 + 20000 * val;
+}
+
+static int k3_avs_program_voltage(struct k3_avs_privdata *priv,
+ struct vd_data *vd,
+ int opp_id)
+{
+ u32 volt = vd->opps[opp_id].volt;
+ struct vd_data *vd2;
+
+ if (!vd->supply)
+ return -ENODEV;
+
+ vd->opp = opp_id;
+ vd->flags |= VD_FLAG_INIT_DONE;
+
+ /* Take care of ganged rails and pick the Max amongst them*/
+ for (vd2 = priv->vd_config->vds; vd2->id >= 0; vd2++) {
+ if (vd == vd2)
+ continue;
+
+ if (vd2->supply != vd->supply)
+ continue;
+
+ if (vd2->opps[vd2->opp].volt > volt)
+ volt = vd2->opps[vd2->opp].volt;
+
+ vd2->flags |= VD_FLAG_INIT_DONE;
+ }
+
+ return regulator_set_value(vd->supply, volt);
+}
+
+static struct vd_data *get_vd(struct k3_avs_privdata *priv, int idx)
+{
+ struct vd_data *vd;
+
+ for (vd = priv->vd_config->vds; vd->id >= 0 && vd->id != idx; vd++)
+ ;
+
+ if (vd->id < 0)
+ return NULL;
+
+ return vd;
+}
+
+/**
+ * k3_avs_set_opp: Sets the voltage for an arbitrary VD rail
+ * @dev: AVS device
+ * @vdd_id: voltage domain ID
+ * @opp_id: OPP ID
+ *
+ * Programs the desired OPP value for the defined voltage rail. This
+ * should be called from board files if reconfiguration is desired.
+ * Returns 0 on success, negative error value on failure.
+ */
+int k3_avs_set_opp(struct udevice *dev, int vdd_id, int opp_id)
+{
+ struct k3_avs_privdata *priv = dev_get_priv(dev);
+ struct vd_data *vd;
+
+ vd = get_vd(priv, vdd_id);
+ if (!vd)
+ return -EINVAL;
+
+ return k3_avs_program_voltage(priv, vd, opp_id);
+}
+
+static int match_opp(struct vd_data *vd, u32 freq)
+{
+ struct opp *opp;
+ int opp_id;
+
+ for (opp_id = 0; opp_id < NUM_OPPS; opp_id++) {
+ opp = &vd->opps[opp_id];
+ if (opp->freq == freq)
+ return opp_id;
+ }
+
+ printf("No matching OPP found for freq %d.\n", freq);
+
+ return -EINVAL;
+}
+
+/**
+ * k3_avs_notify_freq: Notify clock rate change towards AVS subsystem
+ * @dev_id: Device ID for the clock to be changed
+ * @clk_id: Clock ID for the clock to be changed
+ * @freq: New frequency for clock
+ *
+ * Checks if the provided clock is the MPU clock or not, if not, return
+ * immediately. If MPU clock is provided, maps the provided MPU frequency
+ * towards an MPU OPP, and programs the voltage to the regulator. Return 0
+ * on success, negative error value on failure.
+ */
+int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq)
+{
+ int opp_id;
+ struct k3_avs_privdata *priv = k3_avs_priv;
+ struct vd_data *vd;
+
+ for (vd = priv->vd_config->vds; vd->id >= 0; vd++) {
+ if (vd->dev_id != dev_id || vd->clk_id != clk_id)
+ continue;
+
+ opp_id = match_opp(vd, freq);
+ if (opp_id < 0)
+ return opp_id;
+
+ vd->opp = opp_id;
+ return k3_avs_program_voltage(priv, vd, opp_id);
+ }
+
+ return -EINVAL;
+}
+
+static int k3_avs_configure(struct udevice *dev, struct k3_avs_privdata *priv)
+{
+ struct vd_config *conf;
+ int ret;
+ char pname[20];
+ struct vd_data *vd;
+
+ conf = (void *)dev_get_driver_data(dev);
+
+ priv->vd_config = conf;
+
+ for (vd = conf->vds; vd->id >= 0; vd++) {
+ sprintf(pname, "vdd-supply-%d", vd->id);
+ ret = device_get_supply_regulator(dev, pname, &vd->supply);
+ if (ret)
+ dev_warn(dev, "supply not found for VD%d.\n", vd->id);
+
+ sprintf(pname, "ti,default-opp-%d", vd->id);
+ ret = dev_read_u32_default(dev, pname, -1);
+ if (ret != -1)
+ vd->opp = ret;
+ }
+
+ return 0;
+}
+
+/**
+ * k3_avs_probe: parses VD info from VTM, and re-configures the OPP data
+ *
+ * Parses all VDs on a device calculating the AVS class-0 voltages for them,
+ * and updates the vd_data based on this. The vd_data itself shall be used
+ * to program the required OPPs later on. Returns 0 on success, negative
+ * error value on failure.
+ */
+static int k3_avs_probe(struct udevice *dev)
+{
+ int opp_id;
+ u32 volt;
+ struct opp *opp;
+ struct k3_avs_privdata *priv;
+ struct vd_data *vd;
+ int ret;
+
+ priv = dev_get_priv(dev);
+
+ k3_avs_priv = priv;
+
+ ret = k3_avs_configure(dev, priv);
+ if (ret)
+ return ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENODEV;
+
+ for (vd = priv->vd_config->vds; vd->id >= 0; vd++) {
+ if (!(readl(AM6_VTM_DEVINFO(vd->id)) &
+ AM6_VTM_AVS0_SUPPORTED)) {
+ dev_warn(dev, "AVS-class 0 not supported for VD%d\n",
+ vd->id);
+ continue;
+ }
+
+ for (opp_id = 0; opp_id < NUM_OPPS; opp_id++) {
+ opp = &vd->opps[opp_id];
+
+ if (!opp->freq)
+ continue;
+
+ volt = priv->vd_config->efuse_xlate(priv, vd->id,
+ opp_id);
+ if (volt)
+ opp->volt = volt;
+ }
+ }
+
+ for (vd = priv->vd_config->vds; vd->id >= 0; vd++) {
+ if (vd->flags & VD_FLAG_INIT_DONE)
+ continue;
+
+ k3_avs_program_voltage(priv, vd, vd->opp);
+ }
+
+ return 0;
+}
+
+static struct vd_data am654_vd_data[] = {
+ {
+ .id = AM6_VDD_CORE,
+ .dev_id = 82, /* AM6_DEV_CBASS0 */
+ .clk_id = 0, /* main sysclk0 */
+ .opp = AM6_OPP_NOM,
+ .opps = {
+ [AM6_OPP_NOM] = {
+ .volt = 1000000,
+ .freq = 250000000, /* CBASS0 */
+ },
+ },
+ },
+ {
+ .id = AM6_VDD_MPU0,
+ .dev_id = 202, /* AM6_DEV_COMPUTE_CLUSTER_A53_0 */
+ .clk_id = 0, /* ARM clock */
+ .opp = AM6_OPP_NOM,
+ .opps = {
+ [AM6_OPP_NOM] = {
+ .volt = 1000000,
+ .freq = 800000000,
+ },
+ [AM6_OPP_OD] = {
+ .volt = 1100000,
+ .freq = 1000000000,
+ },
+ [AM6_OPP_TURBO] = {
+ .volt = 1220000,
+ .freq = 1100000000,
+ },
+ },
+ },
+ {
+ .id = AM6_VDD_MPU1,
+ .opp = AM6_OPP_NOM,
+ .dev_id = 204, /* AM6_DEV_COMPUTE_CLUSTER_A53_2 */
+ .clk_id = 0, /* ARM clock */
+ .opps = {
+ [AM6_OPP_NOM] = {
+ .volt = 1000000,
+ .freq = 800000000,
+ },
+ [AM6_OPP_OD] = {
+ .volt = 1100000,
+ .freq = 1000000000,
+ },
+ [AM6_OPP_TURBO] = {
+ .volt = 1220000,
+ .freq = 1100000000,
+ },
+ },
+ },
+ { .id = -1 },
+};
+
+static struct vd_data j721e_vd_data[] = {
+ {
+ .id = J721E_VDD_MPU,
+ .opp = AM6_OPP_NOM,
+ .dev_id = 202, /* J721E_DEV_A72SS0_CORE0 */
+ .clk_id = 2, /* ARM clock */
+ .opps = {
+ [AM6_OPP_NOM] = {
+ .volt = 880000, /* TBD in DM */
+ .freq = 2000000000,
+ },
+ },
+ },
+ { .id = -1 },
+};
+
+static struct vd_config j721e_vd_config = {
+ .efuse_xlate = am6_efuse_xlate,
+ .vds = j721e_vd_data,
+};
+
+static struct vd_config am654_vd_config = {
+ .efuse_xlate = am6_efuse_xlate,
+ .vds = am654_vd_data,
+};
+
+static const struct udevice_id k3_avs_ids[] = {
+ { .compatible = "ti,am654-avs", .data = (ulong)&am654_vd_config },
+ { .compatible = "ti,j721e-avs", .data = (ulong)&j721e_vd_config },
+ {}
+};
+
+U_BOOT_DRIVER(k3_avs) = {
+ .name = "k3_avs",
+ .of_match = k3_avs_ids,
+ .id = UCLASS_MISC,
+ .probe = k3_avs_probe,
+ .priv_auto_alloc_size = sizeof(struct k3_avs_privdata),
+};
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 19e7b50046..13603b9d57 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -51,6 +51,13 @@ config PCIE_ECAM_GENERIC
Say Y here if you want to enable support for generic ECAM-based
PCIe host controllers, such as the one emulated by QEMU.
+config PCI_PHYTIUM
+ bool "Phytium PCIe support"
+ depends on DM_PCI
+ help
+ Say Y here if you want to enable PCIe controller support on
+ Phytium SoCs.
+
config PCIE_DW_MVEBU
bool "Enable Armada-8K PCIe driver (DesignWare core)"
depends on DM_PCI
@@ -68,6 +75,13 @@ config PCIE_FSL
PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
This driver does not support SRIO_PCIE_BOOT feature.
+config PCI_MPC85XX
+ bool "MPC85XX PowerPC PCI support"
+ depends on DM_PCI
+ help
+ Say Y here if you want to enable PCI controller support on FSL
+ PowerPC MPC85xx SoC.
+
config PCI_RCAR_GEN2
bool "Renesas RCar Gen2 PCIe driver"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index b1d3dc8610..219473aa79 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
+obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
@@ -37,6 +38,7 @@ obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
pcie_layerscape_gen4_fixup.o
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
+obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c
new file mode 100644
index 0000000000..e58ab60ee0
--- /dev/null
+++ b/drivers/pci/pci_mpc85xx.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ */
+#include <common.h>
+#include <asm/cpm_85xx.h>
+#include <pci.h>
+#include <dm.h>
+#include <asm/fsl_law.h>
+
+struct mpc85xx_pci_priv {
+ void __iomem *cfg_addr;
+ void __iomem *cfg_data;
+};
+
+static int mpc85xx_pci_dm_read_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong *value,
+ enum pci_size_t size)
+{
+ struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+ u32 addr;
+
+ addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
+ out_be32(priv->cfg_addr, addr);
+ sync();
+ *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
+
+ return 0;
+}
+
+static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+ u32 addr;
+
+ addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
+ out_be32(priv->cfg_addr, addr);
+ sync();
+ out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
+
+ return 0;
+}
+
+static int
+mpc85xx_pci_dm_setup_laws(struct pci_region *io, struct pci_region *mem,
+ struct pci_region *pre)
+{
+ /*
+ * Unfortunately we have defines for this addresse,
+ * as we have to setup the TLB, and at this stage
+ * we have no access to DT ... may we check here
+ * if the value in the define is the same ?
+ */
+ if (mem)
+ set_next_law(mem->phys_start, law_size_bits(mem->size),
+ LAW_TRGT_IF_PCI);
+ if (io)
+ set_next_law(io->phys_start, law_size_bits(io->size),
+ LAW_TRGT_IF_PCI);
+ if (pre)
+ set_next_law(pre->phys_start, law_size_bits(pre->size),
+ LAW_TRGT_IF_PCI);
+
+ return 0;
+}
+
+static int mpc85xx_pci_dm_probe(struct udevice *dev)
+{
+ struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+ struct pci_region *io;
+ struct pci_region *mem;
+ struct pci_region *pre;
+ int count;
+ ccsr_pcix_t *pcix;
+
+ count = pci_get_regions(dev, &io, &mem, &pre);
+ if (count != 2) {
+ printf("%s: wrong count of regions %d only 2 allowed\n",
+ __func__, count);
+ return -EINVAL;
+ }
+
+ mpc85xx_pci_dm_setup_laws(io, mem, pre);
+
+ pcix = priv->cfg_addr;
+ /* BAR 1: memory */
+ out_be32(&pcix->potar1, (mem->bus_start >> 12) & 0x000fffff);
+ out_be32(&pcix->potear1, 0);
+ out_be32(&pcix->powbar1, (mem->phys_start >> 12) & 0x000fffff);
+ out_be32(&pcix->powbear1, 0);
+ out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
+ POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
+
+ /* BAR 1: IO */
+ out_be32(&pcix->potar2, (io->bus_start >> 12) & 0x000fffff);
+ out_be32(&pcix->potear2, 0);
+ out_be32(&pcix->powbar2, (io->phys_start >> 12) & 0x000fffff);
+ out_be32(&pcix->powbear2, 0);
+ out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
+ POWAR_IO_WRITE | (__ilog2(io->size) - 1)));
+
+ out_be32(&pcix->pitar1, 0);
+ out_be32(&pcix->piwbar1, 0);
+ out_be32(&pcix->piwar1, (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
+ PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G));
+
+ out_be32(&pcix->powar3, 0);
+ out_be32(&pcix->powar4, 0);
+ out_be32(&pcix->piwar2, 0);
+ out_be32(&pcix->piwar3, 0);
+
+ return 0;
+}
+
+static int mpc85xx_pci_dm_remove(struct udevice *dev)
+{
+ return 0;
+}
+
+static int mpc85xx_pci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->cfg_addr = (void __iomem *)addr;
+ addr += 4;
+ priv->cfg_data = (void __iomem *)addr;
+
+ return 0;
+}
+
+static const struct dm_pci_ops mpc85xx_pci_ops = {
+ .read_config = mpc85xx_pci_dm_read_config,
+ .write_config = mpc85xx_pci_dm_write_config,
+};
+
+static const struct udevice_id mpc85xx_pci_ids[] = {
+ { .compatible = "fsl,mpc8540-pci" },
+ { }
+};
+
+U_BOOT_DRIVER(mpc85xx_pci) = {
+ .name = "mpc85xx_pci",
+ .id = UCLASS_PCI,
+ .of_match = mpc85xx_pci_ids,
+ .ops = &mpc85xx_pci_ops,
+ .probe = mpc85xx_pci_dm_probe,
+ .remove = mpc85xx_pci_dm_remove,
+ .ofdata_to_platdata = mpc85xx_pci_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct mpc85xx_pci_priv),
+};
diff --git a/drivers/pci/pcie_phytium.c b/drivers/pci/pcie_phytium.c
new file mode 100644
index 0000000000..92e281e7c2
--- /dev/null
+++ b/drivers/pci/pcie_phytium.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium PCIE host driver
+ *
+ * Heavily based on drivers/pci/pcie_xilinx.c
+ *
+ * Copyright (C) 2019
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <asm/io.h>
+
+/**
+ * struct phytium_pcie - phytium PCIe controller state
+ * @cfg_base: The base address of memory mapped configuration space
+ */
+struct phytium_pcie {
+ void *cfg_base;
+};
+
+/*
+ * phytium_pci_skip_dev()
+ * @parent: Identifies the PCIe device to access
+ *
+ * Checks whether the parent of the PCIe device is bridge
+ *
+ * Return: true if it is bridge, else false.
+ */
+static int phytium_pci_skip_dev(pci_dev_t parent)
+{
+ unsigned char pos, id;
+ unsigned long addr = 0x40000000;
+ unsigned short capreg;
+ unsigned char port_type;
+
+ addr += PCI_BUS(parent) << 20;
+ addr += PCI_DEV(parent) << 15;
+ addr += PCI_FUNC(parent) << 12;
+
+ pos = 0x34;
+ while (1) {
+ pos = readb(addr + pos);
+ if (pos < 0x40)
+ break;
+ pos &= ~3;
+ id = readb(addr + pos);
+ if (id == 0xff)
+ break;
+ if (id == 0x10) {
+ capreg = readw(addr + pos + 2);
+ port_type = (capreg >> 4) & 0xf;
+ if (port_type == 0x6 || port_type == 0x4)
+ return 1;
+ else
+ return 0;
+ }
+ pos += 1;
+ }
+ return 0;
+}
+
+/**
+ * pci_phytium_conf_address() - Calculate the address of a config access
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @paddress: Pointer to the pointer to write the calculates address to
+ *
+ * Calculates the address that should be accessed to perform a PCIe
+ * configuration space access for a given device identified by the PCIe
+ * controller device @pcie and the bus, device & function numbers in @bdf. If
+ * access to the device is not valid then the function will return an error
+ * code. Otherwise the address to access will be written to the pointer pointed
+ * to by @paddress.
+ */
+static int pci_phytium_conf_address(struct udevice *bus, pci_dev_t bdf,
+ uint offset,
+ void **paddress)
+{
+ struct phytium_pcie *pcie = dev_get_priv(bus);
+ void *addr;
+ pci_dev_t bdf_parent;
+
+ unsigned int bus_no = PCI_BUS(bdf);
+ unsigned int dev_no = PCI_DEV(bdf);
+
+ bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
+
+ addr = pcie->cfg_base;
+ addr += PCI_BUS(bdf) << 20;
+ addr += PCI_DEV(bdf) << 15;
+ addr += PCI_FUNC(bdf) << 12;
+
+ if (bus_no > 0 && dev_no > 0) {
+ if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
+ PCI_HEADER_TYPE_BRIDGE)
+ return -ENODEV;
+ if (phytium_pci_skip_dev(bdf_parent))
+ return -ENODEV;
+ }
+
+ addr += offset;
+ *paddress = addr;
+
+ return 0;
+}
+
+/**
+ * pci_phytium_read_config() - Read from configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus.
+ */
+static int pci_phytium_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ return pci_generic_mmap_read_config(bus, pci_phytium_conf_address,
+ bdf, offset, valuep, size);
+}
+
+/**
+ * pci_phytium_write_config() - Write to configuration space
+ * @bus: Pointer to the PCI bus
+ * @bdf: Identifies the PCIe device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus.
+ */
+static int pci_phytium_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ return pci_generic_mmap_write_config(bus, pci_phytium_conf_address,
+ bdf, offset, value, size);
+}
+
+/**
+ * pci_phytium_ofdata_to_platdata() - Translate from DT to device state
+ * @dev: A pointer to the device being operated on
+ *
+ * Translate relevant data from the device tree pertaining to device @dev into
+ * state that the driver will later make use of. This state is stored in the
+ * device's private data structure.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+static int pci_phytium_ofdata_to_platdata(struct udevice *dev)
+{
+ struct phytium_pcie *pcie = dev_get_priv(dev);
+ struct fdt_resource reg_res;
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int err;
+
+ err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
+ 0, &reg_res);
+ if (err < 0) {
+ pr_err("\"reg\" resource not found\n");
+ return err;
+ }
+
+ pcie->cfg_base = map_physmem(reg_res.start,
+ fdt_resource_size(&reg_res),
+ MAP_NOCACHE);
+
+ return 0;
+}
+
+static const struct dm_pci_ops pci_phytium_ops = {
+ .read_config = pci_phytium_read_config,
+ .write_config = pci_phytium_write_config,
+};
+
+static const struct udevice_id pci_phytium_ids[] = {
+ { .compatible = "phytium,pcie-host-1.0" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_phytium) = {
+ .name = "pci_phytium",
+ .id = UCLASS_PCI,
+ .of_match = pci_phytium_ids,
+ .ops = &pci_phytium_ops,
+ .ofdata_to_platdata = pci_phytium_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct phytium_pcie),
+};
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 4718dc700c..b4bf018674 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -275,3 +275,10 @@ config SPL_PMIC_LP87565
help
The LP87565 is a PMIC containing a bunch of SMPS.
This driver binds the pmic children in SPL.
+
+config PMIC_TPS65941
+ bool "Enable driver for Texas Instruments TPS65941 PMIC"
+ depends on DM_PMIC
+ help
+ The TPS65941 is a PMIC containing a bunch of SMPS & LDOs.
+ This driver binds the pmic children.
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 888dbb2857..ec64327805 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o
obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o
+obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c
new file mode 100644
index 0000000000..e8f3c950bd
--- /dev/null
+++ b/drivers/power/pmic/tps65941.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/tps65941.h>
+#include <dm/device.h>
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "ldo", .driver = TPS65941_LDO_DRIVER },
+ { .prefix = "buck", .driver = TPS65941_BUCK_DRIVER },
+ { },
+};
+
+static int tps65941_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ if (dm_i2c_write(dev, reg, buff, len)) {
+ pr_err("write error to device: %p register: %#x!\n", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int tps65941_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ if (dm_i2c_read(dev, reg, buff, len)) {
+ pr_err("read error from device: %p register: %#x!\n", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int tps65941_bind(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found!\n", __func__,
+ dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ printf("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops tps65941_ops = {
+ .read = tps65941_read,
+ .write = tps65941_write,
+};
+
+static const struct udevice_id tps65941_ids[] = {
+ { .compatible = "ti,tps659411", .data = TPS659411 },
+ { .compatible = "ti,tps659413", .data = TPS659413 },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_tps65941) = {
+ .name = "tps65941_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = tps65941_ids,
+ .bind = tps65941_bind,
+ .ops = &tps65941_ops,
+};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 9aa00fad42..25fc787a29 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -273,6 +273,16 @@ config DM_REGULATOR_TPS65910
regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements
the get/set api for value and enable.
+config DM_REGULATOR_TPS62360
+ bool "Enable driver for TPS6236x Power Regulator"
+ depends on DM_REGULATOR
+ help
+ The TPS6236X DC/DC step down converter provides a single output
+ power line peaking at 3A current. This driver supports all four
+ variants of the chip (TPS62360, TPS62361, TPS62362, TPS62363). It
+ implements the get/set api for value only, as the power line is
+ always on.
+
config DM_REGULATOR_STPMIC1
bool "Enable driver for STPMIC1 regulators"
depends on DM_REGULATOR && PMIC_STPMIC1
@@ -313,3 +323,13 @@ config SPL_DM_REGULATOR_LP873X
This enables implementation of driver-model regulator uclass
features for REGULATOR LP873X and the family of LP873X PMICs.
The driver implements get/set api for: value and enable in SPL.
+
+config DM_REGULATOR_TPS65941
+ bool "Enable driver for TPS65941 PMIC regulators"
+ depends on PMIC_TPS65941
+ help
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR TPS65941 and the family of TPS65941 PMICs.
+ TPS65941 series of PMICs have 5 single phase BUCKs that can also
+ be configured in multi phase modes & 4 LDOs. The driver implements
+ get/set api for value and enable.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 6a3d4bbee4..b611c901ba 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -26,4 +26,6 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o
obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
+obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o
+obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o
diff --git a/drivers/power/regulator/tps62360_regulator.c b/drivers/power/regulator/tps62360_regulator.c
new file mode 100644
index 0000000000..3b123f503c
--- /dev/null
+++ b/drivers/power/regulator/tps62360_regulator.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/regulator.h>
+
+#define TPS62360_REG_SET0 0
+
+#define TPS62360_I2C_CHIP 0x60
+
+#define TPS62360_VSEL_STEPSIZE 10000 /* In uV */
+
+struct tps62360_regulator_config {
+ u32 vmin;
+ u32 vmax;
+};
+
+struct tps62360_regulator_pdata {
+ u8 vsel_offset;
+ struct udevice *i2c;
+ struct tps62360_regulator_config *config;
+};
+
+/*
+ * TPS62362/TPS62363 are just re-using these values for now, their preset
+ * voltage values are just different compared to TPS62360/TPS62361.
+ */
+static struct tps62360_regulator_config tps62360_data = {
+ .vmin = 770000,
+ .vmax = 1400000,
+};
+
+static struct tps62360_regulator_config tps62361_data = {
+ .vmin = 500000,
+ .vmax = 1770000,
+};
+
+static int tps62360_regulator_set_value(struct udevice *dev, int uV)
+{
+ struct tps62360_regulator_pdata *pdata = dev_get_platdata(dev);
+ u8 regval;
+
+ if (uV < pdata->config->vmin || uV > pdata->config->vmax)
+ return -EINVAL;
+
+ uV -= pdata->config->vmin;
+
+ uV = DIV_ROUND_UP(uV, TPS62360_VSEL_STEPSIZE);
+
+ if (uV > U8_MAX)
+ return -EINVAL;
+
+ regval = (u8)uV;
+
+ return dm_i2c_write(pdata->i2c, TPS62360_REG_SET0 + pdata->vsel_offset,
+ &regval, 1);
+}
+
+static int tps62360_regulator_get_value(struct udevice *dev)
+{
+ u8 regval;
+ int ret;
+ struct tps62360_regulator_pdata *pdata = dev_get_platdata(dev);
+
+ ret = dm_i2c_read(pdata->i2c, TPS62360_REG_SET0 + pdata->vsel_offset,
+ &regval, 1);
+ if (ret) {
+ dev_err(dev, "i2c read failed: %d\n", ret);
+ return ret;
+ }
+
+ return (u32)regval * TPS62360_VSEL_STEPSIZE + pdata->config->vmin;
+}
+
+static int tps62360_regulator_ofdata_to_platdata(struct udevice *dev)
+{
+ struct tps62360_regulator_pdata *pdata = dev_get_platdata(dev);
+ u8 vsel0;
+ u8 vsel1;
+ int ret;
+
+ pdata->config = (void *)dev_get_driver_data(dev);
+
+ vsel0 = dev_read_bool(dev, "ti,vsel0-state-high");
+ vsel1 = dev_read_bool(dev, "ti,vsel1-state-high");
+
+ pdata->vsel_offset = vsel0 + vsel1 * 2;
+
+ ret = i2c_get_chip(dev->parent, TPS62360_I2C_CHIP, 1, &pdata->i2c);
+ if (ret) {
+ dev_err(dev, "i2c dev get failed.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dm_regulator_ops tps62360_regulator_ops = {
+ .get_value = tps62360_regulator_get_value,
+ .set_value = tps62360_regulator_set_value,
+};
+
+static const struct udevice_id tps62360_regulator_ids[] = {
+ { .compatible = "ti,tps62360", .data = (ulong)&tps62360_data },
+ { .compatible = "ti,tps62361", .data = (ulong)&tps62361_data },
+ { .compatible = "ti,tps62362", .data = (ulong)&tps62360_data },
+ { .compatible = "ti,tps62363", .data = (ulong)&tps62361_data },
+ { },
+};
+
+U_BOOT_DRIVER(tps62360_regulator) = {
+ .name = "tps62360_regulator",
+ .id = UCLASS_REGULATOR,
+ .ops = &tps62360_regulator_ops,
+ .of_match = tps62360_regulator_ids,
+ .platdata_auto_alloc_size = sizeof(struct tps62360_regulator_pdata),
+ .ofdata_to_platdata = tps62360_regulator_ofdata_to_platdata,
+};
diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c
new file mode 100644
index 0000000000..a00ef58129
--- /dev/null
+++ b/drivers/power/regulator/tps65941_regulator.c
@@ -0,0 +1,407 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Keerthy <j-keerthy@ti.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/tps65941.h>
+
+static const char tps65941_buck_ctrl[TPS65941_BUCK_NUM] = {0x4, 0x6, 0x8, 0xA,
+ 0xC};
+static const char tps65941_buck_vout[TPS65941_BUCK_NUM] = {0xE, 0x10, 0x12,
+ 0x14, 0x16};
+static const char tps65941_ldo_ctrl[TPS65941_BUCK_NUM] = {0x1D, 0x1E, 0x1F,
+ 0x20};
+static const char tps65941_ldo_vout[TPS65941_BUCK_NUM] = {0x23, 0x24, 0x25,
+ 0x26};
+
+static int tps65941_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= TPS65941_BUCK_MODE_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= TPS65941_BUCK_MODE_MASK;
+ else
+ ret &= ~TPS65941_BUCK_MODE_MASK;
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tps65941_buck_volt2val(int uV)
+{
+ if (uV > TPS65941_BUCK_VOLT_MAX)
+ return -EINVAL;
+ else if (uV > 1650000)
+ return (uV - 1660000) / 20000 + 0xAB;
+ else if (uV > 1110000)
+ return (uV - 1110000) / 10000 + 0x73;
+ else if (uV > 600000)
+ return (uV - 600000) / 5000 + 0x0F;
+ else if (uV >= 300000)
+ return (uV - 300000) / 20000 + 0x00;
+ else
+ return -EINVAL;
+}
+
+static int tps65941_buck_val2volt(int val)
+{
+ if (val > TPS65941_BUCK_VOLT_MAX_HEX)
+ return -EINVAL;
+ else if (val > 0xAB)
+ return 1660000 + (val - 0xAB) * 20000;
+ else if (val > 0x73)
+ return 1100000 + (val - 0x73) * 10000;
+ else if (val > 0xF)
+ return 600000 + (val - 0xF) * 5000;
+ else if (val >= 0x0)
+ return 300000 + val * 5000;
+ else
+ return -EINVAL;
+}
+
+int tps65941_lookup_slew(int id)
+{
+ switch (id) {
+ case 0:
+ return 33000;
+ case 1:
+ return 20000;
+ case 2:
+ return 10000;
+ case 3:
+ return 5000;
+ case 4:
+ return 2500;
+ case 5:
+ return 1300;
+ case 6:
+ return 630;
+ case 7:
+ return 310;
+ default:
+ return -1;
+ }
+}
+
+static int tps65941_buck_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret, delta, uwait, slew;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ ret &= TPS65941_BUCK_VOLT_MASK;
+ ret = tps65941_buck_val2volt(ret);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ *uV = ret;
+ return 0;
+ }
+
+ /*
+ * Compute the delta voltage, find the slew rate and wait
+ * for the appropriate amount of time after voltage switch
+ */
+ if (*uV > ret)
+ delta = *uV - ret;
+ else
+ delta = ret - *uV;
+
+ slew = pmic_reg_read(dev->parent, uc_pdata->ctrl_reg + 1);
+ if (slew < 0)
+ return ret;
+
+ slew &= TP65941_BUCK_CONF_SLEW_MASK;
+ slew = tps65941_lookup_slew(slew);
+ if (slew <= 0)
+ return ret;
+
+ uwait = delta / slew;
+
+ hex = tps65941_buck_volt2val(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= 0x0;
+ ret = hex;
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+
+ udelay(uwait);
+
+ return ret;
+}
+
+static int tps65941_ldo_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= TPS65941_LDO_MODE_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= TPS65941_LDO_MODE_MASK;
+ else
+ ret &= ~TPS65941_LDO_MODE_MASK;
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tps65941_ldo_val2volt(int val)
+{
+ if (val > TPS65941_LDO_VOLT_MAX_HEX || val < TPS65941_LDO_VOLT_MIN_HEX)
+ return -EINVAL;
+ else if (val >= TPS65941_LDO_VOLT_MIN_HEX)
+ return 600000 + (val - TPS65941_LDO_VOLT_MIN_HEX) * 50000;
+ else
+ return -EINVAL;
+}
+
+static int tps65941_ldo_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ ret &= TPS65941_LDO_VOLT_MASK;
+ ret = tps65941_ldo_val2volt(ret);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ *uV = ret;
+ return 0;
+ }
+
+ hex = tps65941_buck_volt2val(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= 0x0;
+ ret = hex;
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+
+ return ret;
+}
+
+static int tps65941_ldo_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ int idx;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_LDO;
+
+ idx = dev->driver_data;
+ if (idx == 1 || idx == 2 || idx == 3 || idx == 4) {
+ debug("Single phase regulator\n");
+ } else {
+ printf("Wrong ID for regulator\n");
+ return -EINVAL;
+ }
+
+ uc_pdata->ctrl_reg = tps65941_ldo_ctrl[idx - 1];
+ uc_pdata->volt_reg = tps65941_ldo_vout[idx - 1];
+
+ return 0;
+}
+
+static int tps65941_buck_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ int idx;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ idx = dev->driver_data;
+ if (idx == 1 || idx == 2 || idx == 3 || idx == 4 || idx == 5) {
+ debug("Single phase regulator\n");
+ } else if (idx == 12) {
+ idx = 1;
+ } else if (idx == 34) {
+ idx = 3;
+ } else if (idx == 1234) {
+ idx = 1;
+ } else {
+ printf("Wrong ID for regulator\n");
+ return -EINVAL;
+ }
+
+ uc_pdata->ctrl_reg = tps65941_buck_ctrl[idx - 1];
+ uc_pdata->volt_reg = tps65941_buck_vout[idx - 1];
+
+ return 0;
+}
+
+static int ldo_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = tps65941_ldo_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int ldo_set_value(struct udevice *dev, int uV)
+{
+ return tps65941_ldo_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int ldo_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = tps65941_ldo_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int ldo_set_enable(struct udevice *dev, bool enable)
+{
+ return tps65941_ldo_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static int buck_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = tps65941_buck_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int buck_set_value(struct udevice *dev, int uV)
+{
+ return tps65941_buck_val(dev, PMIC_OP_SET, &uV);
+}
+
+static int buck_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+ ret = tps65941_buck_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int buck_set_enable(struct udevice *dev, bool enable)
+{
+ return tps65941_buck_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops tps65941_ldo_ops = {
+ .get_value = ldo_get_value,
+ .set_value = ldo_set_value,
+ .get_enable = ldo_get_enable,
+ .set_enable = ldo_set_enable,
+};
+
+U_BOOT_DRIVER(tps65941_ldo) = {
+ .name = TPS65941_LDO_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65941_ldo_ops,
+ .probe = tps65941_ldo_probe,
+};
+
+static const struct dm_regulator_ops tps65941_buck_ops = {
+ .get_value = buck_get_value,
+ .set_value = buck_set_value,
+ .get_enable = buck_get_enable,
+ .set_enable = buck_set_enable,
+};
+
+U_BOOT_DRIVER(tps65941_buck) = {
+ .name = TPS65941_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &tps65941_buck_ops,
+ .probe = tps65941_buck_probe,
+};
View Lorry Controller Status