diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/i2c/Kconfig | 33 | ||||
| -rw-r--r-- | drivers/i2c/Makefile | 1 | ||||
| -rw-r--r-- | drivers/i2c/zynq_i2c.c | 313 | ||||
| -rw-r--r-- | drivers/misc/Kconfig | 1 | ||||
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 8 | ||||
| -rw-r--r-- | drivers/mmc/mmc-uclass.c | 19 | ||||
| -rw-r--r-- | drivers/mmc/mmc.c | 26 | ||||
| -rw-r--r-- | drivers/mmc/renesas-sdhi.c | 3 | ||||
| -rw-r--r-- | drivers/mmc/tmio-common.c | 10 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/mxs_nand.c | 11 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/mxs_nand_spl.c | 1 | ||||
| -rw-r--r-- | drivers/net/fec_mxc.c | 2 | ||||
| -rw-r--r-- | drivers/net/phy/mv88e61xx.c | 8 | ||||
| -rw-r--r-- | drivers/serial/serial_mxc.c | 13 | ||||
| -rw-r--r-- | drivers/spi/zynqmp_gqspi.c | 1 | ||||
| -rw-r--r-- | drivers/usb/host/ehci-mx6.c | 7 |
16 files changed, 89 insertions, 368 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index d83afe4dc6..b6bc678091 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -456,39 +456,6 @@ config SYS_I2C_XILINX_XIIC help Support for Xilinx AXI I2C controller. -config SYS_I2C_ZYNQ - bool "Xilinx I2C driver" - depends on ARCH_ZYNQMP || ARCH_ZYNQ - depends on !DM_I2C - help - Support for Xilinx I2C controller. - -config SYS_I2C_ZYNQ_SLAVE - hex "Set slave addr" - depends on SYS_I2C_ZYNQ - default 0 - help - Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr. - -config SYS_I2C_ZYNQ_SPEED - int "Set I2C speed" - depends on SYS_I2C_ZYNQ - default 100000 - help - Set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting. - -config ZYNQ_I2C0 - bool "Xilinx I2C0 controller" - depends on SYS_I2C_ZYNQ - help - Enable Xilinx I2C0 controller. - -config ZYNQ_I2C1 - bool "Xilinx I2C1 controller" - depends on SYS_I2C_ZYNQ - help - Enable Xilinx I2C1 controller. - config SYS_I2C_IHS bool "gdsys IHS I2C driver" depends on DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index ec2d1964c3..dc40055efb 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o -obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o obj-$(CONFIG_I2C_MUX) += muxes/ diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c deleted file mode 100644 index da25067c21..0000000000 --- a/drivers/i2c/zynq_i2c.c +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Driver for the Zynq-7000 PS I2C controller - * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) - * - * Author: Joe Hershberger <joe.hershberger@ni.com> - * Copyright (c) 2012 Joe Hershberger. - * - * Copyright (c) 2012-2013 Xilinx, Michal Simek - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.txt for instructions. - */ - -#include <common.h> -#include <asm/io.h> -#include <i2c.h> -#include <linux/errno.h> -#include <asm/arch/hardware.h> - -/* i2c register set */ -struct zynq_i2c_registers { - u32 control; - u32 status; - u32 address; - u32 data; - u32 interrupt_status; - u32 transfer_size; - u32 slave_mon_pause; - u32 time_out; - u32 interrupt_mask; - u32 interrupt_enable; - u32 interrupt_disable; -}; - -/* Control register fields */ -#define ZYNQ_I2C_CONTROL_RW 0x00000001 -#define ZYNQ_I2C_CONTROL_MS 0x00000002 -#define ZYNQ_I2C_CONTROL_NEA 0x00000004 -#define ZYNQ_I2C_CONTROL_ACKEN 0x00000008 -#define ZYNQ_I2C_CONTROL_HOLD 0x00000010 -#define ZYNQ_I2C_CONTROL_SLVMON 0x00000020 -#define ZYNQ_I2C_CONTROL_CLR_FIFO 0x00000040 -#define ZYNQ_I2C_CONTROL_DIV_B_SHIFT 8 -#define ZYNQ_I2C_CONTROL_DIV_B_MASK 0x00003F00 -#define ZYNQ_I2C_CONTROL_DIV_A_SHIFT 14 -#define ZYNQ_I2C_CONTROL_DIV_A_MASK 0x0000C000 - -/* Status register values */ -#define ZYNQ_I2C_STATUS_RXDV 0x00000020 -#define ZYNQ_I2C_STATUS_TXDV 0x00000040 -#define ZYNQ_I2C_STATUS_RXOVF 0x00000080 -#define ZYNQ_I2C_STATUS_BA 0x00000100 - -/* Interrupt register fields */ -#define ZYNQ_I2C_INTERRUPT_COMP 0x00000001 -#define ZYNQ_I2C_INTERRUPT_DATA 0x00000002 -#define ZYNQ_I2C_INTERRUPT_NACK 0x00000004 -#define ZYNQ_I2C_INTERRUPT_TO 0x00000008 -#define ZYNQ_I2C_INTERRUPT_SLVRDY 0x00000010 -#define ZYNQ_I2C_INTERRUPT_RXOVF 0x00000020 -#define ZYNQ_I2C_INTERRUPT_TXOVF 0x00000040 -#define ZYNQ_I2C_INTERRUPT_RXUNF 0x00000080 -#define ZYNQ_I2C_INTERRUPT_ARBLOST 0x00000200 - -#define ZYNQ_I2C_FIFO_DEPTH 16 -#define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */ - -static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap) -{ - return adap->hwadapnr ? - /* Zynq PS I2C1 */ - (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 : - /* Zynq PS I2C0 */ - (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0; -} - -/* I2C init called by cmd_i2c when doing 'i2c reset'. */ -static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, - int slaveadd) -{ - struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); - - /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ - writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) | - (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control); - - /* Enable master mode, ack, and 7-bit addressing */ - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_MS | - ZYNQ_I2C_CONTROL_ACKEN | ZYNQ_I2C_CONTROL_NEA); -} - -#ifdef DEBUG -static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c) -{ - int int_status; - int status; - int_status = readl(&zynq_i2c->interrupt_status); - - status = readl(&zynq_i2c->status); - if (int_status || status) { - debug("Status: "); - if (int_status & ZYNQ_I2C_INTERRUPT_COMP) - debug("COMP "); - if (int_status & ZYNQ_I2C_INTERRUPT_DATA) - debug("DATA "); - if (int_status & ZYNQ_I2C_INTERRUPT_NACK) - debug("NACK "); - if (int_status & ZYNQ_I2C_INTERRUPT_TO) - debug("TO "); - if (int_status & ZYNQ_I2C_INTERRUPT_SLVRDY) - debug("SLVRDY "); - if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) - debug("RXOVF "); - if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) - debug("TXOVF "); - if (int_status & ZYNQ_I2C_INTERRUPT_RXUNF) - debug("RXUNF "); - if (int_status & ZYNQ_I2C_INTERRUPT_ARBLOST) - debug("ARBLOST "); - if (status & ZYNQ_I2C_STATUS_RXDV) - debug("RXDV "); - if (status & ZYNQ_I2C_STATUS_TXDV) - debug("TXDV "); - if (status & ZYNQ_I2C_STATUS_RXOVF) - debug("RXOVF "); - if (status & ZYNQ_I2C_STATUS_BA) - debug("BA "); - debug("TS%d ", readl(&zynq_i2c->transfer_size)); - debug("\n"); - } -} -#endif - -/* Wait for an interrupt */ -static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) -{ - int timeout, int_status; - - for (timeout = 0; timeout < 100; timeout++) { - udelay(100); - int_status = readl(&zynq_i2c->interrupt_status); - if (int_status & mask) - break; - } -#ifdef DEBUG - zynq_i2c_debug_status(zynq_i2c); -#endif - /* Clear interrupt status flags */ - writel(int_status & mask, &zynq_i2c->interrupt_status); - - return int_status & mask; -} - -/* - * I2C probe called by cmd_i2c when doing 'i2c probe'. - * Begin read, nak data byte, end. - */ -static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) -{ - struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); - - /* Attempt to read a byte */ - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | - ZYNQ_I2C_CONTROL_RW); - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - writel(0xFF, &zynq_i2c->interrupt_status); - writel(dev, &zynq_i2c->address); - writel(1, &zynq_i2c->transfer_size); - - return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | - ZYNQ_I2C_INTERRUPT_NACK) & - ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; -} - -/* - * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c - * Begin write, send address byte(s), begin read, receive data bytes, end. - */ -static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, - int alen, u8 *data, int length) -{ - u32 status; - u32 i = 0; - u8 *cur_data = data; - struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); - - /* Check the hardware can handle the requested bytes */ - if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX)) - return -EINVAL; - - /* Write the register address */ - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | - ZYNQ_I2C_CONTROL_HOLD); - /* - * Temporarily disable restart (by clearing hold) - * It doesn't seem to work. - */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - writel(0xFF, &zynq_i2c->interrupt_status); - if (alen) { - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); - writel(dev, &zynq_i2c->address); - while (alen--) - writel(addr >> (8 * alen), &zynq_i2c->data); - - /* Wait for the address to be sent */ - if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; - } - debug("Device acked address\n"); - } - - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | - ZYNQ_I2C_CONTROL_RW); - /* Start reading data */ - writel(dev, &zynq_i2c->address); - writel(length, &zynq_i2c->transfer_size); - - /* Wait for data */ - do { - status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | - ZYNQ_I2C_INTERRUPT_DATA); - if (!status) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; - } - debug("Read %d bytes\n", - length - readl(&zynq_i2c->transfer_size)); - for (; i < length - readl(&zynq_i2c->transfer_size); i++) - *(cur_data++) = readl(&zynq_i2c->data); - } while (readl(&zynq_i2c->transfer_size) != 0); - /* All done... release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - -#ifdef DEBUG - zynq_i2c_debug_status(zynq_i2c); -#endif - return 0; -} - -/* - * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c - * Begin write, send address byte(s), send data bytes, end. - */ -static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, - int alen, u8 *data, int length) -{ - u8 *cur_data = data; - struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); - - /* Write the register address */ - setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | - ZYNQ_I2C_CONTROL_HOLD); - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); - writel(0xFF, &zynq_i2c->interrupt_status); - writel(dev, &zynq_i2c->address); - if (alen) { - while (alen--) - writel(addr >> (8 * alen), &zynq_i2c->data); - /* Start the tranfer */ - if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; - } - debug("Device acked address\n"); - } - - while (length--) { - writel(*(cur_data++), &zynq_i2c->data); - if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) { - if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, - ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; - } - } - } - - /* All done... release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - /* Wait for the address and data to be sent */ - if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) - return -ETIMEDOUT; - return 0; -} - -static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) -{ - if (speed != 1000000) - return -EINVAL; - - return 0; -} - -#ifdef CONFIG_ZYNQ_I2C0 -U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, - zynq_i2c_write, zynq_i2c_set_bus_speed, - CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, - 0) -#endif -#ifdef CONFIG_ZYNQ_I2C1 -U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, - zynq_i2c_write, zynq_i2c_set_bus_speed, - CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, - 1) -#endif diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 704c8dd195..d6e677fba8 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -245,6 +245,7 @@ config SPL_I2C_EEPROM config ZYNQ_GEM_I2C_MAC_OFFSET hex "Set the I2C MAC offset" default 0x0 + depends on DM_I2C help Set the MAC offset for i2C. diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 21fa2ab1d4..9e34557d16 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -804,7 +804,7 @@ static int esdhc_set_voltage(struct mmc *mmc) case MMC_SIGNAL_VOLTAGE_330: if (priv->vs18_enable) return -EIO; -#ifdef CONFIG_DM_REGULATOR +#if CONFIG_IS_ENABLED(DM_REGULATOR) if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { ret = regulator_set_value(priv->vqmmc_dev, 3300000); if (ret) { @@ -823,7 +823,7 @@ static int esdhc_set_voltage(struct mmc *mmc) return -EAGAIN; case MMC_SIGNAL_VOLTAGE_180: -#ifdef CONFIG_DM_REGULATOR +#if CONFIG_IS_ENABLED(DM_REGULATOR) if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { ret = regulator_set_value(priv->vqmmc_dev, 1800000); if (ret) { @@ -1442,7 +1442,7 @@ static int fsl_esdhc_probe(struct udevice *dev) int node = dev_of_offset(dev); struct esdhc_soc_data *data = (struct esdhc_soc_data *)dev_get_driver_data(dev); -#ifdef CONFIG_DM_REGULATOR +#if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *vqmmc_dev; #endif fdt_addr_t addr; @@ -1500,7 +1500,7 @@ static int fsl_esdhc_probe(struct udevice *dev) priv->vs18_enable = 0; -#ifdef CONFIG_DM_REGULATOR +#if CONFIG_IS_ENABLED(DM_REGULATOR) /* * If emmc I/O has a fixed voltage at 1.8V, this must be provided, * otherwise, emmc will work abnormally. diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 76225b7939..a9c8f335c1 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -368,6 +368,19 @@ static int mmc_blk_probe(struct udevice *dev) return 0; } +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) +static int mmc_blk_remove(struct udevice *dev) +{ + struct udevice *mmc_dev = dev_get_parent(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc_dev); + struct mmc *mmc = upriv->mmc; + + return mmc_deinit(mmc); +} +#endif + static const struct blk_ops mmc_blk_ops = { .read = mmc_bread, #if CONFIG_IS_ENABLED(MMC_WRITE) @@ -382,6 +395,12 @@ U_BOOT_DRIVER(mmc_blk) = { .id = UCLASS_BLK, .ops = &mmc_blk_ops, .probe = mmc_blk_probe, +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + .remove = mmc_blk_remove, + .flags = DM_FLAG_OS_PREPARE, +#endif }; #endif /* CONFIG_BLK */ diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index b04345a1e1..1c1527cc74 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2781,6 +2781,32 @@ int mmc_init(struct mmc *mmc) return err; } +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) +int mmc_deinit(struct mmc *mmc) +{ + u32 caps_filtered; + + if (!mmc->has_init) + return 0; + + if (IS_SD(mmc)) { + caps_filtered = mmc->card_caps & + ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | + MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) | + MMC_CAP(UHS_SDR104)); + + return sd_select_mode_and_width(mmc, caps_filtered); + } else { + caps_filtered = mmc->card_caps & + ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400)); + + return mmc_select_mode_and_width(mmc, caps_filtered); + } +} +#endif + int mmc_set_dsr(struct mmc *mmc, u16 val) { mmc->dsr = val; diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index a556acd5cb..923f846370 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -148,6 +148,9 @@ static int renesas_sdhi_hs400(struct udevice *dev) tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); } + tmio_sd_writel(priv, hs400 ? 0x704 : 0x300, + RENESAS_SDHI_SCC_DT2FF); + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL; tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 2421915a07..6e656e5a9b 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -705,10 +705,14 @@ static void tmio_sd_host_init(struct tmio_sd_priv *priv) * This register dropped backward compatibility at version 0x10. * Write an appropriate value depending on the IP version. */ - if (priv->version >= 0x10) - tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE); - else + if (priv->version >= 0x10) { + if (priv->caps & TMIO_SD_CAP_64BIT) + tmio_sd_writel(priv, 0x100, TMIO_SD_HOST_MODE); + else + tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE); + } else { tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE); + } if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) { tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE); diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index e3341812a2..be4ee2c7f8 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1092,7 +1092,7 @@ int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info) /* * Initializes the NFC hardware. */ -int mxs_nand_init_dma(struct mxs_nand_info *info) +static int mxs_nand_init_dma(struct mxs_nand_info *info) { int i = 0, j, ret = 0; @@ -1163,6 +1163,12 @@ int mxs_nand_init_spl(struct nand_chip *nand) nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE; nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; + + if (is_mx6sx() || is_mx7()) + nand_info->max_ecc_strength_supported = 62; + else + nand_info->max_ecc_strength_supported = 40; + err = mxs_nand_alloc_buffers(nand_info); if (err) return err; @@ -1185,9 +1191,6 @@ int mxs_nand_init_spl(struct nand_chip *nand) nand->ecc.read_page = mxs_nand_ecc_read_page; nand->ecc.mode = NAND_ECC_HW; - nand->ecc.bytes = 9; - nand->ecc.size = 512; - nand->ecc.strength = 8; return 0; } diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index c628f3adec..ba85baac60 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -201,6 +201,7 @@ static int mxs_nand_init(void) /* setup flash layout (does not scan as we override that) */ mtd->size = nand_chip.chipsize; nand_chip.scan_bbt(mtd); + mxs_nand_setup_ecc(mtd); return 0; } diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1a59026a62..a14fe43a5b 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1348,7 +1348,7 @@ static int fecmxc_probe(struct udevice *dev) #ifdef CONFIG_DM_REGULATOR if (priv->phy_supply) { - ret = regulator_autoset(priv->phy_supply); + ret = regulator_set_enable(priv->phy_supply, true); if (ret) { printf("%s: Error enabling phy supply\n", dev->name); return ret; diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index ea54a15310..c1e2860329 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -945,14 +945,14 @@ static int mv88e61xx_phy_config(struct phy_device *phydev) continue; } - res = genphy_config_aneg(phydev); + res = phy_reset(phydev); if (res < 0) { - printf("Error setting PHY %i autoneg\n", i); + printf("Error resetting PHY %i\n", i); continue; } - res = phy_reset(phydev); + res = genphy_config_aneg(phydev); if (res < 0) { - printf("Error resetting PHY %i\n", i); + printf("Error setting PHY %i autoneg\n", i); continue; } diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 7e4e6d36b8..df35ac9114 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -138,13 +138,18 @@ struct mxc_uart { u32 ts; }; -static void _mxc_serial_init(struct mxc_uart *base) +static void _mxc_serial_init(struct mxc_uart *base, int use_dte) { writel(0, &base->cr1); writel(0, &base->cr2); while (!(readl(&base->cr2) & UCR2_SRST)); + if (use_dte) + writel(0x404 | UCR3_ADNIMP, &base->cr3); + else + writel(0x704 | UCR3_ADNIMP, &base->cr3); + writel(0x704 | UCR3_ADNIMP, &base->cr3); writel(0x8000, &base->cr4); writel(0x2b, &base->esc); @@ -226,7 +231,7 @@ static int mxc_serial_tstc(void) */ static int mxc_serial_init(void) { - _mxc_serial_init(mxc_base); + _mxc_serial_init(mxc_base, false); serial_setbrg(); @@ -271,7 +276,7 @@ static int mxc_serial_probe(struct udevice *dev) { struct mxc_serial_platdata *plat = dev->platdata; - _mxc_serial_init(plat->reg); + _mxc_serial_init(plat->reg, plat->use_dte); return 0; } @@ -367,7 +372,7 @@ static inline void _debug_uart_init(void) { struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE; - _mxc_serial_init(base); + _mxc_serial_init(base, false); _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE, false); } diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 75459d156e..da9413c066 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -714,6 +714,7 @@ static const struct dm_spi_ops zynqmp_qspi_ops = { static const struct udevice_id zynqmp_qspi_ids[] = { { .compatible = "xlnx,zynqmp-qspi-1.0" }, + { .compatible = "xlnx,versal-qspi-1.0" }, { } }; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 1acf08dfb7..948394709f 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -404,6 +404,7 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) if (ret) return ret; +#if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { ret = regulator_set_enable(priv->vbus_supply, (type == USB_INIT_DEVICE) ? @@ -413,6 +414,7 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) return ret; } } +#endif if (type == USB_INIT_DEVICE) return 0; @@ -514,15 +516,17 @@ static int ehci_usb_probe(struct udevice *dev) priv->portnr = dev->seq; priv->init_type = type; +#if CONFIG_IS_ENABLED(DM_REGULATOR) ret = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_supply); if (ret) debug("%s: No vbus supply\n", dev->name); - +#endif ret = ehci_mx6_common_init(ehci, priv->portnr); if (ret) return ret; +#if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { ret = regulator_set_enable(priv->vbus_supply, (type == USB_INIT_DEVICE) ? @@ -532,6 +536,7 @@ static int ehci_usb_probe(struct udevice *dev) return ret; } } +#endif if (priv->init_type == USB_INIT_HOST) { setbits_le32(&ehci->usbmode, CM_HOST); |