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-rw-r--r--drivers/clk/Kconfig2
-rw-r--r--drivers/mtd/cfi_flash.c10
-rw-r--r--drivers/net/designware.c15
-rw-r--r--drivers/net/phy/phy.c4
-rw-r--r--drivers/pci/pci-aardvark.c42
-rw-r--r--drivers/phy/marvell/comphy_a3700.c70
-rw-r--r--drivers/phy/marvell/comphy_a3700.h1
-rw-r--r--drivers/phy/marvell/comphy_core.c81
-rw-r--r--drivers/phy/marvell/comphy_core.h67
-rw-r--r--drivers/phy/marvell/comphy_cp110.c621
-rw-r--r--drivers/phy/marvell/comphy_hpipe.h660
-rw-r--r--drivers/phy/marvell/comphy_mux.c11
-rw-r--r--drivers/phy/marvell/utmi_phy.h24
-rw-r--r--drivers/power/regulator/regulator-uclass.c38
-rw-r--r--drivers/spi/zynqmp_gqspi.c3
-rw-r--r--drivers/usb/host/ehci-mx6.c17
16 files changed, 366 insertions, 1300 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4aeaa0cd58..40a5a5dd88 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -125,7 +125,7 @@ config CLK_ZYNQ
depends on CLK && ARCH_ZYNQ
default y
help
- This clock driver adds support for clock realted settings for
+ This clock driver adds support for clock related settings for
Zynq platform.
config CLK_ZYNQMP
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 9642d7c7dc..9c27fea5d8 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2276,12 +2276,12 @@ ulong flash_get_size(phys_addr_t base, int banknum)
flash_unlock_seq(info, 0);
flash_write_cmd(info, 0,
info->addr_unlock1,
- FLASH_CMD_READ_ID);
+ AMD_CMD_SET_PPB_ENTRY);
info->protect[sect_cnt] =
- flash_isset(
- info, sect_cnt,
- FLASH_OFFSET_PROTECT,
- FLASH_STATUS_PROTECT);
+ !flash_isset(info, sect_cnt,
+ 0, 0x01);
+ flash_write_cmd(info, 0, 0,
+ info->cmd_reset);
break;
default:
/* default: not protected */
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index b8ba00b7c0..5d92257e74 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -91,9 +91,8 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
}
#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
-static int dw_mdio_reset(struct mii_dev *bus)
+static int __dw_mdio_reset(struct udevice *dev)
{
- struct udevice *dev = bus->priv;
struct dw_eth_dev *priv = dev_get_priv(dev);
struct dw_eth_pdata *pdata = dev_get_plat(dev);
int ret;
@@ -122,6 +121,13 @@ static int dw_mdio_reset(struct mii_dev *bus)
return 0;
}
+
+static int dw_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+
+ return __dw_mdio_reset(dev);
+}
#endif
#if IS_ENABLED(CONFIG_DM_MDIO)
@@ -142,9 +148,10 @@ int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int
#if CONFIG_IS_ENABLED(DM_GPIO)
int designware_eth_mdio_reset(struct udevice *mdio_dev)
{
- struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+ struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
+ struct udevice *dev = mdio_pdata->mii_bus->priv;
- return dw_mdio_reset(pdata->mii_bus);
+ return __dw_mdio_reset(dev->parent);
}
#endif
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index dcdef9e661..ed197fa46d 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -948,9 +948,9 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
phy_interface_t interface)
{
struct phy_device *phydev = NULL;
- ofnode node = dev_ofnode(dev);
+ ofnode node;
- while (ofnode_valid(node)) {
+ ofnode_for_each_subnode(node, dev_ofnode(dev)) {
node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
if (ofnode_valid(node)) {
phydev = phy_device_create(bus, 0,
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 3b9309f52c..c43d4f309b 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -132,8 +132,9 @@
PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
/* PCIe Retries & Timeout definitions */
-#define MAX_RETRIES 10
-#define PIO_WAIT_TIMEOUT 100
+#define PIO_MAX_RETRIES 1500
+#define PIO_WAIT_TIMEOUT 1000
+#define LINK_MAX_RETRIES 10
#define LINK_WAIT_TIMEOUT 100000
#define CFG_RD_UR_VAL 0xFFFFFFFF
@@ -192,7 +193,7 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
*
* @pcie: The PCI device to access
*
- * Wait up to 1 micro second for PIO access to be accomplished.
+ * Wait up to 1.5 seconds for PIO access to be accomplished.
*
* Return 1 (true) if PIO access is accomplished.
* Return 0 (false) if PIO access is timed out.
@@ -202,7 +203,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
uint start, isr;
uint count;
- for (count = 0; count < MAX_RETRIES; count++) {
+ for (count = 0; count < PIO_MAX_RETRIES; count++) {
start = advk_readl(pcie, PIO_START);
isr = advk_readl(pcie, PIO_ISR);
if (!start && isr)
@@ -214,7 +215,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
udelay(PIO_WAIT_TIMEOUT);
}
- dev_err(pcie->dev, "config read/write timed out\n");
+ dev_err(pcie->dev, "PIO read/write transfer time out\n");
return 0;
}
@@ -323,9 +324,14 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
@@ -342,10 +348,15 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
advk_writel(pcie, 0, PIO_ADDR_MS);
/* Start the transfer */
+ advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
- if (!pcie_advk_wait_pio(pcie))
- return -EINVAL;
+ if (!pcie_advk_wait_pio(pcie)) {
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Check PIO status and get the read result */
ret = pcie_advk_check_pio_status(pcie, true, &reg);
@@ -420,9 +431,11 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+ return -EINVAL;
+ }
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
@@ -450,6 +463,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
/* Start the transfer */
+ advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
if (!pcie_advk_wait_pio(pcie)) {
@@ -494,7 +508,7 @@ static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
int retries;
/* check if the link is up or not */
- for (retries = 0; retries < MAX_RETRIES; retries++) {
+ for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
if (pcie_advk_link_up(pcie)) {
printf("PCIE-%d: Link up\n", pcie->first_busno);
return 0;
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 12523d18a8..06822d1d12 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -17,33 +17,33 @@
DECLARE_GLOBAL_DATA_PTR;
struct comphy_mux_data a3700_comphy_mux_data[] = {
-/* Lane 0 */
+ /* Lane 0 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0 },
- { PHY_TYPE_SGMII1, 0x0 },
- { PHY_TYPE_USB3_HOST0, 0x1 },
- { PHY_TYPE_USB3_DEVICE, 0x1 }
+ { COMPHY_TYPE_UNCONNECTED, 0x0 },
+ { COMPHY_TYPE_SGMII1, 0x0 },
+ { COMPHY_TYPE_USB3_HOST0, 0x1 },
+ { COMPHY_TYPE_USB3_DEVICE, 0x1 }
}
},
-/* Lane 1 */
+ /* Lane 1 */
{
3,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SGMII0, 0x0},
- { PHY_TYPE_PEX0, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SGMII0, 0x0},
+ { COMPHY_TYPE_PEX0, 0x1}
}
},
-/* Lane 2 */
+ /* Lane 2 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SATA0, 0x0},
- { PHY_TYPE_USB3_HOST0, 0x1},
- { PHY_TYPE_USB3_DEVICE, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SATA0, 0x0},
+ { COMPHY_TYPE_USB3_HOST0, 0x1},
+ { COMPHY_TYPE_USB3_DEVICE, 0x1}
}
},
};
@@ -228,10 +228,10 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
/*
* 10. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -284,10 +284,10 @@ static int comphy_sata_power_up(u32 invert)
/*
* 0. Check the Polarity invert bits
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
data |= bs_txd_inv;
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
data |= bs_rxd_inv;
reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv);
@@ -465,10 +465,10 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
/*
* 9. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
/*
@@ -513,7 +513,7 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
* Set Soft ID for Host mode (Device mode works with Hard ID
* detection)
*/
- if (type == PHY_TYPE_USB3_HOST0) {
+ if (type == COMPHY_TYPE_USB3_HOST0) {
/*
* set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
* clear BIT1: set SOFT_ID = Host
@@ -685,8 +685,8 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed)
* comparison to 3.125 Gbps values. These register values are
* stored in "sgmii_phy_init_fix" array.
*/
- if ((speed != PHY_SPEED_1_25G) &&
- (sgmii_phy_init_fix[fix_idx].addr == addr)) {
+ if (speed != COMPHY_SPEED_1_25G &&
+ sgmii_phy_init_fix[fix_idx].addr == addr) {
/* Use new value */
val = sgmii_phy_init_fix[fix_idx].value;
if (fix_idx < fix_arr_sz)
@@ -737,13 +737,13 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
* 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
* COMPHY bit rate
*/
- if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */
+ if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x8 << rf_gen_rx_sel_shift) |
(0x8 << rf_gen_tx_sel_shift),
rf_gen_rx_select | rf_gen_tx_select);
- } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */
+ } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x6 << rf_gen_rx_sel_shift) |
(0x6 << rf_gen_tx_sel_shift),
@@ -819,7 +819,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
* registers are OK.
*/
debug("Running C-DPI phy init %s mode\n",
- speed == PHY_SPEED_3_125G ? "2G5" : "1G");
+ speed == COMPHY_SPEED_3_125G ? "2G5" : "1G");
if (get_ref_clk() == 40)
comphy_sgmii_phy_init(lane, speed);
@@ -837,10 +837,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
/*
* 18. Check the PHY Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -976,30 +976,30 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
comphy_map->type, comphy_map->invert);
switch (comphy_map->type) {
- case PHY_TYPE_UNCONNECTED:
+ case COMPHY_TYPE_UNCONNECTED:
continue;
break;
- case PHY_TYPE_PEX0:
+ case COMPHY_TYPE_PEX0:
ret = comphy_pcie_power_up(comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_USB3_HOST0:
- case PHY_TYPE_USB3_DEVICE:
+ case COMPHY_TYPE_USB3_HOST0:
+ case COMPHY_TYPE_USB3_DEVICE:
ret = comphy_usb3_power_up(lane,
comphy_map->type,
comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SGMII0:
- case PHY_TYPE_SGMII1:
+ case COMPHY_TYPE_SGMII0:
+ case COMPHY_TYPE_SGMII1:
ret = comphy_sgmii_power_up(lane, comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SATA0:
+ case COMPHY_TYPE_SATA0:
ret = comphy_sata_power_up(comphy_map->invert);
break;
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
index b0941ffb37..8748c6c84a 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -7,7 +7,6 @@
#define _COMPHY_A3700_H_
#include "comphy_core.h"
-#include "comphy_hpipe.h"
#define MVEBU_REG(offs) \
((void __iomem *)(ulong)MVEBU_REGISTER(offs))
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index cd54e7f889..2c9d7b2288 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -24,12 +24,12 @@ DECLARE_GLOBAL_DATA_PTR;
static const char *get_speed_string(u32 speed)
{
static const char * const speed_strings[] = {
- "1.25 Gbps", "1.5 Gbps", "2.5 Gbps",
- "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps",
- "6.25 Gbps", "10.31 Gbps"
+ "1.25 Gbps", "2.5 Gbps", "3.125 Gbps",
+ "5 Gbps", "5.125 Gpbs", "6 Gbps",
+ "10.3125 Gbps"
};
- if (speed < 0 || speed > PHY_SPEED_MAX)
+ if (speed < 0 || speed > COMPHY_SPEED_MAX)
return "invalid";
return speed_strings[speed];
@@ -39,14 +39,13 @@ static const char *get_type_string(u32 type)
{
static const char * const type_strings[] = {
"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
- "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0",
- "SGMII1", "SGMII2", "SGMII3", "QSGMII",
- "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
- "XAUI0", "XAUI1", "XAUI2", "XAUI3",
- "RXAUI0", "RXAUI1", "SFI", "IGNORE"
+ "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
+ "USB3", "USB3_HOST0", "USB3_HOST1",
+ "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP",
+ "IGNORE"
};
- if (type < 0 || type > PHY_TYPE_MAX)
+ if (type < 0 || type > COMPHY_TYPE_MAX)
return "invalid";
return type_strings[type];
@@ -59,7 +58,7 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg,
for (lane = 0; lane < chip_cfg->comphy_lanes_count;
lane++, comphy_map_data++) {
- if (comphy_map_data->speed == PHY_SPEED_INVALID) {
+ if (comphy_map_data->speed == COMPHY_SPEED_INVALID) {
printf("Comphy-%d: %-13s\n", lane,
get_type_string(comphy_map_data->type));
} else {
@@ -70,6 +69,16 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg,
}
}
+int comphy_rx_training(struct udevice *dev, u32 lane)
+{
+ struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
+
+ if (chip_cfg->rx_training)
+ return chip_cfg->rx_training(chip_cfg, lane);
+
+ return 0;
+}
+
__weak int comphy_update_map(struct comphy_map *serdes_map, int count)
{
return 0;
@@ -80,7 +89,6 @@ static int comphy_probe(struct udevice *dev)
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
- struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
int subnode;
int lane;
int last_idx = 0;
@@ -114,11 +122,15 @@ static int comphy_probe(struct udevice *dev)
fdtdec_locate_array(blob, node, "mux-lane-order",
chip_cfg->comphy_lanes_count);
- if (device_is_compatible(dev, "marvell,comphy-armada-3700"))
+ if (device_is_compatible(dev, "marvell,comphy-armada-3700")) {
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
+ chip_cfg->rx_training = NULL;
+ }
- if (device_is_compatible(dev, "marvell,comphy-cp110"))
+ if (device_is_compatible(dev, "marvell,comphy-cp110")) {
chip_cfg->ptr_comphy_chip_init = comphy_cp110_init;
+ chip_cfg->rx_training = comphy_cp110_sfi_rx_training;
+ }
/*
* Bail out if no chip_init function is defined, e.g. no
@@ -135,36 +147,45 @@ static int comphy_probe(struct udevice *dev)
if (!fdtdec_get_is_enabled(blob, subnode))
continue;
- comphy_map_data[lane].speed = fdtdec_get_int(
- blob, subnode, "phy-speed", PHY_TYPE_INVALID);
- comphy_map_data[lane].type = fdtdec_get_int(
- blob, subnode, "phy-type", PHY_SPEED_INVALID);
- comphy_map_data[lane].invert = fdtdec_get_int(
- blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT);
- comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode,
- "clk-src");
- comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode,
- "end_point");
- if (comphy_map_data[lane].type == PHY_TYPE_INVALID) {
+ chip_cfg->comphy_map_data[lane].type =
+ fdtdec_get_int(blob, subnode, "phy-type",
+ COMPHY_TYPE_INVALID);
+
+ if (chip_cfg->comphy_map_data[lane].type ==
+ COMPHY_TYPE_INVALID) {
printf("no phy type for lane %d, setting lane as unconnected\n",
lane + 1);
+ continue;
}
+ chip_cfg->comphy_map_data[lane].speed =
+ fdtdec_get_int(blob, subnode, "phy-speed",
+ COMPHY_SPEED_INVALID);
+
+ chip_cfg->comphy_map_data[lane].invert =
+ fdtdec_get_int(blob, subnode, "phy-invert",
+ COMPHY_POLARITY_NO_INVERT);
+
+ chip_cfg->comphy_map_data[lane].clk_src =
+ fdtdec_get_bool(blob, subnode, "clk-src");
+
+ chip_cfg->comphy_map_data[lane].end_point =
+ fdtdec_get_bool(blob, subnode, "end_point");
+
lane++;
}
- res = comphy_update_map(comphy_map_data, chip_cfg->comphy_lanes_count);
+ res = comphy_update_map(chip_cfg->comphy_map_data, chip_cfg->comphy_lanes_count);
if (res < 0)
return res;
/* Save CP index for MultiCP devices (A8K) */
chip_cfg->cp_index = current_idx++;
/* PHY power UP sequence */
- chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data);
+ chip_cfg->ptr_comphy_chip_init(chip_cfg, chip_cfg->comphy_map_data);
/* PHY print SerDes status */
- if (of_machine_is_compatible("marvell,armada8040"))
- printf("Comphy chip #%d:\n", chip_cfg->cp_index);
- comphy_print(chip_cfg, comphy_map_data);
+ printf("Comphy chip #%d:\n", chip_cfg->cp_index);
+ comphy_print(chip_cfg, chip_cfg->comphy_map_data);
/*
* Only run the dedicated PHY init code once, in the last PHY init call
diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h
index 12ab921d24..ba64491dfe 100644
--- a/drivers/phy/marvell/comphy_core.h
+++ b/drivers/phy/marvell/comphy_core.h
@@ -17,58 +17,8 @@
#define debug_exit()
#endif
-/* COMPHY registers */
-#define COMMON_PHY_CFG1_REG 0x0
-#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
-#define COMMON_PHY_CFG1_PWR_UP_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
-#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
-#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
- (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
-#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
-#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
-#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
-#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
- (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
-#define COMMON_PHY_PHY_MODE_OFFSET 15
-#define COMMON_PHY_PHY_MODE_MASK \
- (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
-
-#define COMMON_PHY_CFG6_REG 0x14
-#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
-#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
- (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
-
-#define COMMON_SELECTOR_PHY_OFFSET 0x140
-#define COMMON_SELECTOR_PIPE_OFFSET 0x144
-
-#define COMMON_PHY_SD_CTRL1 0x148
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
-#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
-#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
-
-/* ToDo: Get this address via DT */
-#define MVEBU_CP0_REGS_BASE 0xF2000000UL
-
-#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
-#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
-#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
- (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
-
#define MAX_LANE_OPTIONS 10
-#define MAX_UTMI_PHY_COUNT 3
+#define MAX_UTMI_PHY_COUNT 6
struct comphy_mux_options {
u32 type;
@@ -84,12 +34,14 @@ struct chip_serdes_phy_config {
struct comphy_mux_data *mux_data;
int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
struct comphy_map *);
+ int (*rx_training)(struct chip_serdes_phy_config *, u32);
void __iomem *comphy_base_addr;
void __iomem *hpipe3_base_addr;
u32 comphy_lanes_count;
u32 comphy_mux_bitcount;
const fdt32_t *comphy_mux_lane_order;
u32 cp_index;
+ struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
};
/* Register helper functions */
@@ -150,6 +102,8 @@ static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
#ifdef CONFIG_ARMADA_8K
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map);
+int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane);
#else
static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
@@ -160,6 +114,17 @@ static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
*/
return -1;
}
+
+static inline int comphy_cp110_sfi_rx_training(
+ struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
#endif
void comphy_dedicated_phys_init(void);
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index a323de7c76..418318d12f 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -14,20 +14,16 @@
#include <linux/delay.h>
#include "comphy_core.h"
-#include "comphy_hpipe.h"
#include "sata.h"
#include "utmi_phy.h"
DECLARE_GLOBAL_DATA_PTR;
-#define SD_ADDR(base, lane) (base + 0x1000 * lane)
-#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
-#define COMPHY_ADDR(base, lane) (base + 0x28 * lane)
-
/* Firmware related definitions used for SMC calls */
#define MV_SIP_COMPHY_POWER_ON 0x82000001
#define MV_SIP_COMPHY_POWER_OFF 0x82000002
#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
+#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
/* Used to distinguish between different possible callers (U-boot/Linux) */
#define COMPHY_CALLER_UBOOT (0x1 << 21)
@@ -59,52 +55,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define COMPHY_UNIT_ID3 3
struct utmi_phy_data {
+ void __iomem *utmi_pll_addr;
void __iomem *utmi_base_addr;
void __iomem *usb_cfg_addr;
void __iomem *utmi_cfg_addr;
u32 utmi_phy_port;
};
-/*
- * For CP-110 we have 2 Selector registers "PHY Selectors",
- * and "PIPE Selectors".
- * PIPE selector include USB and PCIe options.
- * PHY selector include the Ethernet and SATA options, every Ethernet
- * option has different options, for example: serdes lane2 had option
- * Eth_port_0 that include (SGMII0, RXAUI0, SFI)
- */
-struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
- {PHY_TYPE_SATA1, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
- {PHY_TYPE_SATA0, 0x4} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
- {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
- {PHY_TYPE_SATA0, 0x4} } },
- {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
- {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
- {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
- {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
- {PHY_TYPE_SGMII1, 0x1} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
- {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
-};
-
-struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
- {PHY_TYPE_PEX0, 0x4} } },
- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
- {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
- {PHY_TYPE_USB3_HOST1, 0x1},
- {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
-};
-
static u32 polling_with_timeout(void __iomem *addr, u32 val,
u32 mask, unsigned long usec_timout)
{
@@ -121,128 +78,6 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val,
return 0;
}
-static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base)
-{
- u32 mask, data, ret = 1;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
- void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
- void __iomem *addr;
-
- debug_enter();
- debug("stage: RFU configurations - hard reset comphy\n");
- /* RFU configurations - hard reset comphy */
- mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- mask |= COMMON_PHY_PHY_MODE_MASK;
- data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* release from hard reset */
- mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- mdelay(1);
-
- /* Start comphy Configuration */
- debug("stage: Comphy configuration\n");
- /* Set PIPE soft reset */
- mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
- data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
- /* Set PHY datapath width mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
- /* Set Data bus width USB mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
- /* Set CORE_CLK output frequency for 250Mhz */
- mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
- /* Set PLL ready delay for 0x2 */
- reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
- 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
- HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
- /* Set reference clock to come from group 1 - 25Mhz */
- reg_set(hpipe_addr + HPIPE_MISC_REG,
- 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
- HPIPE_MISC_REFCLK_SEL_MASK);
- /* Set reference frequcency select - 0x2 */
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- /* Set PHY mode to USB - 0x5 */
- mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
- /* Set the amount of time spent in the LoZ state - set for 0x7 */
- reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
- 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
- HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
- /* Set max PHY generation setting - 5Gbps */
- reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
- 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
- HPIPE_INTERFACE_GEN_MAX_MASK);
- /* Set select data width 20Bit (SEL_BITS[2:0]) */
- reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
- HPIPE_LOOPBACK_SEL_MASK);
- /* select de-emphasize 3.5db */
- reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
- 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
- HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
- /* override tx margining from the MAC */
- reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
- 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
- HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
-
- /* Start analog paramters from ETP(HW) */
- debug("stage: Analog paramters from ETP(HW)\n");
- /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
- mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
- data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
- /* Set Override PHY DFE control pins for 0x1 */
- mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
- data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
- /* Set Spread Spectrum Clock Enable fot 0x1 */
- mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
- data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
- reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
- /* End of analog parameters */
-
- debug("stage: Comphy power up\n");
- /* Release from PIPE soft reset */
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
- 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
- HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
-
- /* wait 15ms - for comphy calibration done */
- debug("stage: Check PLL\n");
- /* Read lane status */
- addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
- data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 15000);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
- pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
- ret = 0;
- }
-
- debug_exit();
- return ret;
-}
-
static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
u32 lane, u32 mode)
{
@@ -263,6 +98,35 @@ static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
return pregs.regs[0] ? 0 : 1;
}
+/* This function performs RX training for all FFE possible values.
+ * We get the result for each FFE and eventually the best FFE will
+ * be used and set to the HW.
+ *
+ * Return '1' on succsess.
+ * Return '0' on failure.
+ */
+int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane)
+{
+ int ret;
+ u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
+
+ debug_enter();
+
+ if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
+ pr_err("Comphy %d isn't configured to SFI\n", lane);
+ return 0;
+ }
+
+ /* Mode is not relevant for xfi training */
+ ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN,
+ ptr_chip_cfg->comphy_base_addr, lane, 0);
+
+ debug_exit();
+
+ return ret;
+}
+
static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
void __iomem *comphy_base_addr, int cp_index,
u32 type)
@@ -357,184 +221,6 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
return ret;
}
-static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base)
-{
- u32 mask, data, ret = 1;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
- void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
- void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
- void __iomem *addr;
-
- debug_enter();
- debug("stage: RFU configurations - hard reset comphy\n");
- /* RFU configurations - hard reset comphy */
- mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- if (lane == 2) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
- COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
- }
- if (lane == 4) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
- COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
- }
-
- /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
- mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
- data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
- data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
-
- /* release from hard reset */
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- mdelay(1);
-
- /* Start comphy Configuration */
- debug("stage: Comphy configuration\n");
- /* set reference clock */
- reg_set(hpipe_addr + HPIPE_MISC_REG,
- 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
- HPIPE_MISC_REFCLK_SEL_MASK);
- /* Power and PLL Control */
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
- /* Loopback register */
- reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
- /* rx control 1 */
- mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
- data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
- mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
- data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
- /* DTL Control */
- reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
- 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
- HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
-
- /* Set analog paramters from ETP(HW) */
- debug("stage: Analog paramters from ETP(HW)\n");
- /* SERDES External Configuration 2 */
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
- 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
- SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
- /* 0x7-DFE Resolution control */
- reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
- HPIPE_DFE_RES_FORCE_MASK);
- /* 0xd-G1_Setting_0 */
- reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
- 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
- HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
- /* 0xE-G1_Setting_1 */
- mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
- data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
- /* 0xA-DFE_Reg3 */
- mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
- data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
- mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
- data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
- reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
-
- /* 0x111-G1_Setting_4 */
- mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
- data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
-
- debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
- /* SERDES External Configuration */
- mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
-
-
- /* check PLL rx & tx ready */
- addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
- data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
- SD_EXTERNAL_STATUS0_PLL_TX_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 15000);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
- pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
- (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
- (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
- ret = 0;
- }
-
- /* RX init */
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
- 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
- SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
-
- /* check that RX init done */
- addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
- data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 100);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
- pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
- ret = 0;
- }
-
- debug("stage: RF Reset\n");
- /* RF Reset */
- mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- debug_exit();
- return ret;
-}
-
static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr,
@@ -580,7 +266,8 @@ static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
return;
}
-static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
+static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr,
+ void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr,
u32 utmi_phy_port)
@@ -598,27 +285,37 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
/* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
- reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask);
+ reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
/* Impedance Calibration Threshold Setting */
- reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
- 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
- UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
+ mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK;
+ data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET;
+ reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
+
+ /* Start Impedance and PLL Calibration */
+ mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK;
+ data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET);
+ mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK;
+ data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET);
+ reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
/* Set LS TX driver strength coarse control */
- mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
- data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
- /* Set LS TX driver fine adjustment */
+ mask = UTMI_TX_CH_CTRL_AMP_MASK;
+ data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
+ mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
+ data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
/* Enable SQ */
mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
- data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
+ data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
/* Enable analog squelch detect */
mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
- data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+ data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+ mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK;
+ data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET;
reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
/* Set External squelch calibration number */
@@ -641,7 +338,8 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
return;
}
-static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
+static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr,
+ void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
{
@@ -660,7 +358,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
UTMI_CTRL_STATUS0_TEST_SEL_MASK);
debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
- addr = utmi_base_addr + UTMI_CALIB_CTRL_REG;
+ addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG;
data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
mask = data;
data = polling_with_timeout(addr, data, mask, 100);
@@ -679,7 +377,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
ret = 0;
}
- addr = utmi_base_addr + UTMI_PLL_CTRL_REG;
+ addr = utmi_pll_addr + UTMI_PLL_CTRL_REG;
data = UTMI_PLL_CTRL_PLL_RDY_MASK;
mask = data;
data = polling_with_timeout(addr, data, mask, 100);
@@ -703,7 +401,7 @@ static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
* the init split in 3 parts:
* 1. Power down transceiver and PLL
* 2. UTMI PHY configure
- * 3. Powe up transceiver and PLL
+ * 3. Power up transceiver and PLL
* Note: - Power down/up should be once for both UTMI PHYs
* - comphy_dedicated_phys_init call this function if at least there is
* one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
@@ -730,14 +428,16 @@ static void comphy_utmi_phy_init(u32 utmi_phy_count,
}
/* UTMI configure */
for (i = 0; i < utmi_phy_count; i++) {
- comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr,
+ comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr,
+ cp110_utmi_data[i].utmi_base_addr,
cp110_utmi_data[i].usb_cfg_addr,
cp110_utmi_data[i].utmi_cfg_addr,
cp110_utmi_data[i].utmi_phy_port);
}
/* UTMI Power up */
for (i = 0; i < utmi_phy_count; i++) {
- if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr,
+ if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr,
+ cp110_utmi_data[i].utmi_base_addr,
cp110_utmi_data[i].usb_cfg_addr,
cp110_utmi_data[i].utmi_cfg_addr,
cp110_utmi_data[i].utmi_phy_port)) {
@@ -770,45 +470,61 @@ static void comphy_utmi_phy_init(u32 utmi_phy_count,
void comphy_dedicated_phys_init(void)
{
struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
- int node;
- int i;
+ int node = -1;
+ int node_idx;
+ int parent = -1;
debug_enter();
debug("Initialize USB UTMI PHYs\n");
- /* Find the UTMI phy node in device tree and go over them */
- node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "marvell,mvebu-utmi-2.6.0");
+ for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) {
+ /* Find the UTMI phy node in device tree */
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, node,
+ "marvell,mvebu-utmi-2.6.0");
+ if (node <= 0)
+ break;
+
+ /* check if node is enabled */
+ if (!fdtdec_get_is_enabled(gd->fdt_blob, node))
+ continue;
+
+ parent = fdt_parent_offset(gd->fdt_blob, node);
+ if (parent <= 0)
+ break;
+
+ /* get base address of UTMI PLL */
+ cp110_utmi_data[node_idx].utmi_pll_addr =
+ (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, parent, "reg", 0, NULL, true);
+ if (!cp110_utmi_data[node_idx].utmi_pll_addr) {
+ pr_err("UTMI PHY PLL address is invalid\n");
+ continue;
+ }
- i = 0;
- while (node > 0) {
/* get base address of UTMI phy */
- cp110_utmi_data[i].utmi_base_addr =
+ cp110_utmi_data[node_idx].utmi_base_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 0, NULL, true);
- if (cp110_utmi_data[i].utmi_base_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].utmi_base_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
/* get usb config address */
- cp110_utmi_data[i].usb_cfg_addr =
+ cp110_utmi_data[node_idx].usb_cfg_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 1, NULL, true);
- if (cp110_utmi_data[i].usb_cfg_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].usb_cfg_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
/* get UTMI config address */
- cp110_utmi_data[i].utmi_cfg_addr =
+ cp110_utmi_data[node_idx].utmi_cfg_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 2, NULL, true);
- if (cp110_utmi_data[i].utmi_cfg_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].utmi_cfg_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
@@ -816,70 +532,30 @@ void comphy_dedicated_phys_init(void)
* get the port number (to check if the utmi connected to
* host/device)
*/
- cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int(
+ cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int(
gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
- if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) {
+ if (cp110_utmi_data[node_idx].utmi_phy_port ==
+ UTMI_PHY_INVALID) {
pr_err("UTMI PHY port type is invalid\n");
- i++;
continue;
}
- node = fdt_node_offset_by_compatible(
- gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0");
- i++;
+ /* count valid UTMI unit */
+ node_idx++;
}
- if (i > 0)
- comphy_utmi_phy_init(i, cp110_utmi_data);
+ if (node_idx > 0)
+ comphy_utmi_phy_init(node_idx, cp110_utmi_data);
debug_exit();
}
-static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *serdes_map)
-{
- void __iomem *comphy_base_addr;
- struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS];
- struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS];
- u32 lane, comphy_max_count;
-
- comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
- comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
-
- /*
- * Copy the SerDes map configuration for PIPE map and PHY map
- * the comphy_mux_init modify the type of the lane if the type
- * is not valid because we have 2 selectores run the
- * comphy_mux_init twice and after that update the original
- * serdes_map
- */
- for (lane = 0; lane < comphy_max_count; lane++) {
- comphy_map_pipe_data[lane].type = serdes_map[lane].type;
- comphy_map_pipe_data[lane].speed = serdes_map[lane].speed;
- comphy_map_phy_data[lane].type = serdes_map[lane].type;
- comphy_map_phy_data[lane].speed = serdes_map[lane].speed;
- }
- ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data;
- comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data,
- comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET);
-
- ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data;
- comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data,
- comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
- /* Fix the type after check the PHY and PIPE configuration */
- for (lane = 0; lane < comphy_max_count; lane++) {
- if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
- (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
- serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
- }
-}
-
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
{
struct comphy_map *ptr_comphy_map;
void __iomem *comphy_base_addr, *hpipe_base_addr;
- u32 comphy_max_count, lane, ret = 0;
+ u32 comphy_max_count, lane, id, ret = 0;
u32 pcie_width = 0;
u32 mode;
@@ -889,13 +565,10 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
- /* Config Comphy mux configuration */
- comphy_mux_cp110_init(ptr_chip_cfg, serdes_map);
-
/* Check if the first 4 lanes configured as By-4 */
for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
lane++, ptr_comphy_map++) {
- if (ptr_comphy_map->type != PHY_TYPE_PEX0)
+ if (ptr_comphy_map->type != COMPHY_TYPE_PEX0)
break;
pcie_width++;
}
@@ -912,14 +585,18 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
pcie_width = 1;
}
switch (ptr_comphy_map->type) {
- case PHY_TYPE_UNCONNECTED:
- case PHY_TYPE_IGNORE:
+ case COMPHY_TYPE_UNCONNECTED:
+ mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT;
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF,
+ ptr_chip_cfg->comphy_base_addr,
+ lane, mode);
+ case COMPHY_TYPE_IGNORE:
continue;
break;
- case PHY_TYPE_PEX0:
- case PHY_TYPE_PEX1:
- case PHY_TYPE_PEX2:
- case PHY_TYPE_PEX3:
+ case COMPHY_TYPE_PEX0:
+ case COMPHY_TYPE_PEX1:
+ case COMPHY_TYPE_PEX2:
+ case COMPHY_TYPE_PEX3:
mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
ptr_comphy_map->clk_src,
COMPHY_PCIE_MODE,
@@ -928,71 +605,61 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SATA0:
- case PHY_TYPE_SATA1:
- case PHY_TYPE_SATA2:
- case PHY_TYPE_SATA3:
+ case COMPHY_TYPE_SATA0:
+ case COMPHY_TYPE_SATA1:
mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE);
ret = comphy_sata_power_up(lane, hpipe_base_addr,
comphy_base_addr,
ptr_chip_cfg->cp_index,
mode);
break;
- case PHY_TYPE_USB3_HOST0:
- case PHY_TYPE_USB3_HOST1:
- case PHY_TYPE_USB3_DEVICE:
- ret = comphy_usb3_power_up(lane, hpipe_base_addr,
- comphy_base_addr);
+ case COMPHY_TYPE_USB3_HOST0:
+ case COMPHY_TYPE_USB3_HOST1:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane,
+ mode);
break;
- case PHY_TYPE_SGMII0:
- case PHY_TYPE_SGMII1:
- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
- debug("Warning: ");
- debug("SGMII PHY speed in lane %d is invalid,",
- lane);
- debug(" set PHY speed to 1.25G\n");
- ptr_comphy_map->speed = PHY_SPEED_1_25G;
- }
-
- /*
- * UINIT_ID not relevant for SGMII0 and SGMII1 - will be
- * ignored by firmware
- */
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID0,
- ptr_comphy_map->speed);
+ case COMPHY_TYPE_USB3_DEVICE:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SGMII2:
- case PHY_TYPE_SGMII3:
- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
+ case COMPHY_TYPE_SGMII0:
+ case COMPHY_TYPE_SGMII1:
+ case COMPHY_TYPE_SGMII2:
+ /* Calculate SGMII ID */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0;
+
+ if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
lane);
- ptr_comphy_map->speed = PHY_SPEED_1_25G;
+ ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
}
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID2,
+ mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SFI:
- mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
- COMPHY_UNIT_ID0,
+ case COMPHY_TYPE_SFI0:
+ case COMPHY_TYPE_SFI1:
+ /* Calculate SFI id */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
+ mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane, mode);
+ break;
+ case COMPHY_TYPE_RXAUI0:
+ case COMPHY_TYPE_RXAUI1:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_RXAUI_MODE);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_RXAUI0:
- case PHY_TYPE_RXAUI1:
- ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
- comphy_base_addr);
- break;
default:
debug("Unknown SerDes type, skip initialize SerDes %d\n",
lane);
@@ -1001,9 +668,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
if (ret == 0) {
/*
* If interface wans't initialized, set the lane to
- * PHY_TYPE_UNCONNECTED state.
+ * COMPHY_TYPE_UNCONNECTED state.
*/
- ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
+ ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED;
pr_err("PLL is not locked - Failed to initialize lane %d\n",
lane);
}
diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h
deleted file mode 100644
index a692035c94..0000000000
--- a/drivers/phy/marvell/comphy_hpipe.h
+++ /dev/null
@@ -1,660 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Marvell International Ltd.
- */
-
-#ifndef _COMPHY_HPIPE_H_
-#define _COMPHY_HPIPE_H_
-
-/* SerDes IP register */
-#define SD_EXTERNAL_CONFIG0_REG 0
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
- (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
- (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
- (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
-
-#define SD_EXTERNAL_CONFIG1_REG 0x4
-#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
-#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
-
-#define SD_EXTERNAL_CONFIG2_REG 0x8
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
-
-#define SD_EXTERNAL_STATUS0_REG 0x18
-#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
-#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
-#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
-#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
-#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
-
-/* HPIPE register */
-#define HPIPE_PWR_PLL_REG 0x4
-#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
-#define HPIPE_PWR_PLL_REF_FREQ_MASK \
- (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
-#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
-#define HPIPE_PWR_PLL_PHY_MODE_MASK \
- (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
-
-#define HPIPE_KVCO_CALIB_CTRL_REG 0x8
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
- (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
-
-#define HPIPE_CAL_REG1_REG 0xc
-#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
-#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
- (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
- (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
-
-#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
-
-#define HPIPE_DFE_REG0 0x01C
-#define HPIPE_DFE_RES_FORCE_OFFSET 15
-#define HPIPE_DFE_RES_FORCE_MASK \
- (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
-
-#define HPIPE_DFE_F3_F5_REG 0x028
-#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
-#define HPIPE_DFE_F3_F5_DFE_EN_MASK \
- (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
-#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
-#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
- (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
-
-#define HPIPE_G1_SET_0_REG 0x034
-#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
-#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
- (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
- (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
-
-#define HPIPE_G1_SET_1_REG 0x038
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
-#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
-#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
-
-#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
-
-#define HPIPE_G2_SET_0_REG 0x3c
-#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
-#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
- (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
- (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
-
-#define HPIPE_G2_SET_1_REG 0x040
-#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
-#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
-#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
-#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
-#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
-
-#define HPIPE_G3_SET_0_REG 0x44
-#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
-#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
- (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
- (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
-#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
- (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
-#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
-
-#define HPIPE_G3_SET_1_REG 0x048
-#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
-#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
-#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
- (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
-#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
-#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
-#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
-#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
-#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
- (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
-
-#define HPIPE_LOOPBACK_REG 0x08c
-#define HPIPE_LOOPBACK_SEL_OFFSET 1
-#define HPIPE_LOOPBACK_SEL_MASK \
- (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
-
-#define HPIPE_SYNC_PATTERN_REG 0x090
-#define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10
-#define HPIPE_SYNC_PATTERN_TXD_SWAP_MASK \
- (0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET)
-#define HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET 11
-#define HPIPE_SYNC_PATTERN_RXD_SWAP_MASK \
- (0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET)
-
-#define HPIPE_INTERFACE_REG 0x94
-#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
-#define HPIPE_INTERFACE_GEN_MAX_MASK \
- (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
-#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
-#define HPIPE_INTERFACE_DET_BYPASS_MASK \
- (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
-#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
-#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
- (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
-
-#define HPIPE_ISOLATE_MODE_REG 0x98
-#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
-#define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
- (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
-#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
-#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
- (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
-
-#define HPIPE_G1_SET_2_REG 0xf4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
- (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
- (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
-
-#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
-
-#define HPIPE_VDD_CAL_CTRL_REG 0x114
-#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
-#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
- (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
-
-#define HPIPE_VDD_CAL_0_REG 0x108
-#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
-#define HPIPE_CAL_VDD_CONT_MODE_MASK \
- (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
-
-#define HPIPE_PCIE_REG0 0x120
-#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
-#define HPIPE_PCIE_IDLE_SYNC_MASK \
- (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
-#define HPIPE_PCIE_SEL_BITS_OFFSET 13
-#define HPIPE_PCIE_SEL_BITS_MASK \
- (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
-
-#define HPIPE_LANE_ALIGN_REG 0x124
-#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
-#define HPIPE_LANE_ALIGN_OFF_MASK \
- (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
-
-#define HPIPE_MISC_REG 0x13C
-#define HPIPE_MISC_CLK100M_125M_OFFSET 4
-#define HPIPE_MISC_CLK100M_125M_MASK \
- (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
-#define HPIPE_MISC_ICP_FORCE_OFFSET 5
-#define HPIPE_MISC_ICP_FORCE_MASK \
- (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
-#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
-#define HPIPE_MISC_TXDCLK_2X_MASK \
- (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
-#define HPIPE_MISC_CLK500_EN_OFFSET 7
-#define HPIPE_MISC_CLK500_EN_MASK \
- (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
-#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
-#define HPIPE_MISC_REFCLK_SEL_MASK \
- (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
-
-#define HPIPE_RX_CONTROL_1_REG 0x140
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
- (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
- (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_REG 0x148
-#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
-#define HPIPE_PWR_CTR_RST_DFE_MASK \
- (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
-#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
-#define HPIPE_PWR_CTR_SFT_RST_MASK \
- (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
-
-#define HPIPE_SPD_DIV_FORCE_REG 0x154
-#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
-#define HPIPE_TXDIGCK_DIV_FORCE_MASK \
- (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
- (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
- (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
- (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
- (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
-
-#define HPIPE_PLLINTP_REG1 0x150
-
-#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
-#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
-#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
- (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
-#define HPIPE_SMAPLER_OFFSET 12
-#define HPIPE_SMAPLER_MASK \
- (0x1 << HPIPE_SMAPLER_OFFSET)
-
-#define HPIPE_TX_REG1_REG 0x174
-#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
-#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
- (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
-#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
-#define HPIPE_TX_REG1_SLC_EN_MASK \
- (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_DTL_REG 0x184
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
- (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
- (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
- (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
-
-#define HPIPE_PHASE_CONTROL_REG 0x188
-#define HPIPE_OS_PH_OFFSET_OFFSET 0
-#define HPIPE_OS_PH_OFFSET_MASK \
- (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
-#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
-#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
- (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
-#define HPIPE_OS_PH_VALID_OFFSET 8
-#define HPIPE_OS_PH_VALID_MASK \
- (0x1 << HPIPE_OS_PH_VALID_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
-#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
-#define HPIPE_TRAIN_PAT_NUM_MASK \
- (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \
- (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
-
-#define HPIPE_DME_REG 0x228
-#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
-#define HPIPE_DME_ETHERNET_MODE_MASK \
- (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
-#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
-#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
- (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
-#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
-#define HPIPE_TX_TRAIN_CTRL_G1_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
-#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
-#define HPIPE_TX_TRAIN_CTRL_G0_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
-#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_TRX_TRAIN_TIMER_MASK \
- (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
-
-#define HPIPE_PCIE_REG1 0x288
-#define HPIPE_PCIE_REG3 0x290
-
-#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
-#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_RX_TRAIN_TIMER_MASK \
- (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
-#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
-#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
-
-#define HPIPE_TX_TRAIN_REG 0x31C
-#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
-#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
- (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
- (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
-#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
-#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
- (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
-
-#define HPIPE_CDR_CONTROL_REG 0x418
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
- (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
- (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
- (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
-#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
-#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
- (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
-#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
-#define HPIPE_TX_NUM_OF_PRESET_MASK \
- (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
-#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
-#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
- (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
-
-#define HPIPE_G1_SETTINGS_3_REG 0x440
-#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
-#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
- (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
-#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
- (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
-#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
- (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
- (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
-#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
- (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
-#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
- (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
-
-#define HPIPE_G1_SETTINGS_4_REG 0x444
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
- (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
-
-#define HPIPE_G2_SETTINGS_3_REG 0x448
-
-#define HPIPE_G2_SETTINGS_4_REG 0x44c
-#define HPIPE_G2_DFE_RES_OFFSET 8
-#define HPIPE_G2_DFE_RES_MASK \
- (0x3 << HPIPE_G2_DFE_RES_OFFSET)
-
-#define HPIPE_G3_SETTING_3_REG 0x450
-#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
-#define HPIPE_G3_FFE_CAP_SEL_MASK \
- (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
-#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
-#define HPIPE_G3_FFE_RES_SEL_MASK \
- (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
-#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
-#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
- (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
-#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
-#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
- (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
-#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
-#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
- (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
-
-#define HPIPE_G3_SETTING_4_REG 0x454
-#define HPIPE_G3_DFE_RES_OFFSET 8
-#define HPIPE_G3_DFE_RES_MASK \
- (0x3 << HPIPE_G3_DFE_RES_OFFSET)
-
-#define HPIPE_TX_PRESET_INDEX_REG 0x468
-#define HPIPE_TX_PRESET_INDEX_OFFSET 0
-#define HPIPE_TX_PRESET_INDEX_MASK \
- (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
-
-#define HPIPE_DFE_CONTROL_REG 0x470
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
- (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
-
-#define HPIPE_DFE_CTRL_28_REG 0x49C
-#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
-#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
- (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
-
-#define HPIPE_G1_SETTING_5_REG 0x538
-#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
-#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
- (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
-
-#define HPIPE_G3_SETTING_5_REG 0x548
-#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
-#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
- (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
-
-#define HPIPE_LANE_CONFIG0_REG 0x600
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
- (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
-
-#define HPIPE_LANE_CONFIG1_REG 0x604
-#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
-#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
- (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
- (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
-
-#define HPIPE_LANE_STATUS1_REG 0x60C
-#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
-#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
- (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
-
-#define HPIPE_LANE_CFG4_REG 0x620
-#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
-#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
- (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
- (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
-#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
- (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
-#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
-#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
- (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
-
-#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
-#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
-#define HPIPE_CFG_PHY_RC_EP_MASK \
- (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
-
-#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
-#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
-#define HPIPE_CFG_UPDATE_POLARITY_MASK \
- (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
-
-#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
- (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
- (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
- (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
-
-#define HPIPE_RST_CLK_CTRL_REG 0x704
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
-
-#define HPIPE_TST_MODE_CTRL_REG 0x708
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
- (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
-
-#define HPIPE_CLK_SRC_LO_REG 0x70c
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
- (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
- (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
- (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
-
-#define HPIPE_CLK_SRC_HI_REG 0x710
-#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
-#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
-
-#define HPIPE_GLOBAL_MISC_CTRL 0x718
-#define HPIPE_GLOBAL_PM_CTRL 0x740
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
- (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
-
-#endif /* _COMPHY_HPIPE_H_ */
-
diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c
index 98327557a8..10981d25ec 100644
--- a/drivers/phy/marvell/comphy_mux.c
+++ b/drivers/phy/marvell/comphy_mux.c
@@ -8,14 +8,13 @@
#include <asm/io.h>
#include "comphy_core.h"
-#include "comphy_hpipe.h"
/*
* comphy_mux_check_config()
* description: this function passes over the COMPHY lanes and check if the type
* is valid for specific lane. If the type is not valid,
* the function update the struct and set the type of the lane as
- * PHY_TYPE_UNCONNECTED
+ * COMPHY_TYPE_UNCONNECTED
*/
static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
struct comphy_map *comphy_map_data, int comphy_max_lanes)
@@ -28,7 +27,7 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
/* Don't check ignored COMPHYs */
- if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ if (comphy_map_data->type == COMPHY_TYPE_IGNORE)
continue;
mux_opt = mux_data->mux_values;
@@ -43,8 +42,8 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
debug("lane number %d, had invalid type %d\n",
lane, comphy_map_data->type);
debug("set lane %d as type %d\n", lane,
- PHY_TYPE_UNCONNECTED);
- comphy_map_data->type = PHY_TYPE_UNCONNECTED;
+ COMPHY_TYPE_UNCONNECTED);
+ comphy_map_data->type = COMPHY_TYPE_UNCONNECTED;
} else {
debug("lane number %d, has type %d\n",
lane, comphy_map_data->type);
@@ -88,7 +87,7 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
- if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ if (comphy_map_data->type == COMPHY_TYPE_IGNORE)
continue;
/*
diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h
index 682a3acc40..8a570bae73 100644
--- a/drivers/phy/marvell/utmi_phy.h
+++ b/drivers/phy/marvell/utmi_phy.h
@@ -38,6 +38,12 @@
#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8
#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \
(0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
+#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13
+#define UTMI_CALIB_CTRL_IMPCAL_START_MASK \
+ (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET)
+#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22
+#define UTMI_CALIB_CTRL_PLLCAL_START_MASK \
+ (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET)
#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23
#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
@@ -45,15 +51,21 @@
#define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
-#define UTMI_TX_CH_CTRL_REG 0xC
+#define UTMI_TX_CH_CTRL_REG 0x0
#define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12
#define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
+#define UTMI_TX_CH_CTRL_AMP_OFFSET 20
+#define UTMI_TX_CH_CTRL_AMP_MASK \
+ (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
-#define UTMI_RX_CH_CTRL0_REG 0x14
+#define UTMI_RX_CH_CTRL0_REG 0x8
+#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8
+#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK \
+ (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET)
#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
@@ -61,15 +73,15 @@
#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
-#define UTMI_RX_CH_CTRL1_REG 0x18
+#define UTMI_RX_CH_CTRL1_REG 0xc
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \
- (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
+ (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \
(0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
-#define UTMI_CTRL_STATUS0_REG 0x24
+#define UTMI_CTRL_STATUS0_REG 0x18
#define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22
#define UTMI_CTRL_STATUS0_SUSPENDM_MASK \
(0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
@@ -77,7 +89,7 @@
#define UTMI_CTRL_STATUS0_TEST_SEL_MASK \
(0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
-#define UTMI_CHGDTC_CTRL_REG 0x38
+#define UTMI_CHGDTC_CTRL_REG 0x2c
#define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8
#define UTMI_CHGDTC_CTRL_VDAT_MASK \
(0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 4d2e730271..fac9606823 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -311,6 +311,17 @@ int regulator_autoset(struct udevice *dev)
return ret;
}
+int regulator_unset(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata;
+
+ uc_pdata = dev_get_uclass_plat(dev);
+ if (uc_pdata && uc_pdata->force_off)
+ return regulator_set_enable(dev, false);
+
+ return -EMEDIUMTYPE;
+}
+
static void regulator_show(struct udevice *dev, int ret)
{
struct dm_regulator_uclass_plat *uc_pdata;
@@ -443,6 +454,7 @@ static int regulator_pre_probe(struct udevice *dev)
uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay",
0);
+ uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off");
node = dev_read_subnode(dev, "regulator-state-mem");
if (ofnode_valid(node)) {
@@ -495,6 +507,32 @@ int regulators_enable_boot_on(bool verbose)
return ret;
}
+int regulators_enable_boot_off(bool verbose)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_REGULATOR, &uc);
+ if (ret)
+ return ret;
+ for (uclass_first_device(UCLASS_REGULATOR, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ ret = regulator_unset(dev);
+ if (ret == -EMEDIUMTYPE) {
+ ret = 0;
+ continue;
+ }
+ if (verbose)
+ regulator_show(dev, ret);
+ if (ret == -ENOSYS)
+ ret = 0;
+ }
+
+ return ret;
+}
+
UCLASS_DRIVER(regulator) = {
.id = UCLASS_REGULATOR,
.name = "regulator",
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index f8d13d193e..17780066ae 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -10,7 +10,6 @@
#include <log.h>
#include <asm/arch/sys_proto.h>
#include <asm/cache.h>
-#include <asm/global_data.h>
#include <asm/io.h>
#include <clk.h>
#include <dm.h>
@@ -156,8 +155,6 @@ struct zynqmp_qspi_dma_regs {
u32 dmadstmsb; /* 0x28 */
};
-DECLARE_GLOBAL_DATA_PTR;
-
struct zynqmp_qspi_plat {
struct zynqmp_qspi_regs *regs;
struct zynqmp_qspi_dma_regs *dma_regs;
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 7642a31b65..06be9deaaa 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -265,6 +265,8 @@ int usb_phy_mode(int port)
}
#endif
+#if !defined(CONFIG_PHY)
+/* Should be done in the MXS PHY driver */
static void usb_oc_config(struct usbnc_regs *usbnc, int index)
{
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
@@ -285,6 +287,7 @@ static void usb_oc_config(struct usbnc_regs *usbnc, int index)
clrbits_le32(ctrl, UCTRL_PWR_POL);
#endif
}
+#endif
#if !CONFIG_IS_ENABLED(DM_USB)
/**
@@ -432,10 +435,12 @@ struct ehci_mx6_priv_data {
struct clk clk;
struct phy phy;
enum usb_init_type init_type;
+#if !defined(CONFIG_PHY)
int portnr;
void __iomem *phy_addr;
void __iomem *misc_addr;
void __iomem *anatop_addr;
+#endif
};
static int mx6_init_after_reset(struct ehci_ctrl *dev)
@@ -448,14 +453,14 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
usb_power_config_mx6(priv->anatop_addr, priv->portnr);
usb_power_config_mx7(priv->misc_addr);
usb_power_config_mx7ulp(priv->phy_addr);
-#endif
usb_oc_config(priv->misc_addr, priv->portnr);
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
@@ -558,6 +563,7 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
static int mx6_parse_dt_addrs(struct udevice *dev)
{
+#if !defined(CONFIG_PHY)
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
int phy_off, misc_off;
const void *blob = gd->fdt_blob;
@@ -594,7 +600,7 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
priv->misc_addr = addr;
-#if !defined(CONFIG_PHY) && defined(CONFIG_MX6)
+#if defined(CONFIG_MX6)
int anatop_off;
/* Resolve ANATOP offset through USB PHY node */
@@ -608,6 +614,7 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
priv->anatop_addr = addr;
#endif
+#endif
return 0;
}
@@ -661,14 +668,14 @@ static int ehci_usb_probe(struct udevice *dev)
usb_power_config_mx6(priv->anatop_addr, priv->portnr);
usb_power_config_mx7(priv->misc_addr);
usb_power_config_mx7ulp(priv->phy_addr);
-#endif
usb_oc_config(priv->misc_addr, priv->portnr);
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
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