diff options
Diffstat (limited to 'include')
178 files changed, 1647 insertions, 6740 deletions
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 6f749736f1..008ebf3ca3 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -61,7 +61,6 @@ typedef struct bd_info { unsigned long bi_vco; /* VCO Out from PLL, in MHz */ #endif #if defined(CONFIG_M68K) - unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif #if defined(CONFIG_EXTRA_CLOCK) @@ -69,23 +68,6 @@ typedef struct bd_info { unsigned long bi_vcofreq; /* vco Freq in MHz */ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ #endif - -#ifdef CONFIG_HAS_ETH1 - unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH2 - unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH3 - unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH4 - unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ -#endif -#ifdef CONFIG_HAS_ETH5 - unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ -#endif - ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ #ifdef CONFIG_NR_DRAM_BANKS diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h deleted file mode 100644 index a515bf9530..0000000000 --- a/include/configs/B4860QDS.h +++ /dev/null @@ -1,759 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * B4860 QDS board configuration file - */ -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg -#ifndef CONFIG_MTD_RAW_NAND -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#else -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif -#endif -#endif - -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#ifndef CONFIG_ARCH_B4420 -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#endif - -/* I2C bus multiplexer */ -#define I2C_MUX_PCA_ADDR 0x77 - -/* VSC Crossbar switches */ -#define CONFIG_VSC_CROSSBAR -#define I2C_CH_DEFAULT 0x8 -#define I2C_CH_VSC3316 0xc -#define I2C_CH_VSC3308 0xd - -#define VSC3316_TX_ADDRESS 0x70 -#define VSC3316_RX_ADDRESS 0x71 -#define VSC3308_TX_ADDRESS 0x02 -#define VSC3308_RX_ADDRESS 0x03 - -/* IDT clock synthesizers */ -#define CONFIG_IDT8T49N222A -#define I2C_CH_IDT 0x9 - -#define IDT_SERDES1_ADDRESS 0x6E -#define IDT_SERDES2_ADDRESS 0x6C - -/* Voltage monitor on channel 2*/ -#define I2C_MUX_CH_VOL_MONITOR 0xa -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -#define CONFIG_ZM7300 -#define I2C_MUX_CH_DPM 0xa -#define I2C_DPM_ADDR 0x28 - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#if 0 -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#endif - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD -#define CONFIG_SYS_DDR_RAW_TIMING - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x53 - -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ - FTIM0_NOR_TEADC(0x04) | \ - FTIM0_NOR_TEAHC(0x20)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ - FTIM2_NOR_TCH(0x0E) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define CONFIG_FSL_QIXIS_V2 -#define QIXIS_BASE 0xffdf0000 -#ifdef CONFIG_PHYS_64BIT -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#else -#define QIXIS_BASE_PHYS QIXIS_BASE -#endif -#define QIXIS_LBMAP_SWITCH 0x01 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x02 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * RapidIO - */ -#ifdef CONFIG_SYS_SRIO -#ifdef CONFIG_SRIO1 -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#endif - -#ifdef CONFIG_SRIO2 -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#else -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 -#endif -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ -#endif -#endif - -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif - -/* - * eSPI - Enhanced SPI - */ - -/* - * MAPLE - */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull -#else -#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 -#endif - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 25 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN - -#define CONFIG_SYS_DPAA_RMAN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x10 -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x11 -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 -#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 - -/*B4860 QDS AMC2PEX-2S default PHY_ADDR */ -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ -#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ - -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f - -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE ulpi - -#ifdef CONFIG_ARCH_B4860 -#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ - "bank_intlv=cs0_cs1;" \ - "en_cpc:cpc2;" -#else -#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - HWCONFIG \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=b4860qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=b4860qds/b4860qds.dtb\0" \ - "bdev=sda3\0" - -/* For emulation this causes u-boot to jump to the start of the proof point - app code automatically */ -#define CONFIG_PROOF_POINTS \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x29000000 - - -;" \ - "cpu 2 release 0x29000000 - - -;" \ - "cpu 3 release 0x29000000 - - -;" \ - "cpu 4 release 0x29000000 - - -;" \ - "cpu 5 release 0x29000000 - - -;" \ - "cpu 6 release 0x29000000 - - -;" \ - "cpu 7 release 0x29000000 - - -;" \ - "go 0x29000000" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x01e00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include <asm/fsl_secure_boot.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h deleted file mode 100644 index 879173f6f2..0000000000 --- a/include/configs/BSC9131RDB.h +++ /dev/null @@ -1,337 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -/* - * BSC9131 RDB board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_NAND_FSL_IFC - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ -#if defined(CONFIG_SYS_CLK_100) -#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ -#else -#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ -#endif - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* enable branch predition */ - -/* DDR Setup */ -#undef CONFIG_SYS_DDR_RAW_TIMING -#undef CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#ifndef __ASSEMBLY__ -extern unsigned long get_sdram_size(void); -#endif -#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -/* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT - -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ - /* CONFIG_SYS_IMMR */ -/* DSP CCSRBAR */ -#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT -#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT - -/* - * Memory map - * - * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable - * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M - * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M - * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M - * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K - * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K - * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K - * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M - * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M - * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M - * - */ - -/* - * IFC Definitions - */ - -/* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -/* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ - | FTIM0_NAND_TWP(0x05) \ - | FTIM0_NAND_TWCHT(0x02) \ - | FTIM0_NAND_TWH(0x04)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ - | FTIM1_NAND_TWBE(0x1E) \ - | FTIM1_NAND_TRR(0x07) \ - | FTIM1_NAND_TRP(0x05)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ - | FTIM2_NAND_TREH(0x04) \ - | FTIM2_NAND_TWHRE(0x11)) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* Set up IFC registers for boot location NAND */ -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -/* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -/* I2C EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* eSPI - Enhanced SPI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 3 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 - -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_HOSTNAME "BSC9131rdb" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "loadaddr=1000000\0" \ - "bootfile=uImage\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=bsc9131rdb.dtb\0" \ - "bdev=sda1\0" \ - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ - "bootm_size=0x37000000\0" \ - "othbootargs=ramdisk_size=600000 " \ - "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h deleted file mode 100644 index ac37ae7cb8..0000000000 --- a/include/configs/BSC9132QDS.h +++ /dev/null @@ -1,548 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* - * BSC9132 QDS board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif -#ifdef CONFIG_NAND_SECBOOT -#define CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -/* - * PCI Windows - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "PCIe Slot" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SYS_CLK_100_DDR_100) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 -#elif defined(CONFIG_SYS_CLK_100_DDR_133) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133000000 -#endif - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* enable branch predition */ - -/* DDR Setup */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ -#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_SDRAM_SIZE (1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -/* DDR3 Controller Settings */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 -#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 -#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 - -#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 -#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 -#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x40461520 -#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 - -#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 -#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 -#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 -#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 -#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 -#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 -#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 -#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 - -/*FIXME: the following params are constant w.r.t diff freq -combinations. this should be removed later -*/ -#if CONFIG_DDR_CLK_FREQ == 100000000 -#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 -#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 -#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 -#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 -#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 -#elif CONFIG_DDR_CLK_FREQ == 133000000 -#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 -#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 -#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 -#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 -#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 -#else -#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 -#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 -#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 -#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 -#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 -#endif - -/* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT - -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - -/* DSP CCSRBAR */ -#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT -#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT - -/* - * IFC Definitions - */ -/* NOR Flash on IFC */ - -#define CONFIG_SYS_FLASH_BASE 0x88000000 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_NOR_CSPR 0x88000101 -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) -/* NOR Flash Timing Params */ - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ - | FTIM0_NOR_TEADC(0x03) \ - | FTIM0_NOR_TAVDS(0x00) \ - | FTIM0_NOR_TEAHC(0x0f)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ - | FTIM1_NOR_TRAD_NOR(0x09) \ - | FTIM1_NOR_TSEQRAD_NOR(0x09)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ - | FTIM2_NOR_TCH(0x4) \ - | FTIM2_NOR_TWPH(0x7) \ - | FTIM2_NOR_TWP(0x1e)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* CFI for NOR Flash */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -/* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ - | FTIM0_NAND_TWP(0x05) \ - | FTIM0_NAND_TWCHT(0x02) \ - | FTIM0_NAND_TWH(0x04)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ - | FTIM1_NAND_TWBE(0x1e) \ - | FTIM1_NAND_TRR(0x07) \ - | FTIM1_NAND_TRP(0x05)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ - | FTIM2_NAND_TREH(0x04) \ - | FTIM2_NAND_TWHRE(0x11)) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* NAND */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_FSL_QIXIS -#endif -#ifdef CONFIG_FSL_QIXIS -#define CONFIG_SYS_FPGA_BASE 0xffb00000 -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_BASE CONFIG_SYS_FPGA_BASE -#define QIXIS_LBMAP_SWITCH 9 -#define QIXIS_LBMAP_MASK 0x07 -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x83 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 - -#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE - -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 -/* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 -#endif - -/* Set up IFC registers for boot location NOR/NAND */ -#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -/* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C EEPROM */ -#define CONFIG_ID_EEPROM -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_BUS_NUM 0 - -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* I2C FPGA */ -#define CONFIG_I2C_FPGA -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 - -#define CONFIG_RTC_DS3231 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * SPI interface will not be available in case of NAND boot SPI CS0 will be - * used for SLIC - */ -/* eSPI - Enhanced SPI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -/* TBI PHY configuration for SGMII mode */ -#define CONFIG_TSEC_TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - -#endif /* CONFIG_TSEC_ENET */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#endif - -/* - * Environment - */ -#if defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_HOSTNAME "BSC9132qds" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" - -#ifdef CONFIG_SDCARD -#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" -#else -#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "loadaddr=1000000\0" \ - "bootfile=uImage\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=bsc9132qds.dtb\0" \ - "bdev=sda1\0" \ - CONFIG_DEF_HWCONFIG\ - "othbootargs=mem=880M ramdisk_size=600000 " \ - "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ - "isolcpus=0\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "debug_halt_off=mw ff7e0e30 0xf0000000;" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#include <asm/fsl_secure_boot.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h deleted file mode 100644 index 9a8cba6b7c..0000000000 --- a/include/configs/C29XPCIE.h +++ /dev/null @@ -1,443 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* - * C29XPCIE board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifdef CONFIG_MTD_RAW_NAND -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_TPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_TPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_NAND_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ - -#ifdef CONFIG_PCI -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -/* - * PCI Windows - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "Slot 1" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DDR_CLK_FREQ 100000000 -#define CONFIG_SYS_CLK_FREQ 66666666 - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ - -/* DDR Setup */ -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x50 -#define CONFIG_SYS_DDR_RAW_TIMING - -/* DDR ECC Setup*/ -#define CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER - -#define CONFIG_SYS_SDRAM_SIZE 512 -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* Platform SRAM setting */ -#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 -#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ - (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) -#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) - -/* - * IFC Definitions - */ -/* NOR Flash on IFC */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ - -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ - -/* 16Bit NOR Flash - S29GL512S10TFI01 */ -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -/* CFI for NOR Flash */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) - -/* 8Bit NAND Flash - K9F1G08U0B */ -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ - | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ - | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ - FTIM0_NAND_TWP(0x0c) | \ - FTIM0_NAND_TWCHT(0x08) | \ - FTIM0_NAND_TWH(0x06)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ - FTIM1_NAND_TWBE(0x1d) | \ - FTIM1_NAND_TRR(0x08) | \ - FTIM1_NAND_TRP(0x0c)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x18)) -#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* Set up IFC registers for boot location NOR/NAND */ -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -/* CPLD on IFC, selected by CS2 */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ - | CONFIG_SYS_CPLD_BASE) - -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 -/* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 - -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -/* - * Config the L2 Cache as L2 SRAM - */ -#if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) -#else -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) -#endif -#endif -#endif - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C EEPROM */ -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* eSPI - Enhanced SPI */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -/* Default mode is RGMII mode */ -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 2 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define CONFIG_ETHPRIME "eTSEC1" -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#if defined(CONFIG_SYS_RAMBOOT) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) -#else -#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE -#endif -#endif - -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "loadaddr=1000000\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=name/of/device-tree.dtb\0" \ - "othbootargs=ramdisk_size=600000\0" \ - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#include <asm/fsl_secure_boot.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index da68f3ccca..21594b4d38 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -239,7 +239,6 @@ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE -#define CONFIG_EEPRO100 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index eaa95bbeff..0cd2e08459 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -172,7 +172,6 @@ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_SKIP_HOST_BRIDGE -#undef CONFIG_EEPRO100 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index d2d1b2fa47..ae79369c6b 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -196,7 +196,6 @@ #define CONFIG_83XX_PCI_STREAMING -#undef CONFIG_EEPRO100 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4707dcf1ab..41ef3d80e1 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -220,7 +220,6 @@ #define CONFIG_83XX_PCI_STREAMING -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index d92312b408..4b43ee1d44 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -275,7 +275,6 @@ #define CONFIG_83XX_PCI_STREAMING -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index b5660f9ff5..49d4aef9ad 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -238,7 +238,6 @@ extern int board_pci_host_broken(void); #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#undef CONFIG_EEPRO100 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ #endif /* CONFIG_PCI */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h deleted file mode 100644 index 340574a985..0000000000 --- a/include/configs/MPC8536DS.h +++ /dev/null @@ -1,642 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. - */ - -/* - * mpc8536ds board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#include "../board/freescale/common/ics307_clk.h" - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_PCI1 1 /* Enable PCI controller 1 */ -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -/* - * Config the L2 Cache as L2 SRAM - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -#if defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ -#define CONFIG_SYS_SPD_BUS_NUM 1 - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 -#define CONFIG_SYS_DDR_MODE_1 0x00480432 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x06180100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2 0x04400010 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 - -/* Make sure required options are set */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Memory map -- xxx -this is wrong, needs updating - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable - * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_BR1_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ - CONFIG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -#define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ -#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ -#ifdef CONFIG_PHYS_64BIT -#define PIXIS_BASE_PHYS 0xfffdf0000ull -#else -#define PIXIS_BASE_PHYS PIXIS_BASE -#endif - -#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ - -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_PWR 0x5 /* PIXIS Power status register */ -#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VSTAT 0x11 /* VELA Status Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ -#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ -#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ -#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ -#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ -#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ -#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ -#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ -#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ -#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ -#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ -#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ -#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ -#define PIXIS_VWATCH 0x24 /* Watchdog Register */ -#define PIXIS_LED 0x25 /* LED Register */ - -#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ - -/* old pixis referenced names */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -#ifndef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#else -#define CONFIG_SYS_NAND_BASE 0xfff00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ - CONFIG_SYS_NAND_BASE + 0x40000, \ - CONFIG_SYS_NAND_BASE + 0x80000, \ - CONFIG_SYS_NAND_BASE + 0xC0000} -#define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) -#define CONFIG_SYS_NAND_U_BOOT_START \ - (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ - | OR_FCM_PGS /* Large Page*/ \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) - -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ - -#define CONFIG_SYS_BR4_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ - -#define CONFIG_SYS_BR6_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_NAND_SPL -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } - -/* - * I2C2 EEPROM - */ -#define CONFIG_ID_EEPROM -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull -#else -#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 -#endif -#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "Slot 1" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "Slot 2" -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, direct to uli, tgtid 3, Base address 8000 */ -#define CONFIG_SYS_PCIE3_NAME "Slot 3" -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -#if defined(CONFIG_PCI) -/*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT - -/*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ - -/* video */ - -#if defined(CONFIG_VIDEO) -#define CONFIG_BIOSEMU -#define CONFIG_ATI_RADEON_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT -#endif - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS - #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define CONFIG_FSL_SGMII_RISER 1 -#define SGMII_RISER_PHY_OFFSET 0x1c - -#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ -#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ - -#if defined(CONFIG_SYS_RAMBOOT) -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#elif defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_MPH_USB -#ifdef CONFIG_HAS_FSL_MPH_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.254 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=8536ds/ramdisk.uboot\0" \ -"fdtaddr=1e00000\0" \ -"fdtfile=8536ds/mpc8536ds.dtb\0" \ -"bdev=sda3\0" \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index f78782a1c1..d2a92619fb 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -112,8 +112,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO -#undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -236,7 +234,6 @@ #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index b2a3201072..834bf7a0ff 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -57,8 +57,6 @@ extern unsigned long get_clock_freq(void); #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") #endif -#undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -282,7 +280,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_PCI2 -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index c9f193fc46..b9c57e1f51 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -63,8 +63,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #error ("CONFIG_SPD_EEPROM is required") #endif -#undef CONFIG_CLOCKS_IN_MHZ - /* * Memory map * @@ -258,7 +256,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #endif -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #ifndef CONFIG_PCI_PNP diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index de2bfd8f2f..1cb62ae849 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -73,7 +73,6 @@ extern unsigned long get_clock_freq(void); #error ("CONFIG_SPD_EEPROM is required") #endif -#undef CONFIG_CLOCKS_IN_MHZ /* * Physical Address Map * @@ -380,7 +379,6 @@ extern unsigned long get_clock_freq(void); #endif #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_DM_PCI) diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index d964b4e121..c25b04e979 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -55,8 +55,6 @@ extern unsigned long get_clock_freq(void); #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") #endif -#undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -280,7 +278,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_PCI2 -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 97d8cc48ed..4d1a417e42 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -113,8 +113,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO -#undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -233,7 +231,6 @@ #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a0bd5f4d40..14663644d1 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -59,8 +59,6 @@ extern unsigned long get_clock_freq(void); #error ("CONFIG_SPD_EEPROM is required") #endif -#undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -290,7 +288,6 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_QE */ #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index beba848214..dd291aca1e 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -109,8 +109,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 #define CONFIG_SYS_DDR_SBE 0x00010000 -#undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -396,7 +394,6 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_QE */ #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 3243f39df4..b4e5e3b3e2 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -118,8 +118,6 @@ #error ("CONFIG_SPD_EEPROM is required") #endif -#undef CONFIG_CLOCKS_IN_MHZ - /* * Memory map * @@ -443,7 +441,6 @@ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #endif -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #ifndef CONFIG_PCI_PNP diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index b2acc72973..c0407bbc16 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -176,8 +176,6 @@ #define CONFIG_SYS_SDRAM_SIZE 256 #endif -#undef CONFIG_CLOCKS_IN_MHZ - #define CONFIG_SYS_INIT_RAM_LOCK 1 #ifndef CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index edbeeefdd4..a7f02aef29 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -221,8 +221,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SDRAM_SIZE 256 #endif -#undef CONFIG_CLOCKS_IN_MHZ - #define CONFIG_SYS_INIT_RAM_LOCK 1 #ifndef CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ @@ -334,7 +332,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP /************************************************************ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h deleted file mode 100644 index 2b761078bc..0000000000 --- a/include/configs/P1022DS.h +++ /dev/null @@ -1,593 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> - * Timur Tabi <timur@freescale.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#include "../board/freescale/common/ics307_clk.h" - -#ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 -#define CONFIG_SYS_NAND_MAX_OOBFREE 5 - -#ifdef CONFIG_MTD_RAW_NAND -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_TPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 4096 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif - -/* High Level Configuration Options */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k - SPL code*/ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_DDR_SPD -#define CONFIG_VERY_BIG_RAM - -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 2048 -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0 0x40110104 -#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 -#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca -#define CONFIG_SYS_DDR_MODE_1 0x00441221 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x0a280100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 -#define CONFIG_SYS_DDR_CONTROL 0xc7000008 -#define CONFIG_SYS_DDR_CONTROL_2 0x24401041 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable - * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable - * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable - * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#else -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#endif - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -#ifndef CONFIG_SYS_MONITOR_BASE -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Nand Flash */ -#if defined(CONFIG_NAND_FSL_ELBC) -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) -#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ - | OR_FCM_PGS /* Large Page*/ \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#else -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#endif - -#endif /* CONFIG_NAND_FSL_ELBC */ - -#define CONFIG_HWCONFIG - -#define CONFIG_FSL_NGPIXIS -#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ -#ifdef CONFIG_PHYS_64BIT -#define PIXIS_BASE_PHYS 0xfffdf0000ull -#else -#define PIXIS_BASE_PHYS PIXIS_BASE -#endif - -#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) - -#define PIXIS_LBMAP_SWITCH 7 -#define PIXIS_LBMAP_MASK 0xF0 -#define PIXIS_LBMAP_ALTBANK 0x20 -#define PIXIS_SPD 0x07 -#define PIXIS_SPD_SYSCLK_MASK 0x07 -#define PIXIS_ELBC_SPI_MASK 0xc0 -#define PIXIS_SPI 0x80 - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Config the L2 Cache as L2 SRAM -*/ -#if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) -#else -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) -#endif -#endif -#endif - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Video */ - -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -/* - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so - * disable empty flash sector detection, which is I/O-intensive. - */ -#undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif - -#ifdef CONFIG_ATI -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT -#define CONFIG_BIOSEMU -#define CONFIG_ATI_RADEON_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET -#endif - -/* I2C */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} -#endif -#define CONFIG_SYS_I2C_FSL - -/* - * I2C2 EEPROM - */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, Slot 1, tgtid 3, Base address b000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -#ifdef CONFIG_TSEC_ENET - -#define CONFIG_TSECV2 - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 2 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) -#endif -#elif defined(CONFIG_SYS_RAMBOOT) -#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#endif - -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_HOSTNAME "p1022ds" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=p1022ds.dtb\0" \ - "bdev=sda3\0" \ - "hwconfig=esdhc;audclk:12\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 8f31fc4c74..ec0c531c46 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -38,8 +38,6 @@ * for your console driver. */ -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index f4440e5764..90480520ab 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -38,8 +38,6 @@ * for your console driver. */ -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h deleted file mode 100644 index 53ae961837..0000000000 --- a/include/configs/T102xQDS.h +++ /dev/null @@ -1,756 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -/* - * T1024/T1023 QDS board configuration file - */ - -#ifndef __T1024QDS_H -#define __T1024QDS_H - -#include <linux/stringify.h> - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DEEP_SLEEP - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg -#endif - -#endif /* CONFIG_RAMBOOT_PBL */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* PCIe Boot - Master */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -#else -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 -#endif -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#else -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 -#endif -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* PCIe Boot - Slave */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -/* Set 1M boot space for PCIe boot */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (256 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#ifdef CONFIG_PHYS_64BIT -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#else -#define QIXIS_BASE_PHYS QIXIS_BASE -#endif -#define QIXIS_LBMAP_SWITCH 0x06 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* Video */ -#ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ -#define CONFIG_FSL_DIU_FB -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -/* - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so - * disable empty flash sector detection, which is I/O-intensive. - */ -#undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif -#endif - -/* I2C */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif - -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ - -#define I2C_MUX_PCA_ADDR 0x77 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ -#define I2C_RETIMER_ADDR 0x18 - -/* I2C bus multiplexer */ -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_DIU 0xC -#define I2C_MUX_CH5 0xD -#define I2C_MUX_CH7 0xF - -/* LDI/DVI Encoder for display */ -#define CONFIG_SYS_I2C_LDI_ADDR 0x38 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 -#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCIe - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE - -#ifdef CONFIG_PCI -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* - *SATA - */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - -/* - * SDHC - */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN - -/* Default address of microcode for the Linux FMan driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#define CONFIG_SYS_QE_FW_ADDR 0x130000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 -#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 -#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 -#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC4" -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ -#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ - "ramdiskfile=t1024qds/ramdisk.uboot\0" \ - "fdtfile=t1024qds/t1024qds.dtb\0" \ - "netdev=eth0\0" \ - "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "fdtaddr=d00000\0" \ - "bdev=sda3\0" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include <asm/fsl_secure_boot.h> - -#endif /* __T1024QDS_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h deleted file mode 100644 index 7ad018b6d7..0000000000 --- a/include/configs/T1040QDS.h +++ /dev/null @@ -1,667 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* - * T1040 QDS board configuration file - */ - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -/* support deep sleep */ -#define CONFIG_DEEP_SLEEP - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ - -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_MTD_NOR_FLASH -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) - -/* - * TDM Definition - */ -#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 - -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#define QIXIS_LBMAP_SWITCH 0x06 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* Video */ -#define CONFIG_FSL_DIU_FB -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -/* - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so - * disable empty flash sector detection, which is I/O-intensive. - */ -#undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif - -/* I2C */ - -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 -#define CONFIG_SYS_FSL_I2C3_SPEED 50000 -#define CONFIG_SYS_FSL_I2C4_SPEED 50000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#endif - -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ - -#define I2C_MUX_PCA_ADDR 0x77 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ - -/* I2C bus multiplexer */ -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_DIU 0xC - -/* LDI/DVI Encoder for display */ -#define CONFIG_SYS_I2C_LDI_ADDR 0x38 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 -#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -#ifdef CONFIG_PCI -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 4, Base address 203000 */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_FSL_ESDHC_ADAPTER_IDENT -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x10 -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x11 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 - -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f - -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* Enable VSC9953 L2 Switch driver */ -#define CONFIG_VSC9953 -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t1040qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=t1040qds/t1040qds.dtb\0" \ - "bdev=sda3\0" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include <asm/fsl_secure_boot.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h deleted file mode 100644 index d92af7202b..0000000000 --- a/include/configs/T4240QDS.h +++ /dev/null @@ -1,555 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -/* - * T4240 QDS board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE4 - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg -#if !defined(CONFIG_MTD_RAW_NAND) && !defined(CONFIG_SDCARD) -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#else -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#endif -#endif /* CONFIG_RAMBOOT_PBL */ - -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_DDR_ECC - -#include "t4qds.h" - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS4 0x54 -#define SPD_EEPROM_ADDRESS5 0x55 -#define SPD_EEPROM_ADDRESS6 0x56 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x83 -#define QIXIS_RST_FORCE_MEM 0x1 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_BRDCFG5 0x55 -#define QIXIS_MUX_SDHC 2 -#define QIXIS_MUX_SDHC_WIDTH8 1 -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -/* I2C */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#else -#undef CONFIG_SYS_I2C -#undef CONFIG_SYS_FSL_I2C2_OFFSET -#undef CONFIG_SYS_FSL_I2C2_SLAVE -#undef CONFIG_SYS_FSL_I2C2_SPEED -#undef CONFIG_SYS_FSL_I2C_SLAVE -#undef CONFIG_SYS_FSL_I2C_SPEED -#undef CONFIG_SYS_FSL_I2C_OFFSET -#endif - -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ - -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_VOL_MONITOR 0xa -#define I2C_MUX_CH_VSC3316_FS 0xc -#define I2C_MUX_CH_VSC3316_BS 0xd - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -/* VSC Crossbar switches */ -#define CONFIG_VSC_CROSSBAR -#define VSC3316_FSM_TX_ADDR 0x70 -#define VSC3316_FSM_RX_ADDR 0x71 - -/* - * RapidIO - */ - -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif -/* - * eSPI - Enhanced SPI - */ - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN -#define CONFIG_SYS_INTERLAKEN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#define FM1_10GEC1_PHY_ADDR 0x0 -#define FM1_10GEC2_PHY_ADDR 0x1 -#define FM2_10GEC1_PHY_ADDR 0x2 -#define FM2_10GEC2_PHY_ADDR 0x3 -#endif - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* -* USB -*/ -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#define CONFIG_ESDHC_DETECT_QUIRK \ - (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ - IS_SVR_REV(get_svr(), 1, 0)) -#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ - (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) -#endif - - -#define __USB_PHY_TYPE utmi - -/* - * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be - * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way - * interleaving. It can be cacheline, page, bank, superbank. - * See doc/README.fsl-ddr for details. - */ -#ifdef CONFIG_ARCH_T4240 -#define CTRL_INTLV_PREFERED 3way_4KB -#else -#define CTRL_INTLV_PREFERED cacheline -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:" \ - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ - "bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t4240qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=t4240qds/t4240qds.dtb\0" \ - "bdev=sda3\0" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include <asm/fsl_secure_boot.h> - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 40fe62fdf0..d43d217956 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -167,8 +167,6 @@ #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ -#undef CONFIG_EEPRO100 -#define CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index cfc9567332..2590a28867 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -227,8 +227,6 @@ #define CONFIG_SYS_DDR_MODE_2 0x8000c000 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 -#undef CONFIG_CLOCKS_IN_MHZ - /* * Memory map * diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index d44028d510..9cbdb1face 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -202,7 +202,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 /* Framebuffer */ -#ifdef CONFIG_VIDEO #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN @@ -211,7 +210,6 @@ #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#endif #define CONFIG_IMX6_PWM_PER_CLK 66000000 diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index cf964373f0..c881ac6211 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -240,7 +240,6 @@ #endif #define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index cc5e8314c7..7cd9ec9659 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -37,7 +37,6 @@ /* Ethernet */ #define CONFIG_DRIVER_TI_EMAC_USE_RMII #define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4a2c39c44d..b7cc1a137b 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -193,7 +193,6 @@ #ifndef CONFIG_SPL_BUILD /* CPSW Ethernet */ #define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #endif diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index e94b7c8d21..adcd9a12e2 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -54,7 +54,6 @@ #define CONFIG_HSMMC2_8BIT /* CPSW Ethernet */ -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index 08d34db106..6dad8216e9 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -103,9 +103,6 @@ #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ #define PHYS_SDRAM_2_SIZE SZ_2G /* 2 GB */ -/* Serial */ -#define CONFIG_BAUDRATE 115200 - /* Monitor Command Prompt */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 6f73606427..519b3b7823 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -12,8 +12,6 @@ #include "tegra124-common.h" -#define CONFIG_ARCH_MISC_INIT - /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 38d0a6e2e9..80262113e3 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -74,7 +74,6 @@ #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CONSOLE_MUX #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/apf27.h b/include/configs/apf27.h index cecd485e20..aaf22acdb5 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -40,7 +40,6 @@ * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 #define CONFIG_HOSTNAME "apf27" #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 624b05ad08..53629743d9 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -19,11 +19,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif -/* general purpose I/O */ -#if !CONFIG_IS_ENABLED(DM_GPIO) -#define CONFIG_AT91_GPIO -#endif - /* * BOOTP options */ diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 378f9dc48b..5e1e590747 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -96,7 +96,6 @@ * CONFIG_DBGU is DBGU unit on J10 * CONFIG_USART1 is USART1 on J14 */ -#define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0/* ignored in arm */ diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 706217fef9..c2d4e485a9 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -25,7 +25,6 @@ #define CONFIG_LCD_LOGO #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_HLCD #define CONFIG_ATMEL_LCD_RGB565 /* diff --git a/include/configs/bcm_northstar2.h b/include/configs/bcm_northstar2.h index 45dc7b29c9..fbfab288b3 100644 --- a/include/configs/bcm_northstar2.h +++ b/include/configs/bcm_northstar2.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_NS16550_COM2 0x66110000 #define CONFIG_SYS_NS16550_COM3 0x66120000 #define CONFIG_SYS_NS16550_COM4 0x66130000 -#define CONFIG_BAUDRATE 115200 /* console configuration */ #define CONFIG_SYS_CBSIZE SZ_1K diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 24569f7d94..01cfed0b86 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -115,7 +115,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * Serial console configuration. */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index f88172a05c..300b9c7b7a 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -57,12 +57,6 @@ "saveenv; " \ "fi; " -/* Autoboot options */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Enter passphrase to stop autoboot, booting in %d seconds\n" -#define CONFIG_AUTOBOOT_STOP_STR "123" - #include <asm/arch/imx-regs.h> #include <linux/sizes.h> diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index 5aa68d1d46..d0cc08baa6 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -16,7 +16,6 @@ #include <configs/bur_am335x_common.h> #include <linux/stringify.h> /* ------------------------------------------------------------------------- */ -#define CONFIG_BOARD_TYPES /* memory */ #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) @@ -70,6 +69,4 @@ BUR_COMMON_ENV \ /* SPI Flash */ /* Environment */ - -#define CONFIG_CONS_INDEX 1 #endif /* __CONFIG_BRSMARC1_H__ */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index 9db011358e..3a18aec5d3 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -15,9 +15,6 @@ #include <configs/bur_am335x_common.h> #include <linux/stringify.h> /* ------------------------------------------------------------------------- */ -#if !defined(CONFIG_AM335X_LCD) -#define CONFIG_AM335X_LCD -#endif #define LCD_BPP LCD_COLOR32 /* memory */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 35f4b74727..a7c667711b 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -155,7 +155,6 @@ #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index c671cb50af..38a56e897e 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -42,12 +42,6 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_BOARD_EARLY_INIT_F - -/* Commands */ - -#undef CONFIG_BOOTM_NETBSD - /* ENET Config */ #define CONFIG_FEC_XCV_TYPE RMII #define FEC_QUIRK_ENET_MAC @@ -140,9 +134,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 -#define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_BOOTCOUNT_ENV - /* Environment organisation */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1, eMMC */ diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index f4dcc54508..a2d198c519 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -147,7 +147,6 @@ /* NAND: SPL related configs */ /* USB configuration */ -#define CONFIG_ARCH_MISC_INIT #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 7d007071e5..8d7222902c 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -135,9 +135,6 @@ #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ -/* Serial */ -#define CONFIG_BAUDRATE 115200 - /* Monitor Command Prompt */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index f5f86f083c..3d3f31369d 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -62,7 +62,6 @@ #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CONSOLE_MUX #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 00e5c8f794..0c36ea6610 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -112,8 +112,6 @@ */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 - #define CONFIG_HOSTNAME "ccdc" #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "ccdc.img" diff --git a/include/configs/corvus.h b/include/configs/corvus.h index e9064a200d..1dc946d789 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -36,7 +36,6 @@ /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ /* serial console */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 4d651264dd..2bb4e47496 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -166,7 +166,6 @@ * Network & Ethernet Configuration */ #ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #endif diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h index cc51e6646e..06a7091be2 100644 --- a/include/configs/db-88f6281-bp.h +++ b/include/configs/db-88f6281-bp.h @@ -11,7 +11,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_TCLK 166666667 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#define CONFIG_BUILD_TARGET "u-boot.kwb" /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 @@ -30,13 +29,6 @@ #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE #define CONFIG_SYS_MAX_NAND_DEVICE 1 -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /* Console on UART0 */ /* * Environment variables configurations diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 21af126c4b..f90c1c5a18 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -65,7 +65,6 @@ /* BOOTP/DHCP options */ #define CONFIG_BOOTP_NISDOMAIN #define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_TIMEOFFSET #undef CONFIG_BOOTP_VENDOREX diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 5bfdf4044b..0b6617fa82 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -62,7 +62,6 @@ /* UART */ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_BAUDRATE 115200 /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/display5.h b/include/configs/display5.h index 3348ecc7c7..94baa65610 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -66,7 +66,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 #ifndef CONFIG_BOOTCOMMAND #define CONFIG_BOOTCOMMAND "if run check_em_pad; then " \ diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h index e9304206bb..ed801dd845 100644 --- a/include/configs/evb_px5.h +++ b/include/configs/evb_px5.h @@ -8,7 +8,6 @@ #include <configs/rk3368_common.h> -#define CONFIG_CONSOLE_SCROLL_LINES 10 #define CONFIG_SYS_MMC_ENV_DEV 0 #endif diff --git a/include/configs/evb_rk3308.h b/include/configs/evb_rk3308.h index 4d40606e4b..0d2cb21ac6 100644 --- a/include/configs/evb_rk3308.h +++ b/include/configs/evb_rk3308.h @@ -14,7 +14,5 @@ #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#undef CONFIG_CONSOLE_SCROLL_LINES -#define CONFIG_CONSOLE_SCROLL_LINES 10 #endif diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h index ed5888bfd3..26687e6386 100644 --- a/include/configs/evb_rk3328.h +++ b/include/configs/evb_rk3328.h @@ -12,6 +12,4 @@ #define SDRAM_BANK_SIZE (2UL << 30) -#define CONFIG_CONSOLE_SCROLL_LINES 10 - #endif diff --git a/include/configs/firefly_rk3308.h b/include/configs/firefly_rk3308.h index 2cc7b4a153..7b8b62fbcb 100644 --- a/include/configs/firefly_rk3308.h +++ b/include/configs/firefly_rk3308.h @@ -14,7 +14,5 @@ #define ROCKCHIP_DEVICE_SETTINGS \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#undef CONFIG_CONSOLE_SCROLL_LINES -#define CONFIG_CONSOLE_SCROLL_LINES 10 #endif diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 261749db8d..1b26466eda 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 -#define CONFIG_CONS_INDEX 1 #endif /* UART */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 47c5974b2e..a959488cb9 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -176,6 +176,4 @@ #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) -#define CONFIG_BCH - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/geekbox.h b/include/configs/geekbox.h index 91f4feb737..4b12eb7af9 100644 --- a/include/configs/geekbox.h +++ b/include/configs/geekbox.h @@ -8,6 +8,4 @@ #include <configs/rk3368_common.h> -#define CONFIG_CONSOLE_SCROLL_LINES 10 - #endif diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 001e9d385b..67301fabeb 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -11,9 +11,6 @@ /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ #define CONFIG_SYS_CLK_FREQ 66666666 -/* Serial Console */ -#define CONFIG_BAUDRATE 115200 - /* Miscellaneous */ #define CONFIG_SYS_PBSIZE 256 #define CONFIG_CMDLINE_TAG @@ -32,9 +29,6 @@ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -/* Kernel Boot */ -#define CONFIG_BOOTARGS "ignore_loglevel" - /* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0 diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 21102d3c14..ce3ba74924 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,10 +9,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE SZ_8K -#endif - #define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 901a1bed6d..382ba620cc 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -10,10 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE SZ_8K -#endif - #define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index a07440c73b..4350b5a62a 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,10 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE SZ_8K -#endif - #define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 7f38f21c09..9c13235982 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,10 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ -#endif - #define CONFIG_SPL_MAX_SIZE (152 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index f71efd45ab..b564f3831e 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -58,8 +58,6 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_BOARD_EARLY_INIT_F - /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) @@ -175,8 +173,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 6d038f21b7..c655bb24a0 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -55,8 +55,6 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_BOARD_EARLY_INIT_F - /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 8324767eb5..1864374a4f 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -35,8 +35,6 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_BOARD_EARLY_INIT_F - /* Flat Device Tree Definitions */ #define CONFIG_OF_BOARD_SETUP @@ -175,9 +173,6 @@ #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ -/* Serial */ -#define CONFIG_BAUDRATE 115200 - /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 89d7adabea..5621ba8232 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -15,8 +15,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x00128000 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#undef CONFIG_BOOTM_NETBSD - #define CONFIG_FSL_USDHC #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -163,9 +161,6 @@ /* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */ #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ -/* Serial */ -#define CONFIG_BAUDRATE 115200 - /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index a58f68c17e..5fdb67f0ec 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -35,8 +35,6 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_BOARD_EARLY_INIT_F - /* Flat Device Tree Definitions */ #define CONFIG_OF_BOARD_SETUP @@ -175,9 +173,6 @@ /* LPDDR4 board total DDR is 3GB */ #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ -/* Serial */ -#define CONFIG_BAUDRATE 115200 - /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index cc18347ff6..96c1d53b9b 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -35,7 +35,6 @@ */ #define CONFIG_TULIP -#define CONFIG_EEPRO100 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ /*----------------------------------------------------------------------- diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 25f3959533..83466b9e0c 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -82,7 +82,6 @@ #define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ #ifndef CONFIG_SPL_BUILD -#define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 #endif diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index d7ebfeda4c..e7a7ae3198 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00 -#define CONFIG_CONS_INDEX 3 #endif diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 59d65f8891..b0a150dbfb 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -138,11 +138,6 @@ #define CONFIG_SPI_FLASH_SPANSION #endif -/* DM SPI */ -#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) -#define CONFIG_DM_SPI_FLASH -#endif - /* * eTSEC */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index e069467b53..0779b595c3 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -363,11 +363,6 @@ unsigned long get_board_ddr_clk(void); * MMC */ -/* DM SPI */ -#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) -#define CONFIG_DM_SPI_FLASH -#endif - /* * Video */ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 46c60aaf5c..72aed8fed6 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,9 +60,9 @@ #define CONFIG_SYS_FSL_PBL_RCW \ "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_SECURE_BOOT */ +#endif /* ifdef CONFIG_NXP_ESBC */ #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 @@ -97,15 +97,12 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 /* Serial Port */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() -#define CONFIG_BAUDRATE 115200 - /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 53a10ba4dd..16c30d09dc 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -234,11 +234,6 @@ * MMC */ -/* DM SPI */ -#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) -#define CONFIG_DM_SPI_FLASH -#endif - /* * Video */ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index f9040e661d..d184673a71 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -43,12 +43,10 @@ #endif /* Serial Port */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* Miscellaneous configurable options */ @@ -88,10 +86,6 @@ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ -#ifndef CONFIG_CMDLINE_EDITING -#define CONFIG_CMDLINE_EDITING 1 -#endif - #define CONFIG_SYS_MAXARGS 64 /* max command args */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index b18eab51ed..3efac1fa78 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -174,9 +174,7 @@ /* DSPI */ #ifndef SPL_NO_DSPI -#define CONFIG_FSL_DSPI #ifdef CONFIG_FSL_DSPI -#define CONFIG_DM_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ #define CONFIG_SPI_FLASH_SST /* cs1 */ #define CONFIG_SPI_FLASH_EON /* cs2 */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 596f14bf3e..3ea16752de 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -64,7 +64,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 5ab924457e..9bc287f7aa 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -20,7 +20,6 @@ #define CONFIG_SYS_FLASH_BASE 0x20000000 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F 1 /* DDR */ #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ @@ -78,7 +77,6 @@ (void *)CONFIG_SYS_SERIAL1, \ (void *)CONFIG_SYS_SERIAL2, \ (void *)CONFIG_SYS_SERIAL3 } -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* MC firmware */ diff --git a/include/configs/malta.h b/include/configs/malta.h index 773d7c23ed..9602773ff9 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -15,8 +15,6 @@ #define CONFIG_PCI_GT64120 #define CONFIG_PCI_MSC01 -#define CONFIG_PCNET -#define PCNET_HAS_PROM #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 9b9218d296..c6752f4acb 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -32,7 +32,6 @@ #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 -#define CONFIG_CONS_INDEX 1 #endif /* Serial common */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index bb6d82d327..8c7d1395d0 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -33,7 +33,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 /* Command definition */ @@ -145,8 +144,6 @@ #define CONFIG_FSL_IIM -#define CONFIG_BCH - /* Backlight Control */ #define CONFIG_IMX6_PWM_PER_CLK 66666000 diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index b774b167f6..0a28d61703 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -27,7 +27,6 @@ #else #error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx) #endif -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16) diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 942b7dd414..9e93269074 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -32,14 +32,11 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) -#define CONFIG_BOARD_EARLY_INIT_F - /* UART */ #define LPUART_BASE LPUART4_RBASE /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_CACHELINE_SIZE 64 diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 58fa5ccfa3..58fc10d31f 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -157,7 +157,6 @@ #ifdef CONFIG_DRIVER_TI_EMAC #undef CONFIG_DRIVER_TI_EMAC_USE_RMII #define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #endif diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h index f77a5fa4c1..4ef9e8ed5d 100644 --- a/include/configs/owl-common.h +++ b/include/configs/owl-common.h @@ -12,7 +12,6 @@ /* SDRAM Definitions */ #define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 /* Generic Timer Definitions */ #define COUNTER_FREQUENCY (24000000) /* 24MHz */ @@ -29,9 +28,6 @@ */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00) -/* UART Definitions */ -#define CONFIG_BAUDRATE 115200 - /* Console configuration */ #define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 219e5d216b..6b57be912a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -300,8 +300,6 @@ #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 #endif -#undef CONFIG_CLOCKS_IN_MHZ - /* * Memory map * diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h deleted file mode 100644 index d731f9c8fa..0000000000 --- a/include/configs/p1_twr.h +++ /dev/null @@ -1,480 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* - * QorIQ P1 Tower boards configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -#if defined(CONFIG_TWR_P1025) -#define CONFIG_BOARDNAME "TWR-P1025" -#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ -#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ - -#define CONFIG_DDR_CLK_FREQ 66666666 - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ - -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -/* Default settings for DDR3 */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00220004 -#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 -#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x80461320 -#define CONFIG_SYS_DDR_MODE_2 0x00008000 -#define CONFIG_SYS_DDR_INTERVAL 0x09480000 - -/* - * Memory map - * - * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable - * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * - * Localbus - * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable - * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable - * - * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable - * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ - | BR_PS_16 | BR_V) - -#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 - -#define CONFIG_SYS_SSD_BASE 0xe0000000 -#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE -#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ - BR_PS_16 | BR_V) -#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - -#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM -#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -/* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -/* Size of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ - -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ - -/* Serial Port - * open - index 2 - * shorted - index 1 - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 - -/* - * I2C2 EEPROM - */ -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 - -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -#if defined(CONFIG_PCI) -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#undef CONFIG_TSEC2 -#undef CONFIG_TSEC2_NAME -#define CONFIG_TSEC3 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#undef CONFIG_HAS_ETH2 -#endif /* CONFIG_TSEC_ENET */ - -#ifdef CONFIG_QE -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#endif /* CONFIG_QE */ - -#ifdef CONFIG_TWR_P1025 -/* - * QE UEC ethernet configuration - */ -#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) - -#undef CONFIG_UEC_ETH -#define CONFIG_PHY_MODE_NEED_CHANGE - -#define CONFIG_UEC_ETH1 /* ETH1 */ -#define CONFIG_HAS_ETH0 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif /* CONFIG_UEC_ETH1 */ - -#define CONFIG_UEC_ETH5 /* ETH5 */ -#define CONFIG_HAS_ETH1 - -#ifdef CONFIG_UEC_ETH5 -#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ -#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ -#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ -#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 -#endif /* CONFIG_UEC_ETH5 */ -#endif /* CONFIG_TWR-P1025 */ - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#ifdef CONFIG_SYS_RAMBOOT -#ifdef CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"loadaddr=1000000\0" \ -"bootfile=uImage\0" \ -"dtbfile=twr-p1025twr.dtb\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ -"kernelflash=tftpboot $loadaddr $bootfile; " \ - "protect off 0xefa80000 +$filesize; " \ - "erase 0xefa80000 +$filesize; " \ - "cp.b $loadaddr 0xefa80000 $filesize; " \ - "protect on 0xefa80000 +$filesize; " \ - "cmp.b $loadaddr 0xefa80000 $filesize\0" \ -"dtbflash=tftpboot $loadaddr $dtbfile; " \ - "protect off 0xefe80000 +$filesize; " \ - "erase 0xefe80000 +$filesize; " \ - "cp.b $loadaddr 0xefe80000 $filesize; " \ - "protect on 0xefe80000 +$filesize; " \ - "cmp.b $loadaddr 0xefe80000 $filesize\0" \ -"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ - "protect off 0xeeb80000 +$filesize; " \ - "erase 0xeeb80000 +$filesize; " \ - "cp.b $loadaddr 0xeeb80000 $filesize; " \ - "protect on 0xeeb80000 +$filesize; " \ - "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ -"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ - "protect off 0xefec0000 +$filesize; " \ - "erase 0xefec0000 +$filesize; " \ - "cp.b $loadaddr 0xefec0000 $filesize; " \ - "protect on 0xefec0000 +$filesize; " \ - "cmp.b $loadaddr 0xefec0000 $filesize\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"fdtaddr=1e00000\0" \ -"bdev=sda1\0" \ -"norbootaddr=ef080000\0" \ -"norfdtaddr=ef040000\0" \ -"ramdisk_size=120000\0" \ -"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ -"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" - -#define CONFIG_NFSBOOTCOMMAND \ -"setenv bootargs root=/dev/nfs rw " \ -"nfsroot=$serverip:$rootpath " \ -"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $loadaddr $bootfile&&" \ -"tftp $fdtaddr $fdtfile&&" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_HDBOOT \ -"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"usb start;" \ -"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ -"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_USB_FAT_BOOT \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"usb start;" \ -"fatload usb 0:2 $loadaddr $bootfile;" \ -"fatload usb 0:2 $fdtaddr $fdtfile;" \ -"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_USB_EXT2_BOOT \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"usb start;" \ -"ext2load usb 0:4 $loadaddr $bootfile;" \ -"ext2load usb 0:4 $fdtaddr $fdtfile;" \ -"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_NORBOOT \ -"setenv bootargs root=/dev/mtdblock3 rw " \ -"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ -"bootm $norbootaddr - $norfdtaddr" - -#define CONFIG_RAMBOOTCOMMAND_TFTP \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"tftp $ramdiskaddr $ramdiskfile;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"bootm 0xefa80000 0xeeb80000 0xefe80000" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index d524f3cbcf..e4b14c5ecd 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -73,6 +73,5 @@ #define CONFIG_SYS_NS16550_COM4 UART3_BASE #define CONFIG_SYS_NS16550_COM5 UART4_BASE #define CONFIG_SYS_NS16550_COM6 UART5_BASE -#define CONFIG_BAUDRATE 115200 #endif /* ! __CONFIG_PDU001_H */ diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 2ae13b30ee..da2842934b 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -54,8 +54,6 @@ #define CONFIG_REMAKE_ELF -#define CONFIG_BOARD_EARLY_INIT_F - /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) @@ -150,8 +148,6 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ (PHYS_SDRAM_SIZE >> 1)) -#define CONFIG_BAUDRATE 115200 - #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index 2747c0cb93..3eb70d5e78 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -28,11 +28,9 @@ /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ /* serial console */ -#define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS diff --git a/include/configs/pinebook-pro-rk3399.h b/include/configs/pinebook-pro-rk3399.h index 4bc8802d11..d478b19917 100644 --- a/include/configs/pinebook-pro-rk3399.h +++ b/include/configs/pinebook-pro-rk3399.h @@ -14,15 +14,9 @@ #include <configs/rk3399_common.h> -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_ENV_SECT_SIZE (8 * 1024) -#endif - -#undef CONFIG_SYS_SPI_U_BOOT_OFFS -#define CONFIG_SYS_SPI_U_BOOT_OFFS 1024 * 512 - #define SDRAM_BANK_SIZE (2UL << 30) +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + #endif diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 51177f44fe..34235b5a00 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -41,7 +41,6 @@ #define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1} -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_SERIAL0 PER_UART0_CFG #define CONFIG_SYS_SERIAL1 PER_UART1_CFG diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index d6c70601dd..76d6ab1c8b 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -32,9 +32,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -/* MMC/SD IP block */ -//#define CONFIG_BOUNCE_BUFFER - #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h index 2632d48cc9..52d77e06ac 100644 --- a/include/configs/pxa-common.h +++ b/include/configs/pxa-common.h @@ -16,13 +16,6 @@ #endif /* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_PXA_MMC_GENERIC -#endif - -/* * OHCI USB */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index d0c9e5c809..8f1d508b8c 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index e57d0efa7f..f178a06945 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h index 5c6692c199..e207ca45fd 100644 --- a/include/configs/s32v234evb.h +++ b/include/configs/s32v234evb.h @@ -151,11 +151,6 @@ #define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR) #endif -#if 0 -/* Configure PXE */ -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 -#endif - /* Physical memory map */ /* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */ #define PHYS_SDRAM (DDR_BASE_ADDR) diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 9b439a6441..19714402ca 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -44,7 +44,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_MASK_ALE BIT(21) @@ -54,12 +53,6 @@ #define CONFIG_SYS_NAND_ONFI_DETECTION #endif -/* PMECC & PMERRLOC */ -#define CONFIG_ATMEL_NAND_HWECC -#define CONFIG_ATMEL_NAND_HW_PMECC -#define CONFIG_PMECC_CAP 8 -#define CONFIG_PMECC_SECTOR_SIZE 512 - #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #ifdef CONFIG_SD_BOOT diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 8e98254e2d..4d66490cd6 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -39,12 +39,6 @@ "bootz 0x22000000 - 0x21000000" #endif -#ifdef CONFIG_QSPI_BOOT -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" -#endif - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x10000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index 2d1ba757fe..7d6886ea73 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -44,9 +44,6 @@ #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \ "fatload mmc 0:1 0x22000000 zImage; " \ "bootz 0x22000000 - 0x21000000" -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" #endif /* SPL */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 2a81f3a9bc..1a981a7c37 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -67,7 +67,6 @@ #define CONFIG_KEEP_SERVERADDR #define CONFIG_UDP_CHECKSUM #define CONFIG_TIMESTAMP -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_SERVERIP @@ -94,9 +93,9 @@ #endif #define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ - "eth1addr=00:00:11:22:33:45\0" \ - "eth3addr=00:00:11:22:33:46\0" \ - "eth5addr=00:00:11:22:33:47\0" \ + "eth3addr=00:00:11:22:33:45\0" \ + "eth5addr=00:00:11:22:33:46\0" \ + "eth6addr=00:00:11:22:33:47\0" \ "ipaddr=1.2.3.4\0" #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 5adf5a8ca4..cca596d43a 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -180,7 +180,6 @@ #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 55c4bff28a..f94683329b 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -118,8 +118,6 @@ #define CONFIG_SYS_DDR_CONTROL 0xc300c000 #endif -#undef CONFIG_CLOCKS_IN_MHZ - /* * FLASH on the Local Bus * Two banks, one 8MB the other 64MB, using the CFI driver. @@ -434,7 +432,6 @@ #endif #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 4ab364ae9a..5b93ccbda1 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -206,8 +206,6 @@ #define CONFIG_SYS_WRITE_SWAPPED_DATA #define CONFIG_SYS_FLASH_EMPTY_INFO -#undef CONFIG_CLOCKS_IN_MHZ - #define CONFIG_SYS_INIT_RAM_LOCK 1 #ifndef CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ @@ -276,7 +274,6 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/sheep_rk3368.h b/include/configs/sheep_rk3368.h index 238838fd7d..550597c957 100644 --- a/include/configs/sheep_rk3368.h +++ b/include/configs/sheep_rk3368.h @@ -13,6 +13,4 @@ #define DTB_LOAD_ADDR 0x5600000 #define INITRD_LOAD_ADDR 0x5bf0000 -#define CONFIG_CONSOLE_SCROLL_LINES 10 - #endif diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index ed93117650..d146ba51de 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -171,7 +171,6 @@ */ #define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h new file mode 100644 index 0000000000..a46473fc78 --- /dev/null +++ b/include/configs/sipeed-maix.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> + */ + +#ifndef CONFIGS_SIPEED_MAIX_H +#define CONFIGS_SIPEED_MAIX_H + +#include <linux/sizes.h> + +#define CONFIG_SYS_LOAD_ADDR 0x80000000 +/* Start just below the second bank so we don't clobber it during reloc */ +#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF +#define CONFIG_SYS_MALLOC_LEN SZ_128K +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* Don't relocate into AI ram since it isn't set up yet */ +#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M) + +/* For early init */ +#define K210_SYSCTL_BASE 0x50440000 + +#endif /* CONFIGS_SIPEED_MAIX_H */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index aacdd1263e..9498513f76 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -85,11 +85,9 @@ /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO /* enable the GPIO features */ #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ /* serial console */ -#define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 35cd7f69c1..cbef61877e 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -62,14 +62,12 @@ /* GPIOs and IO expander */ #define CONFIG_ATMEL_LEGACY -#define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } /* UARTs/Serial console */ -#define CONFIG_ATMEL_USART #ifndef CONFIG_DM_SERIAL #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index fcd35b715c..24bbea7d03 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -60,11 +60,9 @@ /* GPIOs and IO expander */ #define CONFIG_ATMEL_LEGACY -#define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 /* UARTs/Serial console */ -#define CONFIG_ATMEL_USART /* Boot options */ #define CONFIG_SYS_LOAD_ADDR 0x23000000 diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index ad4c3c0786..eb17470ae6 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -28,12 +28,7 @@ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* Booting Linux */ -#define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS \ - "console=ttyS0," __stringify(CONFIG_BAUDRATE) \ - " ubi.fm_autoconvert=1" \ - " uio_pdrv_genirq.of_id=\"idq,regbank\"" #define CONFIG_BOOTCOMMAND \ "setenv bootcmd '" \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 7237ec95e3..775a122f1f 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -79,7 +79,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * CONFIG_BOOTARGS goes into the environment value "bootargs". * Do note the value will override also the chosen node in FDT blob. */ -#define CONFIG_BOOTARGS "earlycon" #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ "run mmcboot" diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index f271b84a59..ed20b842ac 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -123,7 +123,7 @@ * for serial/usb: execute the stm32prog command * for mmc boot (eMMC, SD card), boot only on the same device * for nand or spi-nand boot, boot with on ubifs partition on UBI partition - * for nor boot, use the default order + * for nor boot, use SD card = mmc0 */ #define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ "echo \"Boot over ${boot_device}${boot_instance}!\";" \ @@ -136,6 +136,8 @@ "if test ${boot_device} = nand ||" \ " test ${boot_device} = spi-nand ;" \ "then env set boot_targets ubifs0; fi;" \ + "if test ${boot_device} = nor;" \ + "then env set boot_targets mmc0; fi;" \ "run distro_bootcmd;" \ "fi;\0" @@ -155,9 +157,7 @@ "splashimage=0xc4300000\0" \ "ramdisk_addr_r=0xc4400000\0" \ "altbootcmd=run bootcmd\0" \ - "env_default=1\0" \ - "env_check=if test $env_default -eq 1;"\ - " then env set env_default 0;env save;fi\0" \ + "env_check=if env info -p -d; then env save; fi\0" \ STM32MP_BOOTCMD \ BOOTENV \ "boot_net_usb_start=true\0" diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index b5bfac77f1..d9c79907ac 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -19,12 +19,6 @@ #define CONFIG_TIMESTAMP -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 root=/dev/ram0 rw " \ - "rootfstype=ramfs " \ - "rdinit=/bin/init " \ - "devtmpfs.mount=1" - #define CONFIG_BOOTCOMMAND \ "sf probe 0:1 50000000; " \ "sf read ${loadaddr} 0x100000 ${kern_size}; " \ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index c13e997921..060030b838 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -120,7 +120,6 @@ * */ #define CONFIG_DRIVER_TI_EMAC_USE_RMII -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 9990c9340a..b9b9292502 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -41,7 +41,6 @@ /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 7376b91f55..eb16eb3d8a 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -37,11 +37,9 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ /* Framebuffer */ -#ifdef CONFIG_VIDEO #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#endif /* PCI */ #ifdef CONFIG_CMD_PCI @@ -76,6 +74,7 @@ #define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */ #define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \ @@ -92,20 +91,29 @@ "bootm 0x10800000 0x10d00000\0" \ "console=ttymxc0\0" \ "fan=gpio set 92\0" \ + "fdt_addr=0x13000000\0" \ + "fdt_addr_r=0x13000000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "kernel_addr_r=0x10008000\0" \ + "pxefile_addr_r=0x10008000\0" \ + "ramdisk_addr_r=0x18000000\0" \ + "scriptaddr=0x14000000\0" \ "set_con_serial=setenv stdout serial; " \ "setenv stderr serial\0" \ - "set_con_hdmi=setenv stdout serial,vga; " \ - "setenv stderr serial,vga\0" \ - "stderr=serial,vga\0" \ + "set_con_hdmi=setenv stdout serial,vidconsole; " \ + "setenv stderr serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ "stdin=serial,usbkbd\0" \ - "stdout=serial,vga\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "if run bootcmd_up1; then " \ - "run bootcmd_up2; " \ - "else " \ - "run bootcmd_mmc; " \ - "fi" + "stdout=serial,vidconsole\0" + +/* Enable distro boot */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(SATA, sata, 0) \ + func(USB, usb, 0) + +#include <config_distro_bootcmd.h> #endif /* __TBS2910_CONFIG_H * */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 99ddc3e923..264b1f1a4c 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -145,7 +145,6 @@ #endif /* Ethernet */ -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_PHY_ET1011C_TX_CLK_FIX diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index d16d61e5cd..01a174b29f 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -88,7 +88,6 @@ #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ CONFIG_SPL_TEXT_BASE) -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 19e1e2249e..4b3981b9b0 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -27,7 +27,6 @@ #ifndef CONFIG_SPL_BUILD /* Network defines. */ -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #endif diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index b632ae010d..fb1dc2dbeb 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -67,7 +67,6 @@ /* Network Configuration */ #define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 32 #define CONFIG_SYS_SGMII_REFCLK_MHZ 312 diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index d5b2a785bc..82a8fa7354 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -23,8 +23,6 @@ #endif #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ -#define CONFIG_BOARD_TYPES - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) #define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) @@ -36,11 +34,8 @@ #error Unknown DDR size - please add! #endif -#define CONFIG_CONS_INDEX 1 - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_BOARD_EARLY_INIT_R #if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) #define VCOREIII_DEFAULT_MTD_ENV \ "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index ca528598f2..878c4996df 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -9,10 +9,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE SZ_8K -#endif - #define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 09cdd3dab5..e63c335f85 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -68,7 +68,7 @@ #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) /* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ +#define COUNTER_FREQUENCY 24000000 /* 24MHz */ /* Generic Interrupt Controller Definitions */ #ifdef CONFIG_GICV3 diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index ca765579e8..ffc3b43fc5 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -135,7 +135,6 @@ #define CONFIG_SYS_SERIAL0 V2M_UART0 #define CONFIG_SYS_SERIAL1 V2M_UART1 -#define CONFIG_ARM_PL180_MMCI #define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 #define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 83ec78dc43..496c228b58 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -17,7 +17,6 @@ /* The value in the common file is too far away for the VInCo platform */ /* serial console */ -#define CONFIG_ATMEL_USART #define CONFIG_USART_BASE 0xfc00c000 #define CONFIG_USART_ID 30 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 3f578720e5..52d632ba0a 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -155,7 +155,6 @@ #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 #undef CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 5aa3ad8ddf..40467b737c 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -34,7 +34,6 @@ #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00 -#define CONFIG_CONS_INDEX 3 /* RAM */ diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h index d256ce8e4b..6ae777507f 100644 --- a/include/configs/wb45n.h +++ b/include/configs/wb45n.h @@ -20,10 +20,8 @@ /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO /* serial console */ -#define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS @@ -85,10 +83,6 @@ #error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' #endif -#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \ - "rw noinitrd mem=64M " \ - "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6" - #define CONFIG_EXTRA_ENV_SETTINGS \ "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ "autoload=no\0" \ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h index bb4deeac9b..c65e591342 100644 --- a/include/configs/wb50n.h +++ b/include/configs/wb50n.h @@ -20,11 +20,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif -/* general purpose I/O */ -#define CONFIG_AT91_GPIO - /* serial console */ -#define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_DBGU @@ -73,11 +69,6 @@ "nand read 0x22000000 0x000e0000 0x500000; " \ "bootm" -#define CONFIG_BOOTARGS \ - "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE \ diff --git a/include/configs/x530.h b/include/configs/x530.h index 7e0f2c24d9..4446510df4 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -30,8 +30,6 @@ * for your console driver. */ -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ - /* NAND */ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/xea.h b/include/configs/xea.h index 65109566d3..144f62e8f9 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -43,7 +43,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " #define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 1276612503..804525dcad 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -108,7 +108,7 @@ "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ - "xspi " + "xspi0 " #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index e868c13416..e7cfebee7c 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -256,6 +256,4 @@ # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" #endif -#define CONFIG_BOARD_EARLY_INIT_F - #endif /* __XILINX_ZYNQMP_H */ diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index ae751aa395..3f57423b78 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -24,5 +24,7 @@ /* BOOTP options */ #undef CONFIG_BOOTP_BOOTFILESIZE #undef CONFIG_BOOTP_MAY_FAIL +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 #endif /* __CONFIG_ZYNQMP_MINI_H */ diff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h new file mode 100644 index 0000000000..812933f51c --- /dev/null +++ b/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __fsl_espi_h +#define __fsl_espi_h + +struct fsl_espi_platdata { + uint flags; + uint speed_hz; + uint num_chipselect; + fdt_addr_t regs_addr; +}; + +#endif /* __fsl_espi_h */ diff --git a/include/dm/platform_data/pxa_mmc_gen.h b/include/dm/platform_data/pxa_mmc_gen.h new file mode 100644 index 0000000000..9875bab2cf --- /dev/null +++ b/include/dm/platform_data/pxa_mmc_gen.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Marcel Ziswiler <marcel.ziswiler@toradex.com> + */ + +#ifndef __PXA_MMC_GEN_H +#define __PXA_MMC_GEN_H + +#include <mmc.h> + +/* + * struct pxa_mmc_platdata - information about a PXA MMC controller + * + * @base: MMC controller base register address + */ +struct pxa_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; + struct pxa_mmc_regs *base; +}; + +#endif /* __PXA_MMC_GEN_H */ diff --git a/include/dm/platform_data/serial_pxa.h b/include/dm/platform_data/serial_pxa.h index 408c00885d..b78bdb6409 100644 --- a/include/dm/platform_data/serial_pxa.h +++ b/include/dm/platform_data/serial_pxa.h @@ -17,7 +17,7 @@ #define FFUART_INDEX 1 #define STUART_INDEX 2 #elif CONFIG_CPU_PXA25X -#define UART_CLK_BASE (1 << 4) /* HWUART */ +#define UART_CLK_BASE BIT(4) /* HWUART */ #define UART_CLK_REG CKEN #define HWUART_INDEX 0 #define STUART_INDEX 1 @@ -42,9 +42,9 @@ /* * struct pxa_serial_platdata - information about a PXA port * - * @base: Uart port base register address - * @port: Uart port index, for cpu with pinmux for uart / gpio - * baudrtatre: Uart port baudrate + * @base: Uart port base register address + * @port: Uart port index, for cpu with pinmux for uart / gpio + * baudrtatre: Uart port baudrate */ struct pxa_serial_platdata { struct pxa_uart_regs *base; diff --git a/include/dm/read.h b/include/dm/read.h index b952551d55..f02ec95954 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -799,7 +799,9 @@ static inline fdt_addr_t dev_read_addr(const struct udevice *dev) static inline void *dev_read_addr_ptr(const struct udevice *dev) { - return devfdt_get_addr_ptr(dev); + void *addr = devfdt_get_addr_ptr(dev); + + return ((fdt_addr_t)(uintptr_t)addr == FDT_ADDR_T_NONE) ? NULL : addr; } static inline fdt_addr_t dev_read_addr_pci(const struct udevice *dev) @@ -923,8 +925,12 @@ static inline const void *dev_read_prop_by_prop(struct ofprop *prop, static inline int dev_read_alias_seq(const struct udevice *dev, int *devnump) { +#if CONFIG_IS_ENABLED(OF_CONTROL) return fdtdec_get_alias_seq(gd->fdt_blob, dev->uclass->uc_drv->name, dev_of_offset(dev), devnump); +#else + return -ENOTSUPP; +#endif } static inline int dev_read_u32_array(const struct udevice *dev, @@ -983,6 +989,8 @@ static inline u64 dev_translate_dma_address(const struct udevice *dev, static inline int dev_read_alias_highest_id(const char *stem) { + if (!CONFIG_IS_ENABLED(OF_LIBFDT)) + return -1; return fdtdec_get_alias_highest_id(gd->fdt_blob, stem); } diff --git a/include/dm/util.h b/include/dm/util.h index 23f8deb14e..9773db6de1 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -42,4 +42,10 @@ static inline void dm_dump_devres(void) /* Dump out a list of drivers */ void dm_dump_drivers(void); +/* Dump out a list with each driver's compatibility strings */ +void dm_dump_driver_compat(void); + +/* Dump out a list of drivers with static platform data */ +void dm_dump_static_driver_info(void); + #endif diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h new file mode 100644 index 0000000000..0e3ed3fb9f --- /dev/null +++ b/include/dt-bindings/clock/k210-sysctl.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> + */ + +#ifndef CLOCK_K210_SYSCTL_H +#define CLOCK_K210_SYSCTL_H + +/* + * Arbitrary identifiers for clocks. + */ +#define K210_CLK_NONE 0 +#define K210_CLK_IN0_H 1 +#define K210_CLK_PLL0_H 2 +#define K210_CLK_PLL0 3 +#define K210_CLK_PLL1 4 +#define K210_CLK_PLL2 5 +#define K210_CLK_PLL2_H 6 +#define K210_CLK_CPU 7 +#define K210_CLK_SRAM0 8 +#define K210_CLK_SRAM1 9 +#define K210_CLK_APB0 10 +#define K210_CLK_APB1 11 +#define K210_CLK_APB2 12 +#define K210_CLK_ROM 13 +#define K210_CLK_DMA 14 +#define K210_CLK_AI 15 +#define K210_CLK_DVP 16 +#define K210_CLK_FFT 17 +#define K210_CLK_GPIO 18 +#define K210_CLK_SPI0 19 +#define K210_CLK_SPI1 20 +#define K210_CLK_SPI2 21 +#define K210_CLK_SPI3 22 +#define K210_CLK_I2S0 23 +#define K210_CLK_I2S1 24 +#define K210_CLK_I2S2 25 +#define K210_CLK_I2S0_M 26 +#define K210_CLK_I2S1_M 27 +#define K210_CLK_I2S2_M 28 +#define K210_CLK_I2C0 29 +#define K210_CLK_I2C1 30 +#define K210_CLK_I2C2 31 +#define K210_CLK_UART1 32 +#define K210_CLK_UART2 33 +#define K210_CLK_UART3 34 +#define K210_CLK_AES 35 +#define K210_CLK_FPIOA 36 +#define K210_CLK_TIMER0 37 +#define K210_CLK_TIMER1 38 +#define K210_CLK_TIMER2 39 +#define K210_CLK_WDT0 40 +#define K210_CLK_WDT1 41 +#define K210_CLK_SHA 42 +#define K210_CLK_OTP 43 +#define K210_CLK_RTC 44 +#define K210_CLK_ACLK 45 + +#endif /* CLOCK_K210_SYSCTL_H */ diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h new file mode 100644 index 0000000000..88d73be84b --- /dev/null +++ b/include/dt-bindings/clock/omap4.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2017 Texas Instruments, Inc. + */ +#ifndef __DT_BINDINGS_CLK_OMAP4_H +#define __DT_BINDINGS_CLK_OMAP4_H + +#define OMAP4_CLKCTRL_OFFSET 0x20 +#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) + +/* mpuss clocks */ +#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* tesla clocks */ +#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* abe clocks */ +#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) +#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) +#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) +#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) +#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) + +/* l4_ao clocks */ +#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) + +/* l3_1 clocks */ +#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_2 clocks */ +#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) + +/* ducati clocks */ +#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_dma clocks */ +#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_emif clocks */ +#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) + +/* d2d clocks */ +#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l4_cfg clocks */ +#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) + +/* l3_instr clocks */ +#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) + +/* ivahd clocks */ +#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) + +/* iss clocks */ +#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) + +/* l3_dss clocks */ +#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_gfx clocks */ +#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_init clocks */ +#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) +#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) + +/* l4_per clocks */ +#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) +#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) +#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) +#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) +#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) +#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) +#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) +#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) +#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) +#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) +#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) +#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) +#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) +#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) +#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) +#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) +#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) +#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) +#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) +#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) +#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) +#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) +#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) + +/* l4_secure clocks */ +#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) +#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) +#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) +#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) +#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) +#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) +#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) +#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) + +/* l4_wkup clocks */ +#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) + +/* emu_sys clocks */ +#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +#endif diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h new file mode 100644 index 0000000000..41775272fd --- /dev/null +++ b/include/dt-bindings/clock/omap5.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2017 Texas Instruments, Inc. + */ +#ifndef __DT_BINDINGS_CLK_OMAP5_H +#define __DT_BINDINGS_CLK_OMAP5_H + +#define OMAP5_CLKCTRL_OFFSET 0x20 +#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) + +/* mpu clocks */ +#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* dsp clocks */ +#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* abe clocks */ +#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) +#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) +#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) +#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) +#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) + +/* l3main1 clocks */ +#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* l3main2 clocks */ +#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* ipu clocks */ +#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* dma clocks */ +#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* emif clocks */ +#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) + +/* l4cfg clocks */ +#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) + +/* l3instr clocks */ +#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) + +/* l4per clocks */ +#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) +#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) +#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) +#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) +#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) +#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) +#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) +#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) +#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) +#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) +#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) +#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) +#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) +#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) +#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) +#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) +#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) +#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) +#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) +#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) +#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) +#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) +#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) +#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) +#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) +#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) +#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) + +/* l4_secure clocks */ +#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) +#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) +#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) +#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) +#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) +#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) +#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) +#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) + +/* iva clocks */ +#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) + +/* dss clocks */ +#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* gpu clocks */ +#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + +/* l3init clocks */ +#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) +#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) +#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) +#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) +#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) +#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) +#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) + +/* wkupaon clocks */ +#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) +#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) +#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) +#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) +#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) + +#endif diff --git a/include/dt-bindings/mfd/k210-sysctl.h b/include/dt-bindings/mfd/k210-sysctl.h new file mode 100644 index 0000000000..bfc918d3ba --- /dev/null +++ b/include/dt-bindings/mfd/k210-sysctl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + */ + +#ifndef K210_SYSCTL_H +#define K210_SYSCTL_H + +/* Taken from kendryte-standalone-sdk/lib/drivers/include/sysctl.h */ +#define K210_SYSCTL_GIT_ID 0x00 /* Git short commit id */ +#define K210_SYSCTL_UART_BAUD 0x04 /* Default UARTHS baud rate */ +#define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */ +#define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */ +#define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */ +#define K210_SYSCTL_PLL_LOCK 0x18 /* PLL lock tester */ +#define K210_SYSCTL_ROM_ERROR 0x1C /* AXI ROM detector */ +#define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */ +#define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */ +#define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */ +#define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */ +#define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */ +#define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */ +#define K210_SYSCTL_THR0 0x38 /* Clock threshold controller 0 */ +#define K210_SYSCTL_THR1 0x3C /* Clock threshold controller 1 */ +#define K210_SYSCTL_THR2 0x40 /* Clock threshold controller 2 */ +#define K210_SYSCTL_THR3 0x44 /* Clock threshold controller 3 */ +#define K210_SYSCTL_THR4 0x48 /* Clock threshold controller 4 */ +#define K210_SYSCTL_THR5 0x4C /* Clock threshold controller 5 */ +#define K210_SYSCTL_THR6 0x50 /* Clock threshold controller 6 */ +#define K210_SYSCTL_MISC 0x54 /* Miscellaneous controller */ +#define K210_SYSCTL_PERI 0x58 /* Peripheral controller */ +#define K210_SYSCTL_SPI_SLEEP 0x5C /* SPI sleep controller */ +#define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */ +#define K210_SYSCTL_DMA_SEL0 0x64 /* DMA handshake selector 0 */ +#define K210_SYSCTL_DMA_SEL1 0x68 /* DMA handshake selector 1 */ +#define K210_SYSCTL_POWER_SEL 0x6C /* IO Power Mode Select controller */ + +#endif /* K210_SYSCTL_H */ diff --git a/include/dt-bindings/reset/k210-sysctl.h b/include/dt-bindings/reset/k210-sysctl.h new file mode 100644 index 0000000000..12bb3880d9 --- /dev/null +++ b/include/dt-bindings/reset/k210-sysctl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> + */ + +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */ diff --git a/include/efi_loader.h b/include/efi_loader.h index c2cae814b6..fc9344c742 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -56,6 +56,9 @@ static inline void *guidcpy(void *dst, const void *src) /* Root node */ extern efi_handle_t efi_root; +/* Set to EFI_SUCCESS when initialized */ +extern efi_status_t efi_obj_list_initialized; + /* EFI system partition */ extern struct efi_system_partition { enum if_type if_type; diff --git a/include/env_default.h b/include/env_default.h index a657927e06..8a0c3057f0 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -83,9 +83,6 @@ const uchar default_environment[] = { #ifdef CONFIG_LOADADDR "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" #endif -#ifdef CONFIG_CLOCKS_IN_MHZ - "clocks_in_mhz=1\0" -#endif #if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" #endif diff --git a/include/fs.h b/include/fs.h index 29f737b8c2..b08b1f40c5 100644 --- a/include/fs.h +++ b/include/fs.h @@ -259,4 +259,15 @@ int do_fs_uuid(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], */ int do_fs_type(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +/** + * do_fs_types - List supported filesystems. + * + * @cmdtp: Command information for fstypes + * @flag: Command flags (CMD_FLAG_...) + * @argc: Number of arguments + * @argv: List of arguments + * @return result (see enum command_ret_t) + */ +int do_fs_types(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); + #endif /* _FS_H */ diff --git a/include/hash.h b/include/hash.h index 835962e7f6..97bb3ed5d9 100644 --- a/include/hash.h +++ b/include/hash.h @@ -12,7 +12,11 @@ struct cmd_tbl; * Maximum digest size for all algorithms we support. Having this value * avoids a malloc() or C99 local declaration in common/cmd_hash.c. */ +#if defined(CONFIG_SHA384) || defined(CONFIG_SHA512) +#define HASH_MAX_DIGEST_SIZE 64 +#else #define HASH_MAX_DIGEST_SIZE 32 +#endif enum { HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */ diff --git a/include/image.h b/include/image.h index ad81dad444..9ababf2a2d 100644 --- a/include/image.h +++ b/include/image.h @@ -32,8 +32,12 @@ struct fdt_region; #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT 1 #define CONFIG_FIT_ENABLE_SHA256_SUPPORT +#define CONFIG_FIT_ENABLE_SHA384_SUPPORT +#define CONFIG_FIT_ENABLE_SHA512_SUPPORT #define CONFIG_SHA1 #define CONFIG_SHA256 +#define CONFIG_SHA384 +#define CONFIG_SHA512 #define IMAGE_ENABLE_IGNORE 0 #define IMAGE_INDENT_STRING "" @@ -92,6 +96,20 @@ struct fdt_region; #define IMAGE_ENABLE_SHA256 0 #endif +#if defined(CONFIG_FIT_ENABLE_SHA384_SUPPORT) || \ + defined(CONFIG_SPL_SHA384_SUPPORT) +#define IMAGE_ENABLE_SHA384 1 +#else +#define IMAGE_ENABLE_SHA384 0 +#endif + +#if defined(CONFIG_FIT_ENABLE_SHA512_SUPPORT) || \ + defined(CONFIG_SPL_SHA512_SUPPORT) +#define IMAGE_ENABLE_SHA512 1 +#else +#define IMAGE_ENABLE_SHA512 0 +#endif + #endif /* IMAGE_ENABLE_FIT */ #ifdef CONFIG_SYS_BOOT_GET_CMDLINE @@ -308,6 +326,7 @@ enum { IH_COMP_LZMA, /* lzma Compression Used */ IH_COMP_LZO, /* lzo Compression Used */ IH_COMP_LZ4, /* lz4 Compression Used */ + IH_COMP_ZSTD, /* zstd Compression Used */ IH_COMP_COUNT, }; diff --git a/include/init.h b/include/init.h index b5a167b6ed..e727031514 100644 --- a/include/init.h +++ b/include/init.h @@ -261,6 +261,15 @@ void relocate_code(ulong start_addr_sp, struct global_data *new_gd, __attribute__ ((noreturn)); #endif +/* Print a numeric value (for use in arch_print_bdinfo()) */ +void bdinfo_print_num(const char *name, ulong value); + +/* Print a clock speed in MHz */ +void bdinfo_print_mhz(const char *name, unsigned long hz); + +/* Show arch-specific information for the 'bd' command */ +void arch_print_bdinfo(void); + #endif /* __ASSEMBLY__ */ /* Put only stuff here that the assembler can digest */ diff --git a/include/kendryte/bypass.h b/include/kendryte/bypass.h new file mode 100644 index 0000000000..a081cbd12f --- /dev/null +++ b/include/kendryte/bypass.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + */ +#ifndef K210_BYPASS_H +#define K210_BYPASS_H + +#include <clk.h> + +struct k210_bypass { + struct clk clk; + struct clk **children; /* Clocks to reparent */ + struct clk **saved_parents; /* Parents saved over en-/dis-able */ + struct clk *bypassee; /* Clock to bypass */ + const struct clk_ops *bypassee_ops; /* Ops of the bypass clock */ + struct clk *alt; /* Clock to set children to when bypassing */ + size_t child_count; +}; + +#define to_k210_bypass(_clk) container_of(_clk, struct k210_bypass, clk) + +int k210_bypass_set_children(struct clk *clk, struct clk **children, + size_t child_count); +struct clk *k210_register_bypass_struct(const char *name, + const char *parent_name, + struct k210_bypass *bypass); +struct clk *k210_register_bypass(const char *name, const char *parent_name, + struct clk *bypassee, + const struct clk_ops *bypassee_ops, + struct clk *alt); +#endif /* K210_BYPASS_H */ diff --git a/include/kendryte/clk.h b/include/kendryte/clk.h new file mode 100644 index 0000000000..9c6245d468 --- /dev/null +++ b/include/kendryte/clk.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> + */ + +#ifndef K210_CLK_H +#define K210_CLK_H + +#define LOG_CATEGORY UCLASS_CLK +#include <linux/types.h> +#include <linux/clk-provider.h> + +static inline struct clk *k210_clk_gate(const char *name, + const char *parent_name, + void __iomem *reg, u8 bit_idx) +{ + return clk_register_gate(NULL, name, parent_name, 0, reg, bit_idx, 0, + NULL); +} + +static inline struct clk *k210_clk_half(const char *name, + const char *parent_name) +{ + return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 2); +} + +static inline struct clk *k210_clk_div(const char *name, + const char *parent_name, + void __iomem *reg, u8 shift, u8 width) +{ + return clk_register_divider(NULL, name, parent_name, 0, reg, shift, + width, 0); +} + +#endif /* K210_CLK_H */ diff --git a/include/kendryte/pll.h b/include/kendryte/pll.h new file mode 100644 index 0000000000..c8e3200799 --- /dev/null +++ b/include/kendryte/pll.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> + */ +#ifndef K210_PLL_H +#define K210_PLL_H + +#include <clk.h> +#include <test/export.h> + +#define K210_PLL_CLKR GENMASK(3, 0) +#define K210_PLL_CLKF GENMASK(9, 4) +#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */ +#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */ +#define K210_PLL_RESET BIT(20) +#define K210_PLL_PWRD BIT(21) /* PoWeReD */ +#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */ +#define K210_PLL_BYPASS BIT(23) +#define K210_PLL_TEST BIT(24) +#define K210_PLL_EN BIT(25) +#define K210_PLL_TEST_EN BIT(26) + +#define K210_PLL_LOCK 0 +#define K210_PLL_CLEAR_SLIP 2 +#define K210_PLL_TEST_OUT 3 + +struct k210_pll { + struct clk clk; + void __iomem *reg; /* Base PLL register */ + void __iomem *lock; /* Common PLL lock register */ + u8 shift; /* Offset of bits in lock register */ + u8 width; /* Width of lock bits to test against */ +}; + +#define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk) + +struct k210_pll_config { + u8 r; + u8 f; + u8 od; +}; + +#ifdef CONFIG_UNIT_TEST +TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, + struct k210_pll_config *best); +#define nop() +#endif + +extern const struct clk_ops k210_pll_ops; + +struct clk *k210_register_pll_struct(const char *name, const char *parent_name, + struct k210_pll *pll); +struct clk *k210_register_pll(const char *name, const char *parent_name, + void __iomem *reg, void __iomem *lock, u8 shift, + u8 width); + +#endif /* K210_PLL_H */ diff --git a/include/linux/compiler-clang.h b/include/linux/compiler-clang.h index d1e49d52b6..333a6695a9 100644 --- a/include/linux/compiler-clang.h +++ b/include/linux/compiler-clang.h @@ -1,12 +1,44 @@ -#ifndef __LINUX_COMPILER_H +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_TYPES_H #error "Please don't include <linux/compiler-clang.h> directly, include <linux/compiler.h> instead." #endif -/* Some compiler specific definitions are overwritten here - * for Clang compiler - */ +/* Compiler specific definitions for Clang compiler */ -#ifdef uninitialized_var -#undef uninitialized_var #define uninitialized_var(x) x = *(&(x)) + +/* same as gcc, this was present in clang-2.6 so we can assume it works + * with any version that can compile the kernel + */ +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +/* all clang versions usable with the kernel support KASAN ABI version 5 */ +#define KASAN_ABI_VERSION 5 + +#if __has_feature(address_sanitizer) || __has_feature(hwaddress_sanitizer) +/* emulate gcc's __SANITIZE_ADDRESS__ flag */ +#define __SANITIZE_ADDRESS__ +#define __no_sanitize_address \ + __attribute__((no_sanitize("address", "hwaddress"))) +#else +#define __no_sanitize_address #endif + +/* + * Not all versions of clang implement the the type-generic versions + * of the builtin overflow checkers. Fortunately, clang implements + * __has_builtin allowing us to avoid awkward version + * checks. Unfortunately, we don't know which version of gcc clang + * pretends to be, so the macro may or may not be defined. + */ +#if __has_builtin(__builtin_mul_overflow) && \ + __has_builtin(__builtin_add_overflow) && \ + __has_builtin(__builtin_sub_overflow) +#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1 +#endif + +/* The following are for compatibility with GCC, from compiler-gcc.h, + * and may be redefined here because they should not be shared with other + * compilers, like ICC. + */ +#define barrier() __asm__ __volatile__("" : : : "memory") diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h index 8d9e079435..d7ee4c6bad 100644 --- a/include/linux/compiler-gcc.h +++ b/include/linux/compiler-gcc.h @@ -1,4 +1,5 @@ -#ifndef __LINUX_COMPILER_H +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_TYPES_H #error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead." #endif @@ -9,11 +10,14 @@ + __GNUC_MINOR__ * 100 \ + __GNUC_PATCHLEVEL__) +#if GCC_VERSION < 40600 +# error Sorry, your compiler is too old - please upgrade it. +#endif + /* Optimization barrier */ /* The "volatile" is due to gcc bugs */ -#define barrier() \ - __asm__ __volatile__("": : :"memory") +#define barrier() __asm__ __volatile__("": : :"memory") /* * This version is i.e. to prevent dead stores elimination on @ptr * where gcc and llvm may behave differently when otherwise using @@ -22,13 +26,12 @@ * clobbered. The issue is as follows: while the inline asm might * access any memory it wants, the compiler could have fit all of * @ptr into memory registers instead, and since @ptr never escaped - * from that, it proofed that the inline asm wasn't touching any of + * from that, it proved that the inline asm wasn't touching any of * it. This version works well with both compilers, i.e. we're telling * the compiler that the inline asm absolutely may see the contents * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495 */ -#define barrier_data(ptr) \ - __asm__ __volatile__("": :"r"(ptr) :"memory") +#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory") /* * This macro obfuscates arithmetic on a variable address so that gcc @@ -55,181 +58,54 @@ (typeof(ptr)) (__ptr + (off)); \ }) -/* Make the optimizer believe the variable can be manipulated arbitrarily. */ -#define OPTIMIZER_HIDE_VAR(var) \ - __asm__ ("" : "=r" (var) : "0" (var)) - -#ifdef __CHECKER__ -#define __must_be_array(a) 0 -#else -/* &a[0] degrades to a pointer: a different type from an array */ -#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) -#endif - -/* - * Force always-inline if the user requests it so via the .config, - * or if gcc is too old: - */ -#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ - !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4) -#define inline inline __attribute__((always_inline)) notrace -#define __inline__ __inline__ __attribute__((always_inline)) notrace -#define __inline __inline __attribute__((always_inline)) notrace -#else -/* A lot of inline functions can cause havoc with function tracing */ -#define inline inline notrace -#define __inline__ __inline__ notrace -#define __inline __inline notrace -#endif - -#define __always_inline inline __attribute__((always_inline)) -#define noinline __attribute__((noinline)) - -#define __deprecated __attribute__((deprecated)) -#define __packed __attribute__((packed)) -#define __weak __attribute__((weak)) -#define __alias(symbol) __attribute__((alias(#symbol))) - /* - * it doesn't make sense on ARM (currently the only user of __naked) - * to trace naked functions because then mcount is called without - * stack and frame pointer being set up and there is no chance to - * restore the lr register to the value before mcount was called. - * - * The asm() bodies of naked functions often depend on standard calling - * conventions, therefore they must be noinline and noclone. - * - * GCC 4.[56] currently fail to enforce this, so we must do so ourselves. - * See GCC PR44290. - */ -#define __naked __attribute__((naked)) noinline __noclone notrace - -#define __noreturn __attribute__((noreturn)) - -/* - * From the GCC manual: - * - * Many functions have no effects except the return value and their - * return value depends only on the parameters and/or global - * variables. Such a function can be subject to common subexpression - * elimination and loop optimization just as an arithmetic operator - * would be. - * [...] + * A trick to suppress uninitialized variable warning without generating any + * code */ -#define __pure __attribute__((pure)) -#define __aligned(x) __attribute__((aligned(x))) -#define __printf(a, b) __attribute__((format(printf, a, b))) -#define __scanf(a, b) __attribute__((format(scanf, a, b))) -#define __attribute_const__ __attribute__((__const__)) -#define __maybe_unused __attribute__((unused)) -#define __always_unused __attribute__((unused)) - -/* gcc version specific checks */ - -#if GCC_VERSION < 30200 -# error Sorry, your compiler is too old - please upgrade it. -#endif - -#if GCC_VERSION < 30300 -# define __used __attribute__((__unused__)) -#else -# define __used __attribute__((__used__)) -#endif - -#ifdef CONFIG_GCOV_KERNEL -# if GCC_VERSION < 30400 -# error "GCOV profiling support for gcc versions below 3.4 not included" -# endif /* __GNUC_MINOR__ */ -#endif /* CONFIG_GCOV_KERNEL */ +#define uninitialized_var(x) x = x -#if GCC_VERSION >= 30400 -#define __must_check __attribute__((warn_unused_result)) +#ifdef CONFIG_RETPOLINE +#define __noretpoline __attribute__((__indirect_branch__("keep"))) #endif -#if GCC_VERSION >= 40000 +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) -/* GCC 4.1.[01] miscompiles __weak */ -#ifdef __KERNEL__ -# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101 -# error Your version of gcc miscompiles the __weak directive -# endif -#endif +#define __compiletime_object_size(obj) __builtin_object_size(obj, 0) -#define __used __attribute__((__used__)) -#define __compiler_offsetof(a, b) \ - __builtin_offsetof(a, b) +#define __compiletime_warning(message) __attribute__((__warning__(message))) +#define __compiletime_error(message) __attribute__((__error__(message))) -#if GCC_VERSION >= 40100 && GCC_VERSION < 40600 -# define __compiletime_object_size(obj) __builtin_object_size(obj, 0) +#if defined(LATENT_ENTROPY_PLUGIN) && !defined(__CHECKER__) +#define __latent_entropy __attribute__((latent_entropy)) #endif -#if GCC_VERSION >= 40300 -/* Mark functions as cold. gcc will assume any path leading to a call - * to them will be unlikely. This means a lot of manual unlikely()s - * are unnecessary now for any paths leading to the usual suspects - * like BUG(), printk(), panic() etc. [but let's keep them for now for - * older compilers] - * - * Early snapshots of gcc 4.3 don't support this and we can't detect this - * in the preprocessor, but we can live with this because they're unreleased. - * Maketime probing would be overkill here. +/* + * calling noreturn functions, __builtin_unreachable() and __builtin_trap() + * confuse the stack allocation in gcc, leading to overly large stack + * frames, see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365 * - * gcc also has a __attribute__((__hot__)) to move hot functions into - * a special section, but I don't see any sense in this right now in - * the kernel context + * Adding an empty inline assembly before it works around the problem */ -#define __cold __attribute__((__cold__)) - -#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) +#define barrier_before_unreachable() asm volatile("") -#ifndef __CHECKER__ -# define __compiletime_warning(message) __attribute__((warning(message))) -# define __compiletime_error(message) __attribute__((error(message))) -#endif /* __CHECKER__ */ -#endif /* GCC_VERSION >= 40300 */ - -#if GCC_VERSION >= 40500 /* * Mark a position in code as unreachable. This can be used to * suppress control flow warnings after asm blocks that transfer * control elsewhere. - * - * Early snapshots of gcc 4.5 don't support this and we can't detect - * this in the preprocessor, but we can live with this because they're - * unreleased. Really, we need to have autoconf for the kernel. - */ -#define unreachable() __builtin_unreachable() - -/* Mark a function definition as prohibited from being cloned. */ -#define __noclone __attribute__((__noclone__)) - -#endif /* GCC_VERSION >= 40500 */ - -#if GCC_VERSION >= 40600 -/* - * When used with Link Time Optimization, gcc can optimize away C functions or - * variables which are referenced only from assembly code. __visible tells the - * optimizer that something else uses this function or variable, thus preventing - * this. */ -#define __visible __attribute__((externally_visible)) -#endif - +#define unreachable() \ + do { \ + annotate_unreachable(); \ + barrier_before_unreachable(); \ + __builtin_unreachable(); \ + } while (0) -#if GCC_VERSION >= 40900 && !defined(__CHECKER__) -/* - * __assume_aligned(n, k): Tell the optimizer that the returned - * pointer can be assumed to be k modulo n. The second argument is - * optional (default 0), so we use a variadic macro to make the - * shorthand. - * - * Beware: Do not apply this to functions which may return - * ERR_PTRs. Also, it is probably unwise to apply it to functions - * returning extra information in the low bits (but in that case the - * compiler should see some alignment anyway, when the return value is - * massaged by 'flags = ptr & 3; ptr &= ~3;'). - */ -#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__))) +#if defined(RANDSTRUCT_PLUGIN) && !defined(__CHECKER__) +#define __randomize_layout __attribute__((randomize_layout)) +#define __no_randomize_layout __attribute__((no_randomize_layout)) +/* This anon struct can add padding, so only enable it under randstruct. */ +#define randomized_struct_fields_start struct { +#define randomized_struct_fields_end } __randomize_layout; #endif /* @@ -243,43 +119,56 @@ */ #define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) -#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP -#if GCC_VERSION >= 40400 +/* + * sparse (__CHECKER__) pretends to be gcc, but can't do constant + * folding in __builtin_bswap*() (yet), so don't set these for it. + */ +#if defined(CONFIG_ARCH_USE_BUILTIN_BSWAP) && !defined(__CHECKER__) #define __HAVE_BUILTIN_BSWAP32__ #define __HAVE_BUILTIN_BSWAP64__ -#endif -#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600) +#if GCC_VERSION >= 40800 #define __HAVE_BUILTIN_BSWAP16__ #endif -#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ +#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP && !__CHECKER__ */ -#if GCC_VERSION >= 50000 +#if GCC_VERSION >= 70000 +#define KASAN_ABI_VERSION 5 +#elif GCC_VERSION >= 50000 #define KASAN_ABI_VERSION 4 #elif GCC_VERSION >= 40902 #define KASAN_ABI_VERSION 3 #endif -#if GCC_VERSION >= 40902 -/* - * Tell the compiler that address safety instrumentation (KASAN) - * should not be applied to that function. - * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 - */ +#if __has_attribute(__no_sanitize_address__) #define __no_sanitize_address __attribute__((no_sanitize_address)) +#else +#define __no_sanitize_address #endif -#endif /* gcc version >= 40000 specific checks */ - -#if !defined(__noclone) -#define __noclone /* not needed */ -#endif - -#if !defined(__no_sanitize_address) -#define __no_sanitize_address +#if GCC_VERSION >= 50100 +#define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1 #endif /* - * A trick to suppress uninitialized variable warning without generating any - * code + * Turn individual warnings and errors on and off locally, depending + * on version. */ -#define uninitialized_var(x) x = x +#define __diag_GCC(version, severity, s) \ + __diag_GCC_ ## version(__diag_GCC_ ## severity s) + +/* Severity used in pragma directives */ +#define __diag_GCC_ignore ignored +#define __diag_GCC_warn warning +#define __diag_GCC_error error + +#define __diag_str1(s) #s +#define __diag_str(s) __diag_str1(s) +#define __diag(s) _Pragma(__diag_str(GCC diagnostic s)) + +#if GCC_VERSION >= 80000 +#define __diag_GCC_8(s) __diag(s) +#else +#define __diag_GCC_8(s) +#endif + +#define __no_fgcse __attribute__((optimize("-fno-gcse"))) diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h index d4c71132d0..b17f3cd183 100644 --- a/include/linux/compiler-intel.h +++ b/include/linux/compiler-intel.h @@ -1,22 +1,17 @@ -#ifndef __LINUX_COMPILER_H +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_TYPES_H #error "Please don't include <linux/compiler-intel.h> directly, include <linux/compiler.h> instead." #endif #ifdef __ECC -/* Some compiler specific definitions are overwritten here - * for Intel ECC compiler - */ +/* Compiler specific definitions for Intel ECC compiler */ #include <asm/intrinsics.h> /* Intel ECC compiler doesn't support gcc specific asm stmts. * It uses intrinsics to do the equivalent things. */ -#undef barrier -#undef barrier_data -#undef RELOC_HIDE -#undef OPTIMIZER_HIDE_VAR #define barrier() __memory_barrier() #define barrier_data(ptr) barrier() @@ -32,14 +27,8 @@ */ #define OPTIMIZER_HIDE_VAR(var) barrier() -/* Intel ECC compiler doesn't support __builtin_types_compatible_p() */ -#define __must_be_array(a) 0 - #endif -#ifndef __HAVE_BUILTIN_BSWAP16__ /* icc has this, but it's called _bswap16 */ #define __HAVE_BUILTIN_BSWAP16__ #define __builtin_bswap16 _bswap16 -#endif - diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 0ea6c8fcca..5e3b3c08e9 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -1,127 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __LINUX_COMPILER_H #define __LINUX_COMPILER_H -#ifndef __ASSEMBLY__ +#include <linux/compiler_types.h> -#ifdef __CHECKER__ -# define __user __attribute__((noderef, address_space(1))) -# define __kernel __attribute__((address_space(0))) -# define __safe __attribute__((safe)) -# define __force __attribute__((force)) -# define __nocast __attribute__((nocast)) -# define __iomem __attribute__((noderef, address_space(2))) -# define __must_hold(x) __attribute__((context(x,1,1))) -# define __acquires(x) __attribute__((context(x,0,1))) -# define __releases(x) __attribute__((context(x,1,0))) -# define __acquire(x) __context__(x,1) -# define __release(x) __context__(x,-1) -# define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0) -# define __percpu __attribute__((noderef, address_space(3))) -# define __pmem __attribute__((noderef, address_space(5))) -#ifdef CONFIG_SPARSE_RCU_POINTER -# define __rcu __attribute__((noderef, address_space(4))) -#else -# define __rcu -#endif -extern void __chk_user_ptr(const volatile void __user *); -extern void __chk_io_ptr(const volatile void __iomem *); -#else -# define __user -# define __kernel -# define __safe -# define __force -# define __nocast -# define __iomem -# define __chk_user_ptr(x) (void)0 -# define __chk_io_ptr(x) (void)0 -# define __builtin_warning(x, y...) (1) -# define __must_hold(x) -# define __acquires(x) -# define __releases(x) -# define __acquire(x) (void)0 -# define __release(x) (void)0 -# define __cond_lock(x,c) (c) -# define __percpu -# define __rcu -# define __pmem -#endif - -/* Indirect macros required for expanded argument pasting, eg. __LINE__. */ -#define ___PASTE(a,b) a##b -#define __PASTE(a,b) ___PASTE(a,b) +#ifndef __ASSEMBLY__ #ifdef __KERNEL__ -#ifdef __GNUC__ -#include <linux/compiler-gcc.h> -#endif - -#if defined(CC_USING_HOTPATCH) && !defined(__CHECKER__) -#define notrace __attribute__((hotpatch(0,0))) -#else -#define notrace __attribute__((no_instrument_function)) -#endif - -/* Intel compiler defines __GNUC__. So we will overwrite implementations - * coming from above header files here - */ -#ifdef __INTEL_COMPILER -# include <linux/compiler-intel.h> -#endif - -/* Clang compiler defines __GNUC__. So we will overwrite implementations - * coming from above header files here - */ -#ifdef __clang__ -#include <linux/compiler-clang.h> -#endif - -/* - * Generic compiler-dependent macros required for kernel - * build go below this comment. Actual compiler/compiler version - * specific implementations come from the above header files - */ - -struct ftrace_branch_data { - const char *func; - const char *file; - unsigned line; - union { - struct { - unsigned long correct; - unsigned long incorrect; - }; - struct { - unsigned long miss; - unsigned long hit; - }; - unsigned long miss_hit[2]; - }; -}; - /* * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code * to disable branch tracing on a per file basis. */ #if defined(CONFIG_TRACE_BRANCH_PROFILING) \ && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__) -void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); +void ftrace_likely_update(struct ftrace_likely_data *f, int val, + int expect, int is_constant); #define likely_notrace(x) __builtin_expect(!!(x), 1) #define unlikely_notrace(x) __builtin_expect(!!(x), 0) -#define __branch_check__(x, expect) ({ \ - int ______r; \ - static struct ftrace_branch_data \ - __attribute__((__aligned__(4))) \ - __attribute__((section("_ftrace_annotated_branch"))) \ +#define __branch_check__(x, expect, is_constant) ({ \ + long ______r; \ + static struct ftrace_likely_data \ + __aligned(4) \ + __section(_ftrace_annotated_branch) \ ______f = { \ - .func = __func__, \ - .file = __FILE__, \ - .line = __LINE__, \ + .data.func = __func__, \ + .data.file = __FILE__, \ + .data.line = __LINE__, \ }; \ - ______r = likely_notrace(x); \ - ftrace_likely_update(&______f, ______r, expect); \ + ______r = __builtin_expect(!!(x), expect); \ + ftrace_likely_update(&______f, ______r, \ + expect, is_constant); \ ______r; \ }) @@ -131,10 +42,10 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); * written by Daniel Walker. */ # ifndef likely -# define likely(x) (__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 1)) +# define likely(x) (__branch_check__(x, 1, __builtin_constant_p(x))) # endif # ifndef unlikely -# define unlikely(x) (__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 0)) +# define unlikely(x) (__branch_check__(x, 0, __builtin_constant_p(x))) # endif #ifdef CONFIG_PROFILE_ALL_BRANCHES @@ -142,23 +53,24 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); * "Define 'is'", Bill Clinton * "Define 'if'", Steven Rostedt */ -#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) ) -#define __trace_if(cond) \ - if (__builtin_constant_p(!!(cond)) ? !!(cond) : \ - ({ \ - int ______r; \ - static struct ftrace_branch_data \ - __attribute__((__aligned__(4))) \ - __attribute__((section("_ftrace_branch"))) \ - ______f = { \ - .func = __func__, \ - .file = __FILE__, \ - .line = __LINE__, \ - }; \ - ______r = !!(cond); \ - ______f.miss_hit[______r]++; \ - ______r; \ - })) +#define if(cond, ...) if ( __trace_if_var( !!(cond , ## __VA_ARGS__) ) ) + +#define __trace_if_var(cond) (__builtin_constant_p(cond) ? (cond) : __trace_if_value(cond)) + +#define __trace_if_value(cond) ({ \ + static struct ftrace_branch_data \ + __aligned(4) \ + __section(_ftrace_branch) \ + __if_trace = { \ + .func = __func__, \ + .file = __FILE__, \ + .line = __LINE__, \ + }; \ + (cond) ? \ + (__if_trace.miss_hit[1]++,1) : \ + (__if_trace.miss_hit[0]++,0); \ +}) + #endif /* CONFIG_PROFILE_ALL_BRANCHES */ #else @@ -175,9 +87,76 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); # define barrier_data(ptr) barrier() #endif +/* workaround for GCC PR82365 if needed */ +#ifndef barrier_before_unreachable +# define barrier_before_unreachable() do { } while (0) +#endif + /* Unreachable code */ +#ifdef CONFIG_STACK_VALIDATION +/* + * These macros help objtool understand GCC code flow for unreachable code. + * The __COUNTER__ based labels are a hack to make each instance of the macros + * unique, to convince GCC not to merge duplicate inline asm statements. + */ +#define annotate_reachable() ({ \ + asm volatile("%c0:\n\t" \ + ".pushsection .discard.reachable\n\t" \ + ".long %c0b - .\n\t" \ + ".popsection\n\t" : : "i" (__COUNTER__)); \ +}) +#define annotate_unreachable() ({ \ + asm volatile("%c0:\n\t" \ + ".pushsection .discard.unreachable\n\t" \ + ".long %c0b - .\n\t" \ + ".popsection\n\t" : : "i" (__COUNTER__)); \ +}) +#define ASM_UNREACHABLE \ + "999:\n\t" \ + ".pushsection .discard.unreachable\n\t" \ + ".long 999b - .\n\t" \ + ".popsection\n\t" + +/* Annotate a C jump table to allow objtool to follow the code flow */ +#define __annotate_jump_table __section(.rodata..c_jump_table) + +#else +#define annotate_reachable() +#define annotate_unreachable() +#define __annotate_jump_table +#endif + +#ifndef ASM_UNREACHABLE +# define ASM_UNREACHABLE +#endif #ifndef unreachable -# define unreachable() do { } while (1) +# define unreachable() do { \ + annotate_unreachable(); \ + __builtin_unreachable(); \ +} while (0) +#endif + +/* + * KENTRY - kernel entry point + * This can be used to annotate symbols (functions or data) that are used + * without their linker symbol being referenced explicitly. For example, + * interrupt vector handlers, or functions in the kernel image that are found + * programatically. + * + * Not required for symbols exported with EXPORT_SYMBOL, or initcalls. Those + * are handled in their own way (with KEEP() in linker scripts). + * + * KENTRY can be avoided if the symbols in question are marked as KEEP() in the + * linker script. For example an architecture could KEEP() its entire + * boot/exception vector code rather than annotate each function and data. + */ +#ifndef KENTRY +# define KENTRY(sym) \ + extern typeof(sym) sym; \ + static const unsigned long __kentry_##sym \ + __used \ + __section("___kentry" "+" #sym ) \ + = (unsigned long)&sym; #endif #ifndef RELOC_HIDE @@ -188,7 +167,9 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); #endif #ifndef OPTIMIZER_HIDE_VAR -#define OPTIMIZER_HIDE_VAR(var) barrier() +/* Make the optimizer believe the variable can be manipulated arbitrarily. */ +#define OPTIMIZER_HIDE_VAR(var) \ + __asm__ ("" : "=r" (var) : "0" (var)) #endif /* Not-quite-unique ID. */ @@ -220,23 +201,21 @@ void __read_once_size(const volatile void *p, void *res, int size) #ifdef CONFIG_KASAN /* - * This function is not 'inline' because __no_sanitize_address confilcts + * We can't declare function 'inline' because __no_sanitize_address confilcts * with inlining. Attempt to inline it may cause a build failure. * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368 * '__maybe_unused' allows us to avoid defined-but-not-used warnings. */ -static __no_sanitize_address __maybe_unused -void __read_once_size_nocheck(const volatile void *p, void *res, int size) -{ - __READ_ONCE_SIZE; -} +# define __no_kasan_or_inline __no_sanitize_address notrace __maybe_unused #else -static __always_inline +# define __no_kasan_or_inline __always_inline +#endif + +static __no_kasan_or_inline void __read_once_size_nocheck(const volatile void *p, void *res, int size) { __READ_ONCE_SIZE; } -#endif static __always_inline void __write_once_size(volatile void *p, void *res, int size) { @@ -255,20 +234,21 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s /* * Prevent the compiler from merging or refetching reads or writes. The * compiler is also forbidden from reordering successive instances of - * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the - * compiler is aware of some particular ordering. One way to make the - * compiler aware of ordering is to put the two invocations of READ_ONCE, - * WRITE_ONCE or ACCESS_ONCE() in different C statements. + * READ_ONCE and WRITE_ONCE, but only when the compiler is aware of some + * particular ordering. One way to make the compiler aware of ordering is to + * put the two invocations of READ_ONCE or WRITE_ONCE in different C + * statements. * - * In contrast to ACCESS_ONCE these two macros will also work on aggregate - * data types like structs or unions. If the size of the accessed data - * type exceeds the word size of the machine (e.g., 32 bits or 64 bits) - * READ_ONCE() and WRITE_ONCE() will fall back to memcpy and print a - * compile-time warning. + * These two macros will also work on aggregate data types like structs or + * unions. If the size of the accessed data type exceeds the word size of + * the machine (e.g., 32 bits or 64 bits) READ_ONCE() and WRITE_ONCE() will + * fall back to memcpy(). There's at least two memcpy()s: one for the + * __builtin_memcpy() and then one for the macro doing the copy of variable + * - '__u' allocated on the stack. * * Their two major use cases are: (1) Mediating communication between * process-level code and irq/NMI handlers, all running on the same CPU, - * and (2) Ensuring that the compiler does not fold, spindle, or otherwise + * and (2) Ensuring that the compiler does not fold, spindle, or otherwise * mutilate accesses that either do not require ordering or that interact * with an explicit memory barrier or atomic instruction that provides the * required ordering. @@ -291,6 +271,12 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s */ #define READ_ONCE_NOCHECK(x) __READ_ONCE(x, 0) +static __no_kasan_or_inline +unsigned long read_word_at_a_time(const void *addr) +{ + return *(unsigned long *)addr; +} + #define WRITE_ONCE(x, val) \ ({ \ union { typeof(x) __val; char __c[1]; } __u = \ @@ -299,158 +285,28 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s __u.__val; \ }) -/** - * smp_cond_acquire() - Spin wait for cond with ACQUIRE ordering - * @cond: boolean expression to wait for - * - * Equivalent to using smp_load_acquire() on the condition variable but employs - * the control dependency of the wait to reduce the barrier on many platforms. - * - * The control dependency provides a LOAD->STORE order, the additional RMB - * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order, - * aka. ACQUIRE. - */ -#define smp_cond_acquire(cond) do { \ - while (!(cond)) \ - cpu_relax(); \ - smp_rmb(); /* ctrl + rmb := acquire */ \ -} while (0) - -#endif /* __KERNEL__ */ - -#endif /* __ASSEMBLY__ */ - -#ifdef __KERNEL__ -/* - * Allow us to mark functions as 'deprecated' and have gcc emit a nice - * warning for each use, in hopes of speeding the functions removal. - * Usage is: - * int __deprecated foo(void) - */ -#ifndef __deprecated -# define __deprecated /* unimplemented */ -#endif - -#ifdef MODULE -#define __deprecated_for_modules __deprecated -#else -#define __deprecated_for_modules -#endif - -#ifndef __must_check -#define __must_check -#endif - -#ifndef CONFIG_ENABLE_MUST_CHECK -#undef __must_check -#define __must_check -#endif -#ifndef CONFIG_ENABLE_WARN_DEPRECATED -#undef __deprecated -#undef __deprecated_for_modules -#define __deprecated -#define __deprecated_for_modules -#endif - -/* - * Allow us to avoid 'defined but not used' warnings on functions and data, - * as well as force them to be emitted to the assembly file. - * - * As of gcc 3.4, static functions that are not marked with attribute((used)) - * may be elided from the assembly file. As of gcc 3.4, static data not so - * marked will not be elided, but this may change in a future gcc version. - * - * NOTE: Because distributions shipped with a backported unit-at-a-time - * compiler in gcc 3.3, we must define __used to be __attribute__((used)) - * for gcc >=3.3 instead of 3.4. - * - * In prior versions of gcc, such functions and data would be emitted, but - * would be warned about except with attribute((unused)). - * - * Mark functions that are referenced only in inline assembly as __used so - * the code is emitted even though it appears to be unreferenced. - */ -#ifndef __used -# define __used /* unimplemented */ -#endif - -#ifndef __maybe_unused -# define __maybe_unused /* unimplemented */ -#endif - -#ifndef __always_unused -# define __always_unused /* unimplemented */ -#endif - -#ifndef noinline -#define noinline -#endif - -/* - * Rather then using noinline to prevent stack consumption, use - * noinline_for_stack instead. For documentation reasons. - */ -#define noinline_for_stack noinline - -#ifndef __always_inline -#define __always_inline inline -#endif - #endif /* __KERNEL__ */ /* - * From the GCC manual: - * - * Many functions do not examine any values except their arguments, - * and have no effects except the return value. Basically this is - * just slightly more strict class than the `pure' attribute above, - * since function is not allowed to read global memory. - * - * Note that a function that has pointer arguments and examines the - * data pointed to must _not_ be declared `const'. Likewise, a - * function that calls a non-`const' function usually must not be - * `const'. It does not make sense for a `const' function to return - * `void'. - */ -#ifndef __attribute_const__ -# define __attribute_const__ /* unimplemented */ -#endif - -/* - * Tell gcc if a function is cold. The compiler will assume any path - * directly leading to the call is unlikely. + * Force the compiler to emit 'sym' as a symbol, so that we can reference + * it from inline assembler. Necessary in case 'sym' could be inlined + * otherwise, or eliminated entirely due to lack of references that are + * visible to the compiler. */ +#define __ADDRESSABLE(sym) \ + static void * __section(.discard.addressable) __used \ + __PASTE(__addressable_##sym, __LINE__) = (void *)&sym; -#ifndef __cold -#define __cold -#endif - -/* Simple shorthand for a section definition */ -#ifndef __section -# define __section(S) __attribute__ ((__section__(#S))) -#endif - -#ifndef __visible -#define __visible -#endif - -/* - * Assume alignment of return value. +/** + * offset_to_ptr - convert a relative memory offset to an absolute pointer + * @off: the address of the 32-bit offset value */ -#ifndef __assume_aligned -#define __assume_aligned(a, ...) -#endif - - -/* Are two types/vars the same type (ignoring qualifiers)? */ -#ifndef __same_type -# define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) -#endif +static inline void *offset_to_ptr(const int *off) +{ + return (void *)((unsigned long)off + *off); +} -/* Is this type a native word size -- useful for atomic operations */ -#ifndef __native_word -# define __native_word(t) (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long)) -#endif +#endif /* __ASSEMBLY__ */ /* Compile time object size, -1 for unknown */ #ifndef __compiletime_object_size @@ -461,29 +317,14 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s #endif #ifndef __compiletime_error # define __compiletime_error(message) -/* - * Sparse complains of variable sized arrays due to the temporary variable in - * __compiletime_assert. Unfortunately we can't just expand it out to make - * sparse see a constant array size without breaking compiletime_assert on old - * versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether. - */ -# ifndef __CHECKER__ -# define __compiletime_error_fallback(condition) \ - do { ((void)sizeof(char[1 - 2 * condition])); } while (0) -# endif -#endif -#ifndef __compiletime_error_fallback -# define __compiletime_error_fallback(condition) do { } while (0) #endif #ifdef __OPTIMIZE__ # define __compiletime_assert(condition, msg, prefix, suffix) \ do { \ - bool __cond = !(condition); \ extern void prefix ## suffix(void) __compiletime_error(msg); \ - if (__cond) \ + if (!(condition)) \ prefix ## suffix(); \ - __compiletime_error_fallback(__cond); \ } while (0) #else # define __compiletime_assert(condition, msg, prefix, suffix) do { } while (0) @@ -502,58 +343,13 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s * compiler has support to do so. */ #define compiletime_assert(condition, msg) \ - _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__) + _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) #define compiletime_assert_atomic_type(t) \ compiletime_assert(__native_word(t), \ "Need native word sized stores/loads for atomicity.") -/* - * Prevent the compiler from merging or refetching accesses. The compiler - * is also forbidden from reordering successive instances of ACCESS_ONCE(), - * but only when the compiler is aware of some particular ordering. One way - * to make the compiler aware of ordering is to put the two invocations of - * ACCESS_ONCE() in different C statements. - * - * ACCESS_ONCE will only work on scalar types. For union types, ACCESS_ONCE - * on a union member will work as long as the size of the member matches the - * size of the union and the size is smaller than word size. - * - * The major use cases of ACCESS_ONCE used to be (1) Mediating communication - * between process-level code and irq/NMI handlers, all running on the same CPU, - * and (2) Ensuring that the compiler does not fold, spindle, or otherwise - * mutilate accesses that either do not require ordering or that interact - * with an explicit memory barrier or atomic instruction that provides the - * required ordering. - * - * If possible use READ_ONCE()/WRITE_ONCE() instead. - */ -#define __ACCESS_ONCE(x) ({ \ - __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \ - (volatile typeof(x) *)&(x); }) -#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x)) - -/** - * lockless_dereference() - safely load a pointer for later dereference - * @p: The pointer to load - * - * Similar to rcu_dereference(), but for situations where the pointed-to - * object's lifetime is managed by something other than RCU. That - * "something other" might be reference counting or simple immortality. - */ -#define lockless_dereference(p) \ -({ \ - typeof(p) _________p1 = READ_ONCE(p); \ - smp_read_barrier_depends(); /* Dependency order vs. p above. */ \ - (_________p1); \ -}) +/* &a[0] degrades to a pointer: a different type from an array */ +#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) -/* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */ -#ifdef CONFIG_KPROBES -# define __kprobes __attribute__((__section__(".kprobes.text"))) -# define nokprobe_inline __always_inline -#else -# define __kprobes -# define nokprobe_inline inline -#endif #endif /* __LINUX_COMPILER_H */ diff --git a/include/linux/compiler_attributes.h b/include/linux/compiler_attributes.h new file mode 100644 index 0000000000..cdf0165966 --- /dev/null +++ b/include/linux/compiler_attributes.h @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_ATTRIBUTES_H +#define __LINUX_COMPILER_ATTRIBUTES_H + +/* + * The attributes in this file are unconditionally defined and they directly + * map to compiler attribute(s), unless one of the compilers does not support + * the attribute. In that case, __has_attribute is used to check for support + * and the reason is stated in its comment ("Optional: ..."). + * + * Any other "attributes" (i.e. those that depend on a configuration option, + * on a compiler, on an architecture, on plugins, on other attributes...) + * should be defined elsewhere (e.g. compiler_types.h or compiler-*.h). + * The intention is to keep this file as simple as possible, as well as + * compiler- and version-agnostic (e.g. avoiding GCC_VERSION checks). + * + * This file is meant to be sorted (by actual attribute name, + * not by #define identifier). Use the __attribute__((__name__)) syntax + * (i.e. with underscores) to avoid future collisions with other macros. + * Provide links to the documentation of each supported compiler, if it exists. + */ + +/* + * __has_attribute is supported on gcc >= 5, clang >= 2.9 and icc >= 17. + * In the meantime, to support 4.6 <= gcc < 5, we implement __has_attribute + * by hand. + * + * sparse does not support __has_attribute (yet) and defines __GNUC_MINOR__ + * depending on the compiler used to build it; however, these attributes have + * no semantic effects for sparse, so it does not matter. Also note that, + * in order to avoid sparse's warnings, even the unsupported ones must be + * defined to 0. + */ +#ifndef __has_attribute +# define __has_attribute(x) __GCC4_has_attribute_##x +# define __GCC4_has_attribute___assume_aligned__ (__GNUC_MINOR__ >= 9) +# define __GCC4_has_attribute___copy__ 0 +# define __GCC4_has_attribute___designated_init__ 0 +# define __GCC4_has_attribute___externally_visible__ 1 +# define __GCC4_has_attribute___noclone__ 1 +# define __GCC4_has_attribute___nonstring__ 0 +# define __GCC4_has_attribute___no_sanitize_address__ (__GNUC_MINOR__ >= 8) +# define __GCC4_has_attribute___fallthrough__ 0 +#endif + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-alias-function-attribute + */ +#define __alias(symbol) __attribute__((__alias__(#symbol))) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-aligned-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-aligned-type-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-aligned-variable-attribute + */ +#define __aligned(x) __attribute__((__aligned__(x))) +#define __aligned_largest __attribute__((__aligned__)) + +/* + * Note: users of __always_inline currently do not write "inline" themselves, + * which seems to be required by gcc to apply the attribute according + * to its docs (and also "warning: always_inline function might not be + * inlinable [-Wattributes]" is emitted). + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-always_005finline-function-attribute + * clang: mentioned + */ +#define __always_inline inline __attribute__((__always_inline__)) + +/* + * The second argument is optional (default 0), so we use a variadic macro + * to make the shorthand. + * + * Beware: Do not apply this to functions which may return + * ERR_PTRs. Also, it is probably unwise to apply it to functions + * returning extra information in the low bits (but in that case the + * compiler should see some alignment anyway, when the return value is + * massaged by 'flags = ptr & 3; ptr &= ~3;'). + * + * Optional: only supported since gcc >= 4.9 + * Optional: not supported by icc + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-assume_005faligned-function-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#assume-aligned + */ +#if __has_attribute(__assume_aligned__) +# define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__))) +#else +# define __assume_aligned(a, ...) +#endif + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-cold-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Label-Attributes.html#index-cold-label-attribute + */ +#define __cold __attribute__((__cold__)) + +/* + * Note the long name. + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-const-function-attribute + */ +#define __attribute_const__ __attribute__((__const__)) + +/* + * Optional: only supported since gcc >= 9 + * Optional: not supported by clang + * Optional: not supported by icc + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-copy-function-attribute + */ +#if __has_attribute(__copy__) +# define __copy(symbol) __attribute__((__copy__(symbol))) +#else +# define __copy(symbol) +#endif + +/* + * Don't. Just don't. See commit 771c035372a0 ("deprecate the '__deprecated' + * attribute warnings entirely and for good") for more information. + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-deprecated-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-deprecated-type-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-deprecated-variable-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Enumerator-Attributes.html#index-deprecated-enumerator-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#deprecated + */ +#define __deprecated + +/* + * Optional: only supported since gcc >= 5.1 + * Optional: not supported by clang + * Optional: not supported by icc + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-designated_005finit-type-attribute + */ +#if __has_attribute(__designated_init__) +# define __designated_init __attribute__((__designated_init__)) +#else +# define __designated_init +#endif + +/* + * Optional: not supported by clang + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-externally_005fvisible-function-attribute + */ +#if __has_attribute(__externally_visible__) +# define __visible __attribute__((__externally_visible__)) +#else +# define __visible +#endif + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-format-function-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#format + */ +#define __printf(a, b) __attribute__((__format__(printf, a, b))) +#define __scanf(a, b) __attribute__((__format__(scanf, a, b))) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-gnu_005finline-function-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#gnu-inline + */ +#define __gnu_inline __attribute__((__gnu_inline__)) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-malloc-function-attribute + */ +#define __malloc __attribute__((__malloc__)) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-mode-type-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-mode-variable-attribute + */ +#define __mode(x) __attribute__((__mode__(x))) + +/* + * Optional: not supported by clang + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-noclone-function-attribute + */ +#if __has_attribute(__noclone__) +# define __noclone __attribute__((__noclone__)) +#else +# define __noclone +#endif + +/* + * Add the pseudo keyword 'fallthrough' so case statement blocks + * must end with any of these keywords: + * break; + * fallthrough; + * goto <label>; + * return [expression]; + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html#Statement-Attributes + */ +#if __has_attribute(__fallthrough__) +# define fallthrough __attribute__((__fallthrough__)) +#else +# define fallthrough do {} while (0) /* fallthrough */ +#endif + +/* + * Note the missing underscores. + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-noinline-function-attribute + * clang: mentioned + */ +#define noinline __attribute__((__noinline__)) + +/* + * Optional: only supported since gcc >= 8 + * Optional: not supported by clang + * Optional: not supported by icc + * + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-nonstring-variable-attribute + */ +#if __has_attribute(__nonstring__) +# define __nonstring __attribute__((__nonstring__)) +#else +# define __nonstring +#endif + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-noreturn-function-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#noreturn + * clang: https://clang.llvm.org/docs/AttributeReference.html#id1 + */ +#define __noreturn __attribute__((__noreturn__)) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-packed-type-attribute + * clang: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-packed-variable-attribute + */ +#define __packed __attribute__((__packed__)) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-pure-function-attribute + */ +#define __pure __attribute__((__pure__)) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-section-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-section-variable-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#section-declspec-allocate + */ +#define __section(S) __attribute__((__section__(#S))) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-unused-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-unused-type-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-unused-variable-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Label-Attributes.html#index-unused-label-attribute + * clang: https://clang.llvm.org/docs/AttributeReference.html#maybe-unused-unused + */ +#define __always_unused __attribute__((__unused__)) +#define __maybe_unused __attribute__((__unused__)) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-used-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-used-variable-attribute + */ +#define __used __attribute__((__used__)) + +/* + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-weak-function-attribute + * gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-weak-variable-attribute + */ +#define __weak __attribute__((__weak__)) + +#endif /* __LINUX_COMPILER_ATTRIBUTES_H */ diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h new file mode 100644 index 0000000000..1a3060117f --- /dev/null +++ b/include/linux/compiler_types.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_COMPILER_TYPES_H +#define __LINUX_COMPILER_TYPES_H + +#ifndef __ASSEMBLY__ + +#ifdef __CHECKER__ +# define __user __attribute__((noderef, address_space(1))) +# define __kernel __attribute__((address_space(0))) +# define __safe __attribute__((safe)) +# define __force __attribute__((force)) +# define __nocast __attribute__((nocast)) +# define __iomem __attribute__((noderef, address_space(2))) +# define __must_hold(x) __attribute__((context(x,1,1))) +# define __acquires(x) __attribute__((context(x,0,1))) +# define __releases(x) __attribute__((context(x,1,0))) +# define __acquire(x) __context__(x,1) +# define __release(x) __context__(x,-1) +# define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0) +# define __percpu __attribute__((noderef, address_space(3))) +# define __rcu __attribute__((noderef, address_space(4))) +# define __private __attribute__((noderef)) +extern void __chk_user_ptr(const volatile void __user *); +extern void __chk_io_ptr(const volatile void __iomem *); +# define ACCESS_PRIVATE(p, member) (*((typeof((p)->member) __force *) &(p)->member)) +#else /* __CHECKER__ */ +# ifdef STRUCTLEAK_PLUGIN +# define __user __attribute__((user)) +# else +# define __user +# endif +# define __kernel +# define __safe +# define __force +# define __nocast +# define __iomem +# define __chk_user_ptr(x) (void)0 +# define __chk_io_ptr(x) (void)0 +# define __builtin_warning(x, y...) (1) +# define __must_hold(x) +# define __acquires(x) +# define __releases(x) +# define __acquire(x) (void)0 +# define __release(x) (void)0 +# define __cond_lock(x,c) (c) +# define __percpu +# define __rcu +# define __private +# define ACCESS_PRIVATE(p, member) ((p)->member) +#endif /* __CHECKER__ */ + +/* Indirect macros required for expanded argument pasting, eg. __LINE__. */ +#define ___PASTE(a,b) a##b +#define __PASTE(a,b) ___PASTE(a,b) + +#ifdef __KERNEL__ + +/* Attributes */ +#include <linux/compiler_attributes.h> + +/* Compiler specific macros. */ +#ifdef __clang__ +#include <linux/compiler-clang.h> +#elif defined(__INTEL_COMPILER) +#include <linux/compiler-intel.h> +#elif defined(__GNUC__) +/* The above compilers also define __GNUC__, so order is important here. */ +#include <linux/compiler-gcc.h> +#else +#error "Unknown compiler" +#endif + +/* + * Some architectures need to provide custom definitions of macros provided + * by linux/compiler-*.h, and can do so using asm/compiler.h. We include that + * conditionally rather than using an asm-generic wrapper in order to avoid + * build failures if any C compilation, which will include this file via an + * -include argument in c_flags, occurs prior to the asm-generic wrappers being + * generated. + */ +#ifdef CONFIG_HAVE_ARCH_COMPILER_H +#include <asm/compiler.h> +#endif + +struct ftrace_branch_data { + const char *func; + const char *file; + unsigned line; + union { + struct { + unsigned long correct; + unsigned long incorrect; + }; + struct { + unsigned long miss; + unsigned long hit; + }; + unsigned long miss_hit[2]; + }; +}; + +struct ftrace_likely_data { + struct ftrace_branch_data data; + unsigned long constant; +}; + +#ifdef CONFIG_ENABLE_MUST_CHECK +#define __must_check __attribute__((__warn_unused_result__)) +#else +#define __must_check +#endif + +#if defined(CC_USING_HOTPATCH) +#define notrace __attribute__((hotpatch(0, 0))) +#elif defined(CC_USING_PATCHABLE_FUNCTION_ENTRY) +#define notrace __attribute__((patchable_function_entry(0, 0))) +#else +#define notrace __attribute__((__no_instrument_function__)) +#endif + +/* + * it doesn't make sense on ARM (currently the only user of __naked) + * to trace naked functions because then mcount is called without + * stack and frame pointer being set up and there is no chance to + * restore the lr register to the value before mcount was called. + */ +#define __naked __attribute__((__naked__)) notrace + +#define __compiler_offsetof(a, b) __builtin_offsetof(a, b) + +/* + * Force always-inline if the user requests it so via the .config. + * Prefer gnu_inline, so that extern inline functions do not emit an + * externally visible function. This makes extern inline behave as per gnu89 + * semantics rather than c99. This prevents multiple symbol definition errors + * of extern inline functions at link time. + * A lot of inline functions can cause havoc with function tracing. + * Do not use __always_inline here, since currently it expands to inline again + * (which would break users of __always_inline). + */ +#if !CONFIG_IS_ENABLED(OPTIMIZE_INLINING) +#define inline inline __attribute__((__always_inline__)) __gnu_inline \ + __inline_maybe_unused notrace +#else +#define inline inline __gnu_inline \ + __inline_maybe_unused notrace +#endif + +/* + * gcc provides both __inline__ and __inline as alternate spellings of + * the inline keyword, though the latter is undocumented. New kernel + * code should only use the inline spelling, but some existing code + * uses __inline__. Since we #define inline above, to ensure + * __inline__ has the same semantics, we need this #define. + * + * However, the spelling __inline is strictly reserved for referring + * to the bare keyword. + */ +#define __inline__ inline + +/* + * GCC does not warn about unused static inline functions for -Wunused-function. + * Suppress the warning in clang as well by using __maybe_unused, but enable it + * for W=1 build. This will allow clang to find unused functions. Remove the + * __inline_maybe_unused entirely after fixing most of -Wunused-function warnings. + */ +#ifdef KBUILD_EXTRA_WARN1 +#define __inline_maybe_unused +#else +#define __inline_maybe_unused __maybe_unused +#endif + +/* + * Rather then using noinline to prevent stack consumption, use + * noinline_for_stack instead. For documentation reasons. + */ +#define noinline_for_stack noinline + +#endif /* __KERNEL__ */ + +#endif /* __ASSEMBLY__ */ + +/* + * The below symbols may be defined for one or more, but not ALL, of the above + * compilers. We don't consider that to be an error, so set them to nothing. + * For example, some of them are for compiler specific plugins. + */ +#ifndef __latent_entropy +# define __latent_entropy +#endif + +#ifndef __randomize_layout +# define __randomize_layout __designated_init +#endif + +#ifndef __no_randomize_layout +# define __no_randomize_layout +#endif + +#ifndef randomized_struct_fields_start +# define randomized_struct_fields_start +# define randomized_struct_fields_end +#endif + +#ifndef asm_volatile_goto +#define asm_volatile_goto(x...) asm goto(x) +#endif + +#ifdef CONFIG_CC_HAS_ASM_INLINE +#define asm_inline asm __inline +#else +#define asm_inline asm +#endif + +#ifndef __no_fgcse +# define __no_fgcse +#endif + +/* Are two types/vars the same type (ignoring qualifiers)? */ +#define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) + +/* Is this type a native word size -- useful for atomic operations */ +#define __native_word(t) \ + (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || \ + sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long)) + +/* Helpers for emitting diagnostics in pragmas. */ +#ifndef __diag +#define __diag(string) +#endif + +#ifndef __diag_GCC +#define __diag_GCC(version, severity, string) +#endif + +#define __diag_push() __diag(push) +#define __diag_pop() __diag(pop) + +#define __diag_ignore(compiler, version, option, comment) \ + __diag_ ## compiler(version, ignore, option) +#define __diag_warn(compiler, version, option, comment) \ + __diag_ ## compiler(version, warn, option) +#define __diag_error(compiler, version, option, comment) \ + __diag_ ## compiler(version, error, option) + +#endif /* __LINUX_COMPILER_TYPES_H */ diff --git a/include/net.h b/include/net.h index 00a8ec0c78..1bf9867f8c 100644 --- a/include/net.h +++ b/include/net.h @@ -897,9 +897,6 @@ int is_serverip_in_cmd(void); */ int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len); -/* get a random source port */ -unsigned int random_port(void); - /** * update_tftp - Update firmware over TFTP (via DFU) * diff --git a/include/phy.h b/include/phy.h index b5de14cbfc..fedd146091 100644 --- a/include/phy.h +++ b/include/phy.h @@ -170,6 +170,13 @@ struct fixed_link { int asym_pause; }; +/** + * phy_read - Convenience function for reading a given PHY register + * @phydev: the phy_device struct + * @devad: The MMD to read from + * @regnum: register number to read + * @return: value for success or negative errno for failure + */ static inline int phy_read(struct phy_device *phydev, int devad, int regnum) { struct mii_dev *bus = phydev->bus; @@ -182,6 +189,14 @@ static inline int phy_read(struct phy_device *phydev, int devad, int regnum) return bus->read(bus, phydev->addr, devad, regnum); } +/** + * phy_write - Convenience function for writing a given PHY register + * @phydev: the phy_device struct + * @devad: The MMD to read from + * @regnum: register number to write + * @val: value to write to @regnum + * @return: 0 for success or negative errno for failure + */ static inline int phy_write(struct phy_device *phydev, int devad, int regnum, u16 val) { @@ -195,6 +210,13 @@ static inline int phy_write(struct phy_device *phydev, int devad, int regnum, return bus->write(bus, phydev->addr, devad, regnum, val); } +/** + * phy_mmd_start_indirect - Convenience function for writing MMD registers + * @phydev: the phy_device struct + * @devad: The MMD to read from + * @regnum: register number to write + * @return: None + */ static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad, int regnum) { @@ -209,6 +231,14 @@ static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad, (devad | MII_MMD_CTRL_NOINCR)); } +/** + * phy_read_mmd - Convenience function for reading a register + * from an MMD on a given PHY. + * @phydev: The phy_device struct + * @devad: The MMD to read from + * @regnum: The register on the MMD to read + * @return: Value for success or negative errno for failure + */ static inline int phy_read_mmd(struct phy_device *phydev, int devad, int regnum) { @@ -233,6 +263,15 @@ static inline int phy_read_mmd(struct phy_device *phydev, int devad, return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA); } +/** + * phy_write_mmd - Convenience function for writing a register + * on an MMD on a given PHY. + * @phydev: The phy_device struct + * @devad: The MMD to read from + * @regnum: The register on the MMD to read + * @val: value to write to @regnum + * @return: 0 for success or negative errno for failure + */ static inline int phy_write_mmd(struct phy_device *phydev, int devad, int regnum, u16 val) { @@ -257,6 +296,60 @@ static inline int phy_write_mmd(struct phy_device *phydev, int devad, return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val); } +/** + * phy_set_bits_mmd - Convenience function for setting bits in a register + * on MMD + * @phydev: the phy_device struct + * @devad: the MMD containing register to modify + * @regnum: register number to modify + * @val: bits to set + * @return: 0 for success or negative errno for failure + */ +static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad, + u32 regnum, u16 val) +{ + int value, ret; + + value = phy_read_mmd(phydev, devad, regnum); + if (value < 0) + return value; + + value |= val; + + ret = phy_write_mmd(phydev, devad, regnum, value); + if (ret < 0) + return ret; + + return 0; +} + +/** + * phy_clear_bits_mmd - Convenience function for clearing bits in a register + * on MMD + * @phydev: the phy_device struct + * @devad: the MMD containing register to modify + * @regnum: register number to modify + * @val: bits to clear + * @return: 0 for success or negative errno for failure + */ +static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad, + u32 regnum, u16 val) +{ + int value, ret; + + value = phy_read_mmd(phydev, devad, regnum); + if (value < 0) + return value; + + value &= ~val; + + ret = phy_write_mmd(phydev, devad, regnum, value); + if (ret < 0) + return ret; + + return 0; +} + #ifdef CONFIG_PHYLIB_10G extern struct phy_driver gen10g_driver; @@ -275,26 +368,23 @@ static inline int is_10g_interface(phy_interface_t interface) /** * phy_init() - Initializes the PHY drivers - * * This function registers all available PHY drivers * - * @return 0 if OK, -ve on error + * @return: 0 if OK, -ve on error */ int phy_init(void); /** * phy_reset() - Resets the specified PHY - * * Issues a reset of the PHY and waits for it to complete * * @phydev: PHY to reset - * @return 0 if OK, -ve on error + * @return: 0 if OK, -ve on error */ int phy_reset(struct phy_device *phydev); /** * phy_find_by_mask() - Searches for a PHY on the specified MDIO bus - * * The function checks the PHY addresses flagged in phy_mask and returns a * phy_device pointer if it detects a PHY. * This function should only be called if just one PHY is expected to be present @@ -304,7 +394,7 @@ int phy_reset(struct phy_device *phydev); * @bus: MII/MDIO bus to scan * @phy_mask: bitmap of PYH addresses to scan * @interface: type of MAC-PHY interface - * @return pointer to phy_device if a PHY is found, or NULL otherwise + * @return: pointer to phy_device if a PHY is found, or NULL otherwise */ struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, phy_interface_t interface); @@ -320,7 +410,6 @@ void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); /** * phy_connect() - Creates a PHY device for the Ethernet interface - * * Creates a PHY device for the PHY at the given address, if one doesn't exist * already, and associates it with the Ethernet device. * The function may be called with addr <= 0, in this case addr value is ignored @@ -332,7 +421,7 @@ void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); * @addr: PHY address on MDIO bus * @dev: Ethernet device to associate to the PHY * @interface: type of MAC-PHY interface - * @return pointer to phy_device if a PHY is found, or NULL otherwise + * @return: pointer to phy_device if a PHY is found, or NULL otherwise */ struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct udevice *dev, @@ -356,7 +445,6 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); /** * phy_connect() - Creates a PHY device for the Ethernet interface - * * Creates a PHY device for the PHY at the given address, if one doesn't exist * already, and associates it with the Ethernet device. * The function may be called with addr <= 0, in this case addr value is ignored @@ -368,7 +456,7 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); * @addr: PHY address on MDIO bus * @dev: Ethernet device to associate to the PHY * @interface: type of MAC-PHY interface - * @return pointer to phy_device if a PHY is found, or NULL otherwise + * @return: pointer to phy_device if a PHY is found, or NULL otherwise */ struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct eth_device *dev, @@ -428,7 +516,7 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); * phy_get_interface_by_name() - Look up a PHY interface name * * @str: PHY interface name, e.g. "mii" - * @return PHY_INTERFACE_MODE_... value, or -1 if not found + * @return: PHY_INTERFACE_MODE_... value, or -1 if not found */ int phy_get_interface_by_name(const char *str); @@ -436,6 +524,7 @@ int phy_get_interface_by_name(const char *str); * phy_interface_is_rgmii - Convenience function for testing if a PHY interface * is RGMII (all variants) * @phydev: the phy_device struct + * @return: true if MII bus is RGMII or false if it is not */ static inline bool phy_interface_is_rgmii(struct phy_device *phydev) { @@ -447,6 +536,7 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev) * phy_interface_is_sgmii - Convenience function for testing if a PHY interface * is SGMII (all variants) * @phydev: the phy_device struct + * @return: true if MII bus is SGMII or false if it is not */ static inline bool phy_interface_is_sgmii(struct phy_device *phydev) { diff --git a/include/spi.h b/include/spi.h index 5cc6d6e008..9b4fb8dc0b 100644 --- a/include/spi.h +++ b/include/spi.h @@ -39,7 +39,7 @@ #define SPI_DEFAULT_WORDLEN 8 -#ifdef CONFIG_DM_SPI +#if CONFIG_IS_ENABLED(DM_SPI) /* TODO(sjg@chromium.org): Remove this and use max_hz from struct spi_slave */ struct dm_spi_bus { uint max_hz; @@ -131,7 +131,7 @@ enum spi_polarity { * @flags: Indication of SPI flags. */ struct spi_slave { -#ifdef CONFIG_DM_SPI +#if CONFIG_IS_ENABLED(DM_SPI) struct udevice *dev; /* struct spi_slave is dev->parentdata */ uint max_hz; uint speed; @@ -317,7 +317,7 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len); */ int spi_cs_is_valid(unsigned int bus, unsigned int cs); -#ifndef CONFIG_DM_SPI +#if !CONFIG_IS_ENABLED(DM_SPI) /** * Activate a SPI chipselect. * This function is provided by the board code when using a driver @@ -367,7 +367,7 @@ static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) return ret < 0 ? ret : din[1]; } -#ifdef CONFIG_DM_SPI +#if CONFIG_IS_ENABLED(DM_SPI) /** * struct spi_cs_info - Information about a bus chip select diff --git a/include/spi_flash.h b/include/spi_flash.h index d9b2af856c..b336619487 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -39,7 +39,7 @@ struct dm_spi_flash_ops { /* Access the serial operations for a device */ #define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops) -#ifdef CONFIG_DM_SPI_FLASH +#if CONFIG_IS_ENABLED(DM_SPI_FLASH) /** * spi_flash_read_dm() - Read data from SPI flash * diff --git a/include/test/export.h b/include/test/export.h new file mode 100644 index 0000000000..afc755a8ff --- /dev/null +++ b/include/test/export.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + */ + +#ifndef TEST_EXPORT_H +#define TEST_EXPORT_H + +/* Declare something static, unless we are doing unit tests */ +#ifdef CONFIG_UNIT_TEST +#define TEST_STATIC +#else +#define TEST_STATIC static +#endif + +#endif /* TEST_EXPORT_H */ diff --git a/include/u-boot/rsa-checksum.h b/include/u-boot/rsa-checksum.h index 02b814d34e..54e6a73744 100644 --- a/include/u-boot/rsa-checksum.h +++ b/include/u-boot/rsa-checksum.h @@ -10,6 +10,7 @@ #include <image.h> #include <u-boot/sha1.h> #include <u-boot/sha256.h> +#include <u-boot/sha512.h> /** * hash_calculate() - Calculate hash over the data diff --git a/include/u-boot/sha512.h b/include/u-boot/sha512.h new file mode 100644 index 0000000000..516729d775 --- /dev/null +++ b/include/u-boot/sha512.h @@ -0,0 +1,38 @@ +#ifndef _SHA512_H +#define _SHA512_H + +#define SHA384_SUM_LEN 48 +#define SHA384_DER_LEN 19 +#define SHA512_SUM_LEN 64 +#define SHA512_DER_LEN 19 +#define SHA512_BLOCK_SIZE 128 + +#define CHUNKSZ_SHA384 (16 * 1024) +#define CHUNKSZ_SHA512 (16 * 1024) + +typedef struct { + uint64_t state[SHA512_SUM_LEN / 8]; + uint64_t count[2]; + uint8_t buf[SHA512_BLOCK_SIZE]; +} sha512_context; + +extern const uint8_t sha512_der_prefix[]; + +void sha512_starts(sha512_context * ctx); +void sha512_update(sha512_context *ctx, const uint8_t *input, uint32_t length); +void sha512_finish(sha512_context * ctx, uint8_t digest[SHA512_SUM_LEN]); + +void sha512_csum_wd(const unsigned char *input, unsigned int ilen, + unsigned char *output, unsigned int chunk_sz); + +extern const uint8_t sha384_der_prefix[]; + +void sha384_starts(sha512_context * ctx); +void sha384_update(sha512_context *ctx, const uint8_t *input, uint32_t length); +void sha384_finish(sha512_context * ctx, uint8_t digest[SHA384_SUM_LEN]); + +void sha384_csum_wd(const unsigned char *input, unsigned int ilen, + unsigned char *output, unsigned int chunk_sz); + + +#endif /* _SHA512_H */ diff --git a/include/zynqpl.h b/include/zynqpl.h index 766e6918cd..d7dc064585 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,7 +12,8 @@ #include <xilinx.h> #ifdef CONFIG_CMD_ZYNQ_AES -int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen); +int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen, + u8 bstype); #endif extern struct xilinx_fpga_op zynq_op; |