diff options
Diffstat (limited to 'include')
58 files changed, 2186 insertions, 107 deletions
diff --git a/include/common.h b/include/common.h index 3df1defab1..a2c6b27d43 100644 --- a/include/common.h +++ b/include/common.h @@ -265,7 +265,8 @@ int run_command (const char *cmd, int flag); int run_command2(const char *cmd, int flag); #endif int readline (const char *const prompt); -int readline_into_buffer (const char *const prompt, char * buffer); +int readline_into_buffer(const char *const prompt, char *buffer, + int timeout); int parse_line (char *, char *[]); void init_cmd_timeout(void); void reset_cmd_timeout(void); @@ -284,6 +285,7 @@ int last_stage_init(void); extern ulong monitor_flash_len; int mac_read_from_eeprom(void); extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */ +int set_cpu_clk_info(void); /* * Called when console output is requested before the console is available. diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 16db98fe57..c26cb639b3 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -659,6 +659,7 @@ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #else diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index af4609f841..f2d33668d8 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -519,10 +519,6 @@ extern unsigned long get_sdram_size(void); #endif #if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI -#endif - #define CONFIG_MII /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 @@ -609,6 +605,7 @@ extern unsigned long get_sdram_size(void); #if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_RAMBOOT_SPIFLASH) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index cee788ab13..2ac93be4ec 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -518,6 +518,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_RAMBOOT_SPIFLASH) diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h index cf20d2b2ee..365322c6a5 100644 --- a/include/configs/P2020COME.h +++ b/include/configs/P2020COME.h @@ -350,6 +350,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #if defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_RAMBOOT_SPIFLASH) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 2d9657a153..f0eb0294aa 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -596,6 +596,7 @@ */ #if defined(CONFIG_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_SPIFLASH) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index a48055e2c5..da98f8f027 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -92,6 +92,7 @@ #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC + #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 1097) diff --git a/include/configs/PM826.h b/include/configs/PM826.h index f4f93059fa..cde0fd67ab 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -100,11 +100,9 @@ * * if CONFIG_ETHER_ON_SCC is selected, then * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) - * - CONFIG_NET_MULTI must not be defined * * if CONFIG_ETHER_ON_FCC is selected, then * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected - * - CONFIG_NET_MULTI must be defined * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. diff --git a/include/configs/PM828.h b/include/configs/PM828.h index 28666d646b..74ced5ae22 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -100,11 +100,9 @@ * * if CONFIG_ETHER_ON_SCC is selected, then * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) - * - CONFIG_NET_MULTI must not be defined * * if CONFIG_ETHER_ON_FCC is selected, then * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected - * - CONFIG_NET_MULTI must be defined * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 5cc8ece7de..76cd394db2 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -169,8 +169,7 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* to be activated as soon as s3c24x0 has print_cpuinfo support */ -/*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ #define CONFIG_DISPLAY_BOARDINFO /* Display board info */ #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index f797f3ffd9..b5f75d1e8d 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -192,8 +192,7 @@ "console=ttyO2,115200n8\0" \ "mmcdev=0\0" \ "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ + "root=/dev/mmcblk0p2 rw rootwait\0" \ "nandargs=setenv bootargs console=${console} " \ "root=/dev/mtdblock4 rw " \ "rootfstype=jffs2\0" \ diff --git a/include/configs/calimain.h b/include/configs/calimain.h new file mode 100644 index 0000000000..6b68f103d2 --- /dev/null +++ b/include/configs/calimain.h @@ -0,0 +1,363 @@ +/* + * Copyright (C) 2011 OMICRON electronics GmbH + * + * Based on da850evm.h. Original Copyrights follow: + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Board + */ +#define CONFIG_DRIVER_TI_EMAC +#define MACH_TYPE_CALIMAIN 3528 +#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN + +/* + * SoC Configuration + */ +#define CONFIG_MACH_DAVINCI_CALIMAIN +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) +#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() +#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_DA850_LOWLEVEL +#define CONFIG_SYS_DA850_PLL_INIT +#define CONFIG_SYS_DA850_DDR_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DA8XX_GPIO +#define CONFIG_HW_WATCHDOG +#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE +#define CONFIG_SYS_WDT_PERIOD_LOW \ + (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ +#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 +#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) + +/* + * PLL configuration + */ +#define CONFIG_SYS_DV_CLKMODE 0 +#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 +#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 + +#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 + +#define CONFIG_SYS_DA850_PLL0_PLLM \ + ((calimain_get_osc_freq() == 25000000) ? 23 : 24) +#define CONFIG_SYS_DA850_PLL1_PLLM \ + ((calimain_get_osc_freq() == 25000000) ? 20 : 21) + +/* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ + (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (2 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 + +/* + * Flash memory timing + */ + +#define CONFIG_SYS_DA850_CS2CFG ( \ + DAVINCI_ABCR_WSETUP(2) | \ + DAVINCI_ABCR_WSTROBE(5) | \ + DAVINCI_ABCR_WHOLD(3) | \ + DAVINCI_ABCR_RSETUP(1) | \ + DAVINCI_ABCR_RSTROBE(14) | \ + DAVINCI_ABCR_RHOLD(0) | \ + DAVINCI_ABCR_TA(3) | \ + DAVINCI_ABCR_ASIZE_16BIT) + +/* single 64 MB NOR flash device connected to CS2 and CS3 */ +#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG + +/* + * Memory Info + */ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ +#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ + +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2 | \ + DAVINCI_SYSCFG_SUSPSRC_EMAC | \ + DAVINCI_SYSCFG_SUSPSRC_I2C) + +/* memtest start addr */ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) + +/* memtest will be run on 16MB */ +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) + +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ + +/* + * Serial Driver info + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ +#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ +#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ +#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ +#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2) +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */ +#define CONFIG_SYS_MAX_FLASH_SECT \ + ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3) + +/* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +/* + * U-Boot general configuration + */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "Calimain > " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) +#define CONFIG_LOADADDR 0xc0700000 +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* + * Linux Information + */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS "" +#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" +#define CONFIG_BOOTDELAY 0 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_DELAY_STR "\x0d" /* press ENTER to interrupt BOOT */ +#define CONFIG_RESET_TO_RETRY + +/* + * Default environment settings + * gpio0 = button, gpio1 = led green, gpio2 = led red + * verify = n ... disable kernel checksum verification for faster booting + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "tftpdir=calimero\0" \ + "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \ + "erase 0x60800000 +0x400000; " \ + "cp.b $loadaddr 0x60800000 $filesize\0" \ + "flashrootfs=" \ + "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \ + "erase 0x60c00000 +0x2e00000; " \ + "cp.b $loadaddr 0x60c00000 $filesize\0" \ + "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \ + "protect off all; " \ + "erase 0x60000000 +0x80000; " \ + "cp.b $loadaddr 0x60000000 $filesize\0" \ + "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \ + "erase 0x60080000 +0x780000; " \ + "cp.b $loadaddr 0x60080000 $filesize\0" \ + "erase_persistent=erase 0x63a00000 +0x600000;\0" \ + "bootnor=setenv bootargs console=ttyS2,115200n8 " \ + "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ + "rootwait ethaddr=$ethaddr; " \ + "gpio c 1; gpio s 2; bootm 0x60800000\0" \ + "bootrlk=gpio s 1; gpio s 2;" \ + "setenv bootargs console=ttyS2,115200n8 " \ + "ethaddr=$ethaddr; bootm 0x60080000\0" \ + "boottftp=setenv bootargs console=ttyS2,115200n8 " \ + "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ + "rootwait ethaddr=$ethaddr; " \ + "tftpboot $loadaddr $tftpdir/uImage;" \ + "gpio c 1; gpio s 2; bootm $loadaddr\0" \ + "checkupdate=if test -n $update_flag; then " \ + "echo Previous update failed - starting RLK; " \ + "run bootrlk; fi; " \ + "if test -n $initial_setup; then " \ + "echo Running initial setup procedure; " \ + "sleep 1; run flashall; fi\0" \ + "product=accessory\0" \ + "serial=XX12345\0" \ + "checknor=" \ + "if gpio i 0; then run bootnor; fi;\0" \ + "checkrlk=" \ + "if gpio i 0; then run bootrlk; fi;\0" \ + "checkbutton=" \ + "run checknor; sleep 1;" \ + "run checknor; sleep 1;" \ + "run checknor; sleep 1;" \ + "run checknor; sleep 1;" \ + "run checknor;" \ + "gpio s 1; gpio s 2;" \ + "echo ---- Release button to boot RLK ----;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk; sleep 1;" \ + "run checkrlk;" \ + "echo ---- Factory reset requested ----;" \ + "gpio c 1;" \ + "setenv factory_reset true;" \ + "saveenv;" \ + "run bootnor;\0" \ + "flashall=run flashrlk;" \ + "run flashkernel;" \ + "run flashrootfs;" \ + "setenv erase_datafs true;" \ + "setenv initial_setup;" \ + "saveenv;" \ + "run bootnor;\0" \ + "verify=n\0" \ + "clearenv=protect off all;" \ + "erase 0x60040000 +0x40000;\0" \ + "bootlimit=3\0" \ + "altbootcmd=run bootrlk\0" + +#define CONFIG_PREBOOT \ + "echo Version: $ver; " \ + "echo Serial: $serial; " \ + "echo MAC: $ethaddr; " \ + "echo Product: $product; " \ + "gpio c 1; gpio c 2;" + +/* + * U-Boot commands + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_GPIO + +#ifndef CONFIG_DRIVER_TI_EMAC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#endif + +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +/* initial stack pointer in internal SRAM */ +#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) + +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE + +#ifndef __ASSEMBLY__ +int calimain_get_osc_freq(void); +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 5d9672fbc8..0fee53f750 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -68,7 +68,6 @@ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI #define CONFIG_CMD_MII #define CONFIG_SYS_DCACHE_OFF #define CONFIG_RESET_PHY_R @@ -122,6 +121,10 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #ifdef CONFIG_MMC #define CONFIG_DOS_PARTITION #define CONFIG_CMD_EXT2 @@ -135,7 +138,9 @@ #define CONFIG_MTD_DEVICE #define CONFIG_CMD_NAND #define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS #define CONFIG_RBTREE +#define CONFIG_LZO #endif #define CONFIG_CRC32_VERIFY @@ -153,15 +158,24 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_LONGHELP +#define CONFIG_MENU +#define CONFIG_MENU_SHOW +#define CONFIG_FIT +#define CONFIG_CMD_PXE +#define CONFIG_BOARD_IMG_ADDR_R 0x80000000 + #ifdef CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ +#define CONFIG_ENV_SIZE (16 << 10) #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_OFFSET 0x180000 +#define CONFIG_ENV_OFFSET_REDUND 0x1c0000 +#define CONFIG_ENV_RANGE 0x020000 #undef CONFIG_ENV_IS_IN_FLASH #endif #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_CMD_ENV +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ #define CONFIG_ENV_IS_IN_MMC @@ -169,6 +183,11 @@ #endif #define CONFIG_BOOTDELAY 3 +/* + * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running + * Timeout 1 second. + */ +#define CONFIG_AIT_TIMER_TIMEOUT 0x186a00 #define CONFIG_CMDLINE_EDITING #define CONFIG_VERSION_VARIABLE @@ -187,20 +206,17 @@ #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ #define MTDIDS_DEFAULT "nand0=davinci_nand.0" - -#ifdef CONFIG_SYS_NAND_LARGEPAGE -/* Use same layout for 128K/256K blocks; allow some bad blocks */ -#define PART_BOOT "2m(bootloader)ro," -#endif - -#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ -#define PART_REST "-(filesystem)" - -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST - -#define CONFIG_SYS_NAND_PAGE_SIZE (0x800) -#define CONFIG_SYS_NAND_BLOCK_SIZE (0x20000) +#define MTDPARTS_DEFAULT \ + "mtdparts=" \ + "davinci_nand.0:" \ + "128k(spl)," \ + "384k(UBLheader)," \ + "1m(u-boot)," \ + "512k(env)," \ + "-(ubi)" + +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 /* Defines for SPL */ #define CONFIG_SPL @@ -241,7 +257,6 @@ * so we can define, how many UBL Headers * we can write before the real spl code */ -#define CONFIG_SYS_NROF_UBL_HEADER 5 #define CONFIG_SYS_NROF_PAGES_NAND_SPL 6 #define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */ @@ -253,19 +268,12 @@ #define CONFIG_POST CONFIG_SYS_POST_MEMORY #define _POST_WORD_ADDR 0x0 -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xc0000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 - -/* - * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is - * done in board_init_f from c code. - */ -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 /* for UBL header */ #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE) @@ -411,14 +419,14 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \ - "load=tftp ${u_boot_addr_r} ${uboot}\0" \ + "load=tftp ${u_boot_addr_r} ${u-boot}\0" \ "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \ - "writeheader=nandrbl rbl;nand erase 80000 ${pagesz};" \ - "nand write ${u_boot_addr_r} 80000 ${pagesz};" \ + "writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \ + "nand write ${u_boot_addr_r} 20000 ${pagesz};" \ "nandrbl uboot\0" \ - "writenand_spl=nandrbl rbl;nand erase a0000 3000;" \ + "writenand_spl=nandrbl rbl;nand erase 0 3000;" \ "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \ - " a0000 3000;nandrbl uboot\0" \ + " 0 3000;nandrbl uboot\0" \ "writeuboot=nandrbl uboot;" \ "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \ @@ -426,8 +434,77 @@ " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \ "update=run load writenand_spl writeuboot\0" \ - "bootcmd=run bootcmd\0" \ + "bootcmd=run net_nfs\0" \ + "rootpath=/opt/eldk-arm/arm\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "netdev=eth0\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyS0," \ + "${baudrate}n8\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0" \ "rootpath=/opt/eldk-arm/arm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage \0" \ + "kernel_addr_r=80600000\0" \ + "load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \ + "ubi_load_kernel=ubi part ubi 2048;ubifsmount ${img_volume};" \ + "ubifsload ${kernel_addr_r} boot/uImage\0" \ + "fit_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \ + "img_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \ + "img_file=" xstr(CONFIG_HOSTNAME) "/ait.itb\0" \ + "header_addr=20000\0" \ + "img_writeheader=nandrbl rbl;" \ + "nand erase ${header_addr} ${pagesz};" \ + "nand write ${img_addr_r} ${header_addr} ${pagesz};" \ + "nandrbl uboot\0" \ + "img_writespl=nandrbl rbl;nand erase 0 3000;" \ + "nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \ + "img_writeuboot=nandrbl uboot;" \ + "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ + xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \ + ";nand write ${img_addr_r} " \ + xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ + xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \ + "img_writedfenv=ubi part ubi 2048;" \ + "ubi write ${img_addr_r} default ${filesize}\0" \ + "img_volume=rootfs1\0" \ + "img_writeramdisk=ubi part ubi 2048;ubifsmount ${img_volume};" \ + "ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \ + "load_img=tftp ${fit_addr_r} ${img_file}\0" \ + "net_nfs=run load_kernel; " \ + "run nfsargs addip addcon addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "ubi_ubi=run ubi_load_kernel; " \ + "run ubiargs addip addcon addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "ubiargs=setenv bootargs ubi.mtd=4,2048" \ + " root=ubi0:${img_volume} rw rootfstype=ubifs\0" \ + "app_reset=no\0" \ + "dvn_app_vers=void\0" \ + "dvn_boot_vers=void\0" \ + "savenewvers=run savetmpparms restoreparms; saveenv;" \ + "run restoretmpparms\0" \ + "savetmpparms=setenv y_ipaddr ${ipaddr};" \ + "setenv y_netmask ${netmask};" \ + "setenv y_serverip ${serverip};" \ + "setenv y_gatewayip ${gatewayip}\0" \ + "saveparms=setenv x_ipaddr ${ipaddr};" \ + "setenv x_netmask ${netmask};" \ + "setenv x_serverip ${serverip};" \ + "setenv x_gatewayip ${gatewayip}\0" \ + "restoreparms=setenv ipaddr ${x_ipaddr};" \ + "setenv netmask ${x_netmask};" \ + "setenv serverip ${x_serverip};" \ + "setenv gatewayip ${x_gatewayip}\0" \ + "restoretmpparms=setenv ipaddr ${y_ipaddr};" \ + "setenv netmask ${y_netmask};" \ + "setenv serverip ${y_serverip};" \ + "setenv gatewayip ${y_gatewayip}\0" \ "\0" /* USB Configuration */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 348a25bd1f..2c65d74496 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -216,10 +216,4 @@ */ #define CONFIG_PCI -/*----------------------------------------------------------------------- - * Network device support - */ -#define CONFIG_NET_MULTI - - #endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7925b95838..77dd0a2d1e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -88,6 +88,7 @@ #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 1097) diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index e8c021262a..4532e4f4fd 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -203,6 +203,10 @@ #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_SETGETDCR +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #ifndef CONFIG_DRIVER_TI_EMAC #undef CONFIG_CMD_NET #undef CONFIG_CMD_DHCP diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 220890dfd9..989472b181 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -37,13 +37,15 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000 +#define CONFIG_SYS_DA850_PLL_INIT +#define CONFIG_SYS_DA850_DDR_INIT /* * Memory Info @@ -142,7 +144,6 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2 #define CONFIG_SPI #define CONFIG_SPI_FLASH @@ -269,6 +270,10 @@ #define CONFIG_CMD_SAVES #define CONFIG_CMD_MEMORY +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #ifndef CONFIG_DRIVER_TI_EMAC #undef CONFIG_CMD_NET #undef CONFIG_CMD_DHCP @@ -318,7 +323,7 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" #define CONFIG_SPL_STACK 0x8001ff00 #define CONFIG_SPL_TEXT_BASE 0x80000000 #define CONFIG_SPL_MAX_SIZE 32768 diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index ddf673c846..42caf1e42a 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -26,7 +26,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ #define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_DISPLAY_CPUINFO /* SoC Configuration */ #define CONFIG_ARM926EJS /* arm926ejs CPU */ @@ -99,6 +98,10 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #ifdef CONFIG_MMC #define CONFIG_DOS_PARTITION #define CONFIG_CMD_EXT2 diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h index dc5b408a61..b05cfbaa8e 100644 --- a/include/configs/davinci_dm355leopard.h +++ b/include/configs/davinci_dm355leopard.h @@ -25,7 +25,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ #define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_DISPLAY_CPUINFO /* SoC Configuration */ #define CONFIG_ARM926EJS /* arm926ejs CPU */ @@ -84,6 +83,10 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #ifdef CONFIG_NAND_DAVINCI #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index cb6ed24a80..a75bce675b 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -142,6 +142,10 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #ifdef CONFIG_MMC #define CONFIG_DOS_PARTITION #define CONFIG_CMD_EXT2 diff --git a/include/configs/davinci_dm6467Tevm.h b/include/configs/davinci_dm6467Tevm.h index b3a4e44344..0cbdec8681 100644 --- a/include/configs/davinci_dm6467Tevm.h +++ b/include/configs/davinci_dm6467Tevm.h @@ -23,7 +23,6 @@ /* Spectrum Digital TMS320DM6467T EVM board */ #define DAVINCI_DM6467EVM #define DAVINCI_DM6467TEVM -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_USE_NAND #define CONFIG_SYS_NAND_SMALLPAGE @@ -153,6 +152,10 @@ extern unsigned int davinci_arm_clk_get(void); #define CONFIG_CMD_NAND #endif +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index c9a0cd1daa..e0fe6b5c24 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -22,7 +22,6 @@ /* Spectrum Digital TMS320DM6467 EVM board */ #define DAVINCI_DM6467EVM -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_USE_NAND #define CONFIG_SYS_NAND_SMALLPAGE @@ -151,6 +150,10 @@ extern unsigned int davinci_arm_clk_get(void); #define CONFIG_CMD_NAND #endif +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index c0525173e6..310d5770de 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -51,7 +51,6 @@ #define DV_EVM #define CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_SYS_USE_NAND -#define CONFIG_DISPLAY_CPUINFO /*===================*/ /* SoC Configuration */ /*===================*/ @@ -200,6 +199,11 @@ #define CONFIG_CMD_SAVES #define CONFIG_CMD_EEPROM #undef CONFIG_CMD_BDI + +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_SETGETDCR #ifdef CONFIG_SYS_USE_NAND diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index f4ddbeacc3..949174a163 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -26,7 +26,6 @@ #define SCHMOOGIE #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_USE_NAND -#define CONFIG_DISPLAY_CPUINFO #define MACH_TYPE_SCHMOOGIE 1255 #define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE @@ -149,6 +148,10 @@ #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 0c653915bd..c931ede85c 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_USE_NAND #define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */ -#define CONFIG_DISPLAY_CPUINFO /* SoC Configuration */ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ @@ -142,6 +141,10 @@ #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index fc4d8eceac..854099b2a2 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -51,7 +51,6 @@ #define SONATA_BOARD #define CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_SYS_USE_NOR -#define CONFIG_DISPLAY_CPUINFO #define MACH_TYPE_SONATA 1254 #define CONFIG_MACH_TYPE MACH_TYPE_SONATA /*===================*/ @@ -200,6 +199,10 @@ #error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!" #endif +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 diff --git a/include/configs/dns325.h b/include/configs/dns325.h new file mode 100644 index 0000000000..b7a89d358b --- /dev/null +++ b/include/configs/dns325.h @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2011 + * Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_DNS325_H +#define _CONFIG_DNS325_H + +/* + * Machine number definition + */ +#define MACH_TYPE_DNS325 3800 +#define CONFIG_MACH_TYPE MACH_TYPE_DNS325 +#define CONFIG_IDENT_STRING "\nD-Link DNS-325" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_IDE +#define CONFIG_CMD_DATE +#define CONFIG_SYS_MVFS + +#define CONFIG_NR_DRAM_BANKS 1 + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "=> " + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_NETCONSOLE +#endif + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif + +/* + * RTC driver configuration + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Display cpu info at boot + */ +#define CONFIG_DISPLAY_CPUINFO + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_ADDR 0xe0000 +#define CONFIG_ENV_OFFSET 0xe0000 /* env starts here */ + +/* + * Default environment variables + */ +#define MTDIDS_DEFAULT "nand0=orion_nand" + +#define MTDPARTS_DEFAULT "mtdparts=orion_nand:" \ + "896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "console=ttyS0,115200\0" \ + "mtdparts="MTDPARTS_DEFAULT \ + "optargs=\0" \ + "bootenv=uEnv.txt\0" \ + "importbootenv=echo Importing environment ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadbootenv=fatload usb 0 ${loadaddr} ${bootenv}\0" \ + "setbootargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${bootenvroot} " \ + "rootfstype=${bootenvrootfstype}\0" \ + "subbootcmd=run setbootargs; " \ + "if run bootenvloadimage; then " \ + "bootm ${loadaddr};" \ + "fi;\0" \ + "nandroot=ubi0:rootfs ubi.mtd=rootfs\0" \ + "nandrootfstype=ubifs\0" \ + "nandloadimage=nand read ${loadaddr} kernel\0" \ + "setnandbootenv=echo Booting from nand ...; " \ + "setenv bootenvroot ${nandroot}; " \ + "setenv bootenvrootfstype ${nandrootfstype}; " \ + "setenv bootenvloadimage ${nandloadimage}\0" + +#define CONFIG_BOOTCOMMAND \ + "if test -n ${bootenv} && usb start; then " \ + "if run loadbootenv; then " \ + "echo Loaded environment ${bootenv} from usb;" \ + "run importbootenv;" \ + "fi;" \ + "if test -n ${bootenvcmd}; then " \ + "echo Running bootenvcmd ...;" \ + "run bootenvcmd;" \ + "fi;" \ + "fi;" \ + "run setnandbootenv subbootcmd;" + +#endif /* _CONFIG_DNS325_H */ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index cc0f5b05cd..b4610d9474 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -168,6 +168,10 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #ifndef CONFIG_DRIVER_TI_EMAC #undef CONFIG_CMD_NET #undef CONFIG_CMD_DHCP diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 2e2a9a7a99..4549a4c15e 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -88,7 +88,6 @@ #define CONFIG_SH_I2C_BASE1 0xA4750000 /* Ether */ -#define CONFIG_NET_MULTI 1 #define CONFIG_SH_ETHER 1 #define CONFIG_SH_ETHER_USE_PORT (0) #define CONFIG_SH_ETHER_PHY_ADDR (0x1f) diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 88d32b27d6..9b7cc66c65 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -134,6 +134,7 @@ #include <config_cmd_default.h> #define CONFIG_CMD_IDE #define CONFIG_CMD_I2C +#define CONFIG_CMD_USB /* * Network @@ -183,6 +184,19 @@ #endif /* CMD_IDE */ /* + * Common USB/EHCI configuration + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_MARVELL +#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* * I2C related stuff */ #ifdef CONFIG_CMD_I2C @@ -221,6 +235,16 @@ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 #define CONFIG_SYS_MAXARGS 16 +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Enable command line editing */ +#define CONFIG_CMDLINE_EDITING + +/* provide extensive help */ +#define CONFIG_SYS_LONGHELP + /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_SYS_INIT_SP_ADDR \ diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index 522487b395..e2f0f7465d 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -206,7 +206,6 @@ /* USB NET */ #ifdef CONFIG_CMD_NET #define CONFIG_USB_ETHER_ASIX -#define CONFIG_NET_MULTI #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #endif diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index 83aec790e6..29b0d33991 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -40,17 +40,18 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_DA850_LOWLEVEL #define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_DA850_PLL_INIT +#define CONFIG_SYS_DA850_DDR_INIT #define CONFIG_DA8XX_GPIO #define CONFIG_HOSTNAME enbw_cmc -#define CONFIG_DISPLAY_CPUINFO #define MACH_TYPE_ENBW_CMC 3585 #define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC @@ -83,7 +84,7 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2 + /* * I2C Configuration */ @@ -145,7 +146,6 @@ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI #endif /* @@ -271,6 +271,10 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_CACHE +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #ifndef CONFIG_DRIVER_TI_EMAC #undef CONFIG_CMD_NET #undef CONFIG_CMD_DHCP diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index f878665b29..604d2dd5f5 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -179,7 +179,6 @@ #endif /* Ethernet */ -#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_MACB #define CONFIG_RMII diff --git a/include/configs/flea3.h b/include/configs/flea3.h index aac3930f0a..649e27214c 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -113,7 +113,6 @@ /* * Ethernet on SOC (FEC) */ -#define CONFIG_NET_MULTI #define CONFIG_FEC_MXC #define IMX_FEC_BASE FEC_BASE_ADDR #define CONFIG_PHYLIB diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index fa214941af..50a1c171b6 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -35,6 +35,7 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE @@ -43,12 +44,29 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_UART_U_BOOT) +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_EMAC | \ + DAVINCI_SYSCFG_SUSPSRC_I2C | \ + DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2) + +#if defined(CONFIG_UART_U_BOOT) #define CONFIG_SYS_TEXT_BASE 0xc1080000 -#else +#elif !defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_TEXT_BASE 0xc1180000 #endif +/* Spl */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_LOAD +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-hawk.lds" +#define CONFIG_SPL_TEXT_BASE 0xc1080000 +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + /* * Memory Info */ @@ -84,9 +102,7 @@ /* * Network & Ethernet Configuration */ -#if !defined(CONFIG_NAND_SPL) #define CONFIG_DRIVER_TI_EMAC -#endif #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS @@ -185,6 +201,10 @@ #define CONFIG_CMD_SAVES #define CONFIG_CMD_MEMORY +#ifdef CONFIG_CMD_BDI +#define CONFIG_CLOCKS +#endif + #ifdef CONFIG_SYS_USE_NAND #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 9c8d222c2f..c73a10c667 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -194,7 +194,7 @@ int get_scl(void); #define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) #endif -#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ +#define I2C_DELAY udelay(1) #define I2C_SOFT_DECLARATIONS #endif diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 4efff0992b..4d59153706 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -187,7 +187,6 @@ * Ethernet on SOC (FEC) */ #ifdef CONFIG_CMD_NET -#define CONFIG_NET_MULTI #define CONFIG_ETHPRIME "FEC0" #define CONFIG_FEC_MXC #define CONFIG_FEC_MXC_MULTI diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000000..0940e86b86 --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on omap3_evm_config.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */ + +#define MACH_TYPE_MCX 3656 +#define CONFIG_MACH_TYPE MACH_TYPE_MCX + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +#define CONFIG_OF_LIBFDT +#define CONFIG_FIT + +/* + * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader + * and older u-boot.bin with the new U-Boot SPL. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/* + * DDR related + */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C + +/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "mcx # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/* + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * ethernet support + * + */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h new file mode 100644 index 0000000000..2034b59f47 --- /dev/null +++ b/include/configs/mt_ventoux.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2009 TechNexion Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tam3517-common.h" + +#define MACH_TYPE_AM3517_MT_VENTOUX 3832 +#define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX + +#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE + +#define CONFIG_HOSTNAME mt_ventoux + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "mt_ventoux => " +#define CONFIG_SYS_PROMPT V_PROMPT + +/* + * FPGA + */ +#define CONFIG_CMD_FPGA +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 10000 +#define CONFIG_MAX_FPGA_DEVICES 1 +#define CONFIG_FPGA_DELAY() udelay(1) +#define CONFIG_SYS_FPGA_PROG_FEEDBACK + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \ + "bootcmd=run net_nfs\0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 124a7a63ae..0962d3c8c4 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -86,6 +86,8 @@ "script=boot.scr\0" \ "uimage=uImage\0" \ "console=ttymxc3\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "mmcdev=1\0" \ "mmcpart=2\0" \ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 464f0ec650..d650ee340a 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -56,6 +56,17 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 @@ -66,8 +77,6 @@ #include <config_cmd_default.h> #undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS #define CONFIG_BOOTDELAY 3 @@ -78,6 +87,8 @@ "script=boot.scr\0" \ "uimage=uImage\0" \ "console=ttymxc3\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "mmcdev=0\0" \ "mmcpart=2\0" \ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 4c7a686d39..d3a0122a09 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -129,6 +129,14 @@ /* USB EHCI */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI + +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 + +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP + #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index b256317905..4910ddaa83 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -248,7 +248,6 @@ #if defined(CONFIG_CMD_NET) /* Ethernet (SMSC9115 from SMSC9118 family) */ -#define CONFIG_NET_MULTI #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE 0x2C000000 diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index a5746d160c..b819d21340 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -269,7 +269,6 @@ *---------------------------------------------------------------------------- */ #if defined(CONFIG_CMD_NET) - #define CONFIG_NET_MULTI #define CONFIG_SMC911X 1 #define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE 0x2C000000 diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index e9ef2a3782..b4756be528 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -31,9 +31,33 @@ /* * High Level Configuration Options */ -#define CONFIG_PANDA 1 /* working with Panda */ +#define CONFIG_PANDA /* working with Panda */ + +/* USB UHH support options */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62 + +/* USB Networking options */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +#define CONFIG_UBOOT_ENABLE_PADS_ALL + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP #include <configs/omap4_common.h> +#define CONFIG_CMD_NET /* GPIO */ #define CONFIG_CMD_GPIO diff --git a/include/configs/origen.h b/include/configs/origen.h index cd502d10d8..8ede82575c 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -52,8 +52,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING -/* MACH_TYPE_ORIGEN macro will be removed once added to mach-types */ -#define MACH_TYPE_ORIGEN 3455 #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN /* Power Down Modes */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 8e8fa163b8..3098c5acfe 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -630,7 +630,6 @@ #endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ #define CONFIG_CMD_PCI @@ -641,11 +640,6 @@ #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI -#endif - #define CONFIG_MII /* MII PHY management */ #define CONFIG_TSEC1 #define CONFIG_TSEC1_NAME "eTSEC1" @@ -733,6 +727,7 @@ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_NAND_U_BOOT) diff --git a/include/configs/paz00.h b/include/configs/paz00.h new file mode 100644 index 0000000000..f53f20eb97 --- /dev/null +++ b/include/configs/paz00.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2010,2011, NVIDIA CORPORATION. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/sizes.h> +#include "tegra2-common.h" + +/* High-level configuration options */ +#define TEGRA2_SYSMEM "mem=512M@0M" +#define V_PROMPT "Tegra2 (Paz00) MOD # " +#define CONFIG_TEGRA2_BOARD_STRING "Compal Paz00" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 +#define CONFIG_SYS_BOARD_ODMDATA 0x800c0085 /* lp1, 512MB */ + +#define CONFIG_BOARD_EARLY_INIT_F + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA2_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* Environment not stored */ +#define CONFIG_ENV_IS_NOWHERE +#endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index be000cbafe..8286680f26 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -49,6 +49,7 @@ /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index 73159846ef..7d163201e3 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -135,8 +135,7 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* may be activated as soon as s3c24x0 has print_cpuinfo support */ -/*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h new file mode 100644 index 0000000000..9659f9ebd9 --- /dev/null +++ b/include/configs/smdk5250.h @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ +#define CONFIG_SMDK5250 /* which is in a SMDK5250 */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* input clock of PLL: SMDK5250 has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ +#define MACH_TYPE_SMDK5250 3774 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* select serial console configuration */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_SERIAL1 /* use SERIAL 1 */ +#define CONFIG_BAUDRATE 115200 +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 + +#define TZPC_BASE_OFFSET 0x10000 + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_MMC + +#define CONFIG_BOARD_EARLY_INIT_F + +/* PWM */ +#define CONFIG_PWM + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NET + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* MMC SPL */ +#define CONFIG_SPL +#define COPY_BL2_FNPTR_ADDR 0x02020030 + +#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "SMDK5250 # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_SYS_HZ 1000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_RD_LVL + +/* Stack sizes */ +#define CONFIG_STACKSIZE (256 << 10) /* 256KB */ + +#define CONFIG_NR_DRAM_BANKS 8 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_IDENT_STRING " for SMDK5250" + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_SECURE_BL1_ONLY + +/* Secure FW size configuration */ +#ifdef CONFIG_SECURE_BL1_ONLY +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ +#else +#define CONFIG_SEC_FW_SIZE 0 +#endif + +/* Configuration of BL1, BL2, ENV Blocks on mmc */ +#define CONFIG_RES_BLOCK_SIZE (512) +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ + +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) +#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) + +/* U-boot copy size from boot Media to DRAM.*/ +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) +#define CONFIG_DOS_PARTITION + +#define CONFIG_IRAM_STACK 0x02050000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +/* Ethernet Controllor Driver */ +#ifdef CONFIG_CMD_NET +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE 0x5000000 +#define CONFIG_SMC911X_16_BIT +#define CONFIG_ENV_SROM_BANK 1 +#endif /*CONFIG_CMD_NET*/ + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +#endif /* __CONFIG_H */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index f4963ac07e..4c4321d2ff 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -100,6 +100,8 @@ #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_STORAGE @@ -238,7 +240,6 @@ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI /* Defines for SPL */ #define CONFIG_SPL @@ -296,8 +297,8 @@ /* Setup MTD for NAND on the SOM */ #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ - "512k(u-boot),128k(env1)," \ - "128k(env2),6m(kernel),-(rootfs)" + "1m(u-boot),256k(env1)," \ + "256k(env2),6m(kernel),-(rootfs)" #define xstr(s) str(s) #define str(s) #s diff --git a/include/configs/trats.h b/include/configs/trats.h new file mode 100644 index 0000000000..10f11d9579 --- /dev/null +++ b/include/configs/trats.h @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * Heungjun Kim <riverful.kim@samsung.com> + * + * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* which is in a S5P Family */ +#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */ +#define CONFIG_TRATS /* working with TRATS */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_L2CACHE_OFF + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x63300000 + +/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */ +#define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* MACH_TYPE_TRATS macro will be removed once added to mach-types */ +#define MACH_TYPE_TRATS 3928 +#define CONFIG_MACH_TYPE MACH_TYPE_TRATS + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* select serial console configuration */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_SERIAL2 /* use SERIAL 2 */ +#define CONFIG_BAUDRATE 115200 + +/* MMC */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_MMC + +/* PWM */ +#define CONFIG_PWM + +/* It should define before config_cmd_default.h */ +#define CONFIG_SYS_NO_FLASH + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_ONENAND +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_MMC + +#define CONFIG_BOOTDELAY 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run mmcboot" + +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" +#define CONFIG_BOOTBLOCK "10" +#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootk=" \ + "run loaduimage; bootm 0x40007FC0\0" \ + "updatemmc=" \ + "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ + "mmc boot 0 1 1 0\0" \ + "updatebackup=" \ + "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc boot 0 1 1 0\0" \ + "updatebootb=" \ + "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ + "lpj=lpj=3981312\0" \ + "nfsboot=" \ + "set bootargs root=/dev/nfs rw " \ + "nfsroot=${nfsroot},nolock,tcp " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ + "; run bootk\0" \ + "ramfsboot=" \ + "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \ + "${console} ${meminfo} " \ + "initrd=0x43000000,8M ramdisk=8192\0" \ + "mmcboot=" \ + "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ + "run loaduimage; bootm 0x40007FC0\0" \ + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ + "verify=n\0" \ + "rootfstype=ext4\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ + "meminfo=crashkernel=32M@0x50000000\0" \ + "nfsroot=/nfsroot/arm\0" \ + "bootblock=" CONFIG_BOOTBLOCK "\0" \ + "mmcdev=0\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=3\0" \ + "opts=always_resume=1" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "TRATS # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) + +#define CONFIG_SYS_HZ 1000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Stack sizes */ +#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */ + +/* TRATS has 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ +#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */ +#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ +#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */ + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ + +#define CONFIG_DOS_PARTITION + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#include <asm/arch/gpio.h> +/* + * I2C Settings + */ +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6) + +#define CONFIG_SOFT_I2C +#define CONFIG_SOFT_I2C_READ_REPEATED_START +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 7 + +#define CONFIG_PMIC +#define CONFIG_PMIC_I2C +#define CONFIG_PMIC_MAX8998 + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED + +#endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h new file mode 100644 index 0000000000..f87696b235 --- /dev/null +++ b/include/configs/tricorder.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * (C) Copyright 2012 + * Corscience GmbH & Co. KG + * Thomas Weber <weber@corscience.de> + * + * Configuration settings for the Tricorder board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ + +#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Display CPU and Board information */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_OF_LIBFDT + +/* Size of malloc() pool */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512 << 10)) + +/* Hardware drivers */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +/* select serial console configuration */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +/* MMC */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* TWL4030 */ +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED + +/* Board NAND Info */ +#define CONFIG_SYS_NO_FLASH /* no NOR flash */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:" \ + "512k(u-boot-spl)," \ + "1920k(u-boot)," \ + "128k(u-boot-env)," \ + "4m(kernel)," \ + "-(fs)" + +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ +#define CONFIG_CMD_UBI /* UBIFS commands */ + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +/* needed for ubi */ +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS + +/* Environment information */ +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "vram=12M\0" \ + "lcdmode=800x600\0" \ + "defaultdisplay=lcd\0" \ + "kernelopts=rw rootwait\0" \ + "commonargs=" \ + "setenv bootargs console=${console} " \ + "vram=${vram} " \ + "omapfb.mode=lcd:${lcdmode} " \ + "omapdss.def_disp=${defaultdisplay}\0" \ + "mmcargs=" \ + "run commonargs; " \ + "setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 " \ + "${kernelopts}\0" \ + "nandargs=" \ + "run commonargs; " \ + "setenv bootargs ${bootargs} " \ + "omapfb.mode=lcd:${lcdmode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=ubi0:rootfs " \ + "rootfstype=ubifs " \ + "${kernelopts}\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + "autoboot=if mmc init 0; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi\0" + + +#define CONFIG_BOOTCOMMAND "run autoboot" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "OMAP3 Tricorder # " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + 0x01000000) /* 16MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* The stack sizes are set up in start.S using the settings below */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* NAND and environment organization */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* SRAM config */ +#define CONFIG_SYS_SRAM_START 0x40200000 +#define CONFIG_SYS_SRAM_SIZE 0x10000 + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/tt01.h b/include/configs/tt01.h index 7e293c676c..35d2bd820f 100644 --- a/include/configs/tt01.h +++ b/include/configs/tt01.h @@ -180,6 +180,11 @@ #define CONFIG_SMC911X_BASE (CS4_BASE+0x200000) #define CONFIG_SMC911X_16_BIT +/* mmc driver */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXC_MMC +#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR /* * Command definition */ @@ -229,6 +234,13 @@ #define CONFIG_CMDLINE_EDITING +/* MMC boot support */ +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + #define CONFIG_NAND_MXC #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/mc13783.h b/include/mc13783.h new file mode 100644 index 0000000000..5e41c3ee9a --- /dev/null +++ b/include/mc13783.h @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2011 + * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __MC13783_H__ +#define __MC13783_H__ + +/* REG_MODE_0 */ +#define VAUDIOEN (1 << 0) +#define VAUDIOSTBY (1 << 1) +#define VAUDIOMODE (1 << 2) +#define VIOHIEN (1 << 3) +#define VIOHISTBY (1 << 4) +#define VIOHIMODE (1 << 5) +#define VIOLOEN (1 << 6) +#define VIOLOSTBY (1 << 7) +#define VIOLOMODE (1 << 8) +#define VDIGEN (1 << 9) +#define VDIGSTBY (1 << 10) +#define VDIGMODE (1 << 11) +#define VGENEN (1 << 12) +#define VGENSTBY (1 << 13) +#define VGENMODE (1 << 14) +#define VRFDIGEN (1 << 15) +#define VRFDIGSTBY (1 << 16) +#define VRFDIGMODE (1 << 17) +#define VRFREFEN (1 << 18) +#define VRFREFSTBY (1 << 19) +#define VRFREFMODE (1 << 20) +#define VRFCPEN (1 << 21) +#define VRFCPSTBY (1 << 22) +#define VRFCPMODE (1 << 23) + +/* REG_MODE_1 */ +#define VSIMEN (1 << 0) +#define VSIMSTBY (1 << 1) +#define VSIMMODE (1 << 2) +#define VESIMEN (1 << 3) +#define VESIMSTBY (1 << 4) +#define VESIMMODE (1 << 5) +#define VCAMEN (1 << 6) +#define VCAMSTBY (1 << 7) +#define VCAMMODE (1 << 8) +#define VRFBGEN (1 << 9) +#define VRFBGSTBY (1 << 10) +#define VVIBEN (1 << 11) +#define VRF1EN (1 << 12) +#define VRF1STBY (1 << 13) +#define VRF1MODE (1 << 14) +#define VRF2EN (1 << 15) +#define VRF2STBY (1 << 16) +#define VRF2MODE (1 << 17) +#define VMMC1EN (1 << 18) +#define VMMC1STBY (1 << 19) +#define VMMC1MODE (1 << 20) +#define VMMC2EN (1 << 21) +#define VMMC2STBY (1 << 22) +#define VMMC2MODE (1 << 23) + +#endif diff --git a/include/menu.h b/include/menu.h index cf14a9cca3..7af5fdb0ed 100644 --- a/include/menu.h +++ b/include/menu.h @@ -26,5 +26,9 @@ int menu_default_set(struct menu *m, char *item_key); int menu_get_choice(struct menu *m, void **choice); int menu_item_add(struct menu *m, char *item_key, void *item_data); int menu_destroy(struct menu *m); +void menu_display_statusline(struct menu *m); +#if defined(CONFIG_MENU_SHOW) +int menu_show(int bootdelay); +#endif #endif /* __MENU_H__ */ diff --git a/include/usb/ulpi.h b/include/usb/ulpi.h index 802f077be4..4a23fd2af2 100644 --- a/include/usb/ulpi.h +++ b/include/usb/ulpi.h @@ -28,12 +28,23 @@ #endif /* + * ulpi view port address and + * Port_number that can be passed. + * Any additional data to be passed can + * be extended from this structure + */ +struct ulpi_viewport { + u32 viewport_addr; + u32 port_num; +}; + +/* * Initialize the ULPI transciever and check the interface integrity. - * @ulpi_viewport - the address of the ULPI viewport register. + * @ulpi_vp - structure containing ULPI viewport data * * returns 0 on success, ULPI_ERROR on failure. */ -int ulpi_init(u32 ulpi_viewport); +int ulpi_init(struct ulpi_viewport *ulpi_vp); /* * Select transceiver speed. @@ -41,7 +52,7 @@ int ulpi_init(u32 ulpi_viewport); * ULPI_FC_LOW_SPEED, ULPI_FC_FS4LS * returns 0 on success, ULPI_ERROR on failure. */ -int ulpi_select_transceiver(u32 ulpi_viewport, unsigned speed); +int ulpi_select_transceiver(struct ulpi_viewport *ulpi_vp, unsigned speed); /* * Enable/disable VBUS. @@ -50,14 +61,15 @@ int ulpi_select_transceiver(u32 ulpi_viewport, unsigned speed); * * returns 0 on success, ULPI_ERROR on failure. */ -int ulpi_enable_vbus(u32 ulpi_viewport, int on, int ext_power, int ext_ind); +int ulpi_enable_vbus(struct ulpi_viewport *ulpi_vp, + int on, int ext_power, int ext_ind); /* * Enable/disable pull-down resistors on D+ and D- USB lines. * * returns 0 on success, ULPI_ERROR on failure. */ -int ulpi_set_pd(u32 ulpi_viewport, int enable); +int ulpi_set_pd(struct ulpi_viewport *ulpi_vp, int enable); /* * Select OpMode. @@ -66,7 +78,7 @@ int ulpi_set_pd(u32 ulpi_viewport, int enable); * * returns 0 on success, ULPI_ERROR on failure. */ -int ulpi_opmode_sel(u32 ulpi_viewport, unsigned opmode); +int ulpi_opmode_sel(struct ulpi_viewport *ulpi_vp, unsigned opmode); /* * Switch to Serial Mode. @@ -78,7 +90,7 @@ int ulpi_opmode_sel(u32 ulpi_viewport, unsigned opmode); * Switches immediately to Serial Mode. * To return from Serial Mode, STP line needs to be asserted. */ -int ulpi_serial_mode_enable(u32 ulpi_viewport, unsigned smode); +int ulpi_serial_mode_enable(struct ulpi_viewport *ulpi_vp, unsigned smode); /* * Put PHY into low power mode. @@ -89,14 +101,14 @@ int ulpi_serial_mode_enable(u32 ulpi_viewport, unsigned smode); * STP line must be driven low to keep the PHY in suspend. * To resume the PHY, STP line needs to be asserted. */ -int ulpi_suspend(u32 ulpi_viewport); +int ulpi_suspend(struct ulpi_viewport *ulpi_vp); /* * Reset the transceiver. ULPI interface and registers are not affected. * * returns 0 on success, ULPI_ERROR on failure. */ -int ulpi_reset(u32 ulpi_viewport); +int ulpi_reset(struct ulpi_viewport *ulpi_vp); /* ULPI access methods below must be implemented for each ULPI viewport. */ @@ -108,7 +120,7 @@ int ulpi_reset(u32 ulpi_viewport); * * returns 0 on success, ULPI_ERROR on failure. */ -int ulpi_write(u32 ulpi_viewport, u8 *reg, u32 value); +int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value); /* * Read the ULPI PHY register content via the viewport. @@ -116,14 +128,14 @@ int ulpi_write(u32 ulpi_viewport, u8 *reg, u32 value); * * returns register content on success, ULPI_ERROR on failure. */ -u32 ulpi_read(u32 ulpi_viewport, u8 *reg); +u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg); /* * Wait for the reset to complete. * The Link must not attempt to access the PHY until the reset has * completed and DIR line is de-asserted. */ -int ulpi_reset_wait(u32 ulpi_viewport); +int ulpi_reset_wait(struct ulpi_viewport *ulpi_vp); /* Access Extended Register Set (indicator) */ #define ACCESS_EXT_REGS_OFFSET 0x2f /* read-write */ |