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* mmc: add nexell driverStefan Bosch2020-07-293-0/+246
| | | | | | | | | | | | | | Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - driver changed to DM. - pinctrl-driver/dt is used now instead of configuring the mmc I/O-pins in the mmc-driver. - nexell_dwmmc_ofdata_to_platdata() reworked, i.e. valid default values are used now (where possible) and the appropriate if-blocks have been removed. - new dt-property "mmcboost" is used now instead of "CONFIG_BOOST_MMC" which was not defined anywhere. Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
* i2c: add nexell driverStefan Bosch2020-07-294-0/+664
| | | | | | | | | | | | | | | | | Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - i2c/nx_i2c.c: Some adaptions mainly because of changes in "struct udevice". - several Bugfixes in nx_i2c.c. - the driver has been for s5p6818 only. Code extended appropriately in order s5p4418 is also working. - "probe_chip" added. - pinctrl-driver/dt is used instead of configuring the i2c I/O-pins in the i2c-driver. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). - livetree API (dev_read_...) is used instead of fdt one (fdt...). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
* gpio: add nexell driverStefan Bosch2020-07-293-0/+260
| | | | | | | Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - livetree API (dev_read_...) is used instead of fdt one (fdt...). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
* arm: add mach-nexell (all files except header files)Stefan Bosch2020-07-2913-0/+1999
| | | | | | | | | | | | | | | | | | | Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - SPL not supported yet --> no spl-directory in arch/arm/mach-nexell. Appropriate line in Makefile removed. - clock.c: 'section(".data")' added to declaration of clk_periphs[] and core_hz. - Kconfig: Changes to have a structure like in mach-bcm283x/Kconfig, e.g. "config ..." entries moved from other Kconfig. - timer.c: 'section(".data")' added to declaration of timestamp and lastdec. - arch/arm/mach-nexell/serial.c removed because this is for the UARTs of the S5P6818 SoC which is not supported yet. S5P4418 UARTs are different, here the (existing) PL011-code is used. - '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where possible (and similar). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
* arm: add mach-nexell (header files)Stefan Bosch2020-07-2912-0/+1624
| | | | | | | | | Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - DM_VIDEO support (display_dev.h). - boot0.h added, handles NSIH --> tools/nexell obsolete. - gpio.h: Include-path to errno.h changed. Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
* arm: qemu: override flash accessors to use virtualizable instructionsArd Biesheuvel2020-07-292-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some instructions in the ARM ISA have multiple output registers, such as ldrd/ldp (load pair), where two registers are loaded from memory, but also ldr with indexing, where the memory base register is incremented as well when the value is loaded to the destination register. MMIO emulation under KVM is based on using the architecturally defined syndrome information that is provided when an exception is taken to the hypervisor. This syndrome information describes whether the instruction that triggered the exception is a load or a store, what the faulting address was, and which register was the destination register. This syndrome information can only describe one destination register, and when the trapping instruction is one with multiple outputs, KVM throws an error like kvm [615929]: Data abort outside memslots with no valid syndrome info on the host and kills the QEMU process with the following error: U-Boot 2020.07-rc3-00208-g88bd5b179360-dirty (Jun 06 2020 - 11:59:22 +0200) DRAM: 1 GiB Flash: error: kvm run failed Function not implemented R00=00000001 R01=00000040 R02=7ee0ce20 R03=00000000 R04=7ffd9eec R05=00000004 R06=7ffda3f8 R07=00000055 R08=7ffd9eec R09=7ef0ded0 R10=7ee0ce20 R11=00000000 R12=00000004 R13=7ee0cdf8 R14=00000000 R15=7ff72d08 PSR=200001d3 --C- A svc32 QEMU: Terminated This means that, in order to run U-Boot in QEMU under KVM, we need to avoid such instructions when accessing emulated devices. For the flash in particular, which is a hybrid between a ROM (backed by a read-only KVM memslot) when in array mode, and an emulated MMIO device (when in write mode), we need to take care to only use instructions that KVM can deal with when they trap. So override the flash read accessors that are used when running on QEMU under KVM. Note that the the 64-bit wide read and write accessors have been omitted: they are never used when running under QEMU given that it does not emulate CFI flash that supports it. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* arm: qemu: disable the EFI workaround for older GRUBArd Biesheuvel2020-07-291-0/+1
| | | | | | | | | | | | | | | | | | | The QEMU/mach-virt targeted port of u-boot currently only runs on QEMU under TCG emulation, which does not model the caches at all, and so no users can exist that are relying on the GRUB hack for EFI boot. We will shortly enable support for running under KVM, but the GRUB hack (which disables all caches without doing cache cleaning by VA during ExitBootServices()) is likely to cause more problems than it solves, given that KVM hosts require correct maintenance if they incorporate non-architected system caches. So let's disable the GRUB hack by default on the QEMU/mach-virt port. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* arm: qemu: implement enable_caches()Ard Biesheuvel2020-07-291-0/+7
| | | | | | | | | | Add an override for enable_caches to enable the I and D caches, along with the cached 1:1 mapping of all of DRAM. This is needed for running U-Boot under virtualization with QEMU/kvm. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* arm: qemu: enable LPAE on 32-bitArd Biesheuvel2020-07-291-0/+1
| | | | | | | | | | | | | | | | | | | | | QEMU's mach-virt machine only supports selecting CPU models that implement the virtualization extensions, and are therefore guaranteed to support LPAE as well. Initially, QEMU would not allow emulating these CPUs running in HYP mode (or EL2, for AArch64), but today, it also contains a complete implementation of the virtualization extensions themselves. This means we could be running U-Boot in HYP mode, in which case the LPAE long descriptor page table format is the only format that is supported. If we are not running in HYP mode, we can use either. So let's enable CONFIG_ARMV7_LPAE for qemu_arm_defconfig so that we get the best support for running with the MMU and caches enabled at any privilege level. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGHArd Biesheuvel2020-07-291-4/+19
| | | | | | | | | | | | | The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* msm_gpio: Add support for Qualcomm IPQ40xxRobert Marko2020-07-292-1/+3
| | | | | | | | | | Snapdragon SoCs and IPQ40xx use common TLMM IP, so existing driver supports IPQ40xx as well. So lets simply add a compatible for IPQ40xx. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
* msm_serial: Read bit rate register value from DTRobert Marko2020-07-292-1/+9
| | | | | | | | | IPQ40xx and currently supported Snapdragon boards don't use the same one so enable reading it from DT, if no DT property is found default value is the same as the previous define. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
* arm: Add support for Qualcomm IPQ40xx familyRobert Marko2020-07-2911-0/+412
| | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces initial support for the popular Qualcomm IPQ40x8 and IPQ40x9 WiSoC series. IPQ40xx series have 4x Cortex A7 ARM-v7A cores. Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029. IPQ40x8 and IPQ40x9 use the same cores, but differ in addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8) and supported peripherals (IPQ40x8 lacks RGMII, LCD controller and EMMC/SDHCI controllers). IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only by their rated temperatures rates with IPQ402X models being rated for wider temperature ranges. Initially this supports: * Simple clock driver (Only for UART1 now, will be extended) * Pinctrl driver (Supports UARTX and GPIO now, will be extended) * GPIOs already supported by msm_gpio driver with updates * UARTs already supported by serial_msm driver with updates Further peripherals will come in later patches. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* pinctrl: mediatek: add PUPD/R0/R1 support for MT7623David Woodhouse2020-07-293-5/+146
| | | | | | | | | The pins for the MMC controller weren't being set up correctly because the pinctrl driver only sets the GPIO pullup/pulldown config and doesn't handle the special cases with PUPD/R0/R1 control. Signed-off-by: David Woodhouse <dwmw2@infradead.org> Tested-by: Frank Wunderlich <frank-w@public-files.de>
* arm: dts: mediatek: enable sgmii mode and mt7531 switch for mt7629MarkLee2020-07-281-6/+8
| | | | | | | This patch enable sgmii mode and mt7531 switch support in mt7629 ethernet dts node Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
* eth: mtk-eth: enable mt7629 sgmii mode support in mediatek eth driverMarkLee2020-07-282-1/+3
| | | | | | | | | The sgmii mode init flow is almost the same for all mediatek SoC, the only difference is the register offset(SGMSYS_GEN2_SPEED) is 0x2028 in the old chip(mt7622) but changed to 0x128 for the newer chip(mt7629 and the following chips). Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
* Merge branch '2020-07-28-Kconfig-migrations'Tom Rini2020-07-281057-581/+1115
|\ | | | | | | - Migration of more symbols to Kconfig
| * configs: migrate CONFIG_SPL_LOAD_FIT_ADDRESS to defconfigsWIP/20202-07-28-Kconfig-migrationsPeng Fan2020-07-2827-20/+18
| | | | | | | | | | | | | | | | | | | | Done with: ./tools/moveconfig.py -S SPL_LOAD_FIT_ADDRESS ./tools/moveconfig.py -S SPL_LOAD_FIT_ADDRESS -H Signed-off-by: Peng Fan <peng.fan@nxp.com> [trini: A few more migrations] Signed-off-by: Tom Rini <trini@konsulko.com>
| * Kconfig: add SPL_LOAD_FIT_ADDRESSPeng Fan2020-07-281-0/+8
| | | | | | | | | | | | Add SPL_LOAD_FIT_ADDRESS to make user could add it in defconfig Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * Convert CONFIG_SYS_MMCSD_FS_BOOT_PARTITION to KconfigAdam Ford2020-07-2848-50/+7
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_MMCSD_FS_BOOT_PARTITION Signed-off-by: Adam Ford <aford173@gmail.com>
| * configs: Remove dead CONFIG optionsAdam Ford2020-07-288-8/+0
| | | | | | | | | | | | | | | | | | | | BOOTP_DEFAULT is defined in several boards, but this config option is never checked or used. This patch removes this config option from config files and the whitelist.txt Signed-off-by: Adam Ford <aford173@gmail.com>
| * Convert CONFIG_BOOTP_SEND_HOSTNAME to KconfigAdam Ford2020-07-2896-33/+81
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_BOOTP_SEND_HOSTNAME Signed-off-by: Adam Ford <aford173@gmail.com>
| * Convert CONFIG_DRIVER_TI_EMAC_USE_RMII to KconfigAdam Ford2020-07-286-4/+7
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_DRIVER_TI_EMAC_USE_RMII Signed-off-by: Adam Ford <aford173@gmail.com>
| * Convert CONFIG_SPL_NAND_BASE et al to KconfigAdam Ford2020-07-2885-40/+69
| | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_NAND_BASE CONFIG_SPL_NAND_IDENT Signed-off-by: Adam Ford <aford173@gmail.com>
| * Convert CONFIG_SPL_NAND_DRIVERS et al to KconfigAdam Ford2020-07-2887-72/+142
| | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SPL_NAND_DRIVERS CONFIG_SPL_NAND_ECC CONFIG_SPL_NAND_SIMPLE Signed-off-by: Adam Ford <aford173@gmail.com>
| * Convert CONFIG_ENV_OVERWRITE to KconfigAdam Ford2020-07-28979-354/+783
|/ | | | | | | | | This converts the following to Kconfig: CONFIG_ENV_OVERWRITE Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rerun migration, remove some comments] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch '2020-07-28-update-azure-tests'WIP/28Jul2020Tom Rini2020-07-281-16/+6
|\ | | | | | | - Update Azure to fix some recent issues with Windows host tool builds
| * azure: Switch to use the MSYS2 official installer as the CI baseBin Meng2020-07-281-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent CI failures were seen [1] when building MSYS2 Windows host tools. The error messages are something like: downloading mingw32.db... downloading mingw32.db.sig... error: mingw32: key "4A6129F4E4B84AE46ED7F635628F528CF3053E04" is unknown error: mingw32: signature from "David Macek <david.macek.0@gmail.com>" is unknown trust error: failed to update mingw32 (invalid or corrupted database (PGP signature)) Per the MSYS2 official news [2], this was caused by a packager switch and several solutions were suggested, e.g.: a new package of msys2-keyring and a new msys2 installer that includes them are released. However right now we have been using the MSYS2 github CI base repo [3] for the MSYS2 build in U-Boot, but per the project information on the github webpage, it says: "This repository is unused/deprecated and will be remove after 2021-01-01". Since it is unmaintained it's unlikely the new PGP keys will be included in the git repo, and the only choice is to switch to use the MSYS2 official installer as the CI base instead. [1] https://dev.azure.com/u-boot/u-boot/_build/results?buildId=975 [2] https://www.msys2.org/news/#2020-06-29-new-packagers [3] https://github.com/msys2/msys2-ci-base Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * azure: Add the missing build dependency for MSYS2 buildBin Meng2020-07-281-1/+1
| | | | | | | | | | | | | | | | | | Package 'flex' is needed when building the U-Boot host tool, but is currently missing in the build dependency in the CI pipeline. This is to prepare switching to an installer based CI build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * azure: Drop 32-bit MSYS2 buildBin Meng2020-07-281-12/+4
| | | | | | | | | | | | | | | | | | As of 2020-05-17, 32-bit MSYS2 is no longer actively supported by the upstream [1]. Let's drop the 32-bit Windows host tool build. [1] https://www.msys2.org/news/#2020-05-17-32-bit-msys2-no-longer-actively-supported Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * azure: Use a login shell everywhere for MSYS2 buildBin Meng2020-07-281-5/+2
| | | | | | | | | | | | | | | | | | This simplifies things a bit to just use a login shell everywhere. This keeps in sync with MSYS2 upstream commit: 9d11b7f0aa93 ("azure-pipelines: simplify things a bit"). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | configs: Resync with savedefconfigTom Rini2020-07-281005-1309/+1049
|/ | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* Prepare v2020.10-rc1v2020.10-rc1Tom Rini2020-07-271-2/+2
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'u-boot-amlogic-20200727' of ↵Tom Rini2020-07-272-4/+50
|\ | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Handle errors in Meson serial driver - Enable HDMI, keyboard and ADC for Odroid-C2
| * configs: odroid-c2: update for HDMI output, ADC & USB keyboardAnand Moon2020-07-271-0/+11
| | | | | | | | | | | | | | | | | | Enable options to permit HDMI output on Odroid-C2 GXBB boards. Enable VPU Power Domain. Enable ADC and USB_KERBOARD. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
| * serial: meson: handle RX errorsNeil Armstrong2020-07-271-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This checks and handles RX errors on the Amlogic UART controller after experiencing errors on the Khadas VIM3 & VIM3L when UART AO A lines are not connected. When the RX line is not connected, the first byte is erroneous and breaks the U-Boot autoboot, breaking automatic boot. This checks and drops any erroneous RX byte on pending and getc callbacks to avoid returning true to pending when an error byte is in the FIFO. Fixes: bfcef28ae4 ("arm: add initial support for Amlogic Meson and ODROID-C2") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Guillaume La Roque <glaroque@baylibre.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/27Jul2020Tom Rini2020-07-27181-1084/+2317
|\ \ | | | | | | | | | | | | | | | | | | | | | - Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a - lx2-watchdog support - layerscape: pci-endpoint support, spin table relocation fixes and cleanups - fsl-crypto: RNG support and bug fixes
| * | configs: ls2088a: Restore CONFIG_ENV_ADDR to IFC-NORKuldeep Singh2020-07-271-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Restore CONFIG_ENV_ADDR value to fix boot hang with IFC-NOR which is default boot source. Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: dts: ls1028a: Add dspi flash device node to qdsZhao Qiang2020-07-271-0/+74
| | | | | | | | | | | | | | | | | | | | | Add dspi flash device node to fsl-ls1028a-qds.dtsi Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | configs: lx2160a: Enable Watchdog supportZhao Qiang2020-07-272-0/+6
| | | | | | | | | | | | | | | | | | | | | Enable support to compile SBSA driver. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm64: lx2160a: dts: Add watchdog nodeZhao Qiang2020-07-271-0/+7
| | | | | | | | | | | | | | | | | | | | | Add watchdog node which is sbsa into lx2160a dtsi Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | Watchdog: introduce ARM SBSA watchdog driverZhao Qiang2020-07-274-0/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Server Base System Architecture (SBSA) specification, the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0) is for alerting the system by interrupt, the second one (WS1) is a real hardware reset. More details about the hardware specification of this device: ARM DEN0029B - Server Base System Architecture (SBSA) This driver can operate ARM SBSA Generic Watchdog as a single stage In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: Add specific config entry for RC and EP mode driverHou Zhiqiang2020-07-27106-117/+155
| | | | | | | | | | | | | | | | | | | | | | | | Add Root Complex and Endpoint mode specific config entries, such that it's feasible to enable the RC and/or EP mode driver indepently. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci_ep: layerscape: Add the PCIe EP mode support for lx2160a-v2Xiaowei Bao2020-07-272-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | Add the PCIe EP mode support for lx2160a-v2 platform. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: layerscape: Modify the ls_pcie_dump_atu functionXiaowei Bao2020-07-274-14/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the ls_pcie_dump_atu function, make it can print the INBOUND windows registers. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci_ep: layerscape: Add the SRIOV VFs of PF supportXiaowei Bao2020-07-273-13/+42
| | | | | | | | | | | | | | | | | | | | | | | | Add the INBOUND configuration for VFs of PF. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci_ep: layerscape: Add Support for ls2085a and ls2080a EP modeXiaowei Bao2020-07-271-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the ls2085a and ls2080a use different way to set the BAR size, so add the BAR size init code here. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci_ep: layerscape: Add the workaround for errata A-009460Xiaowei Bao2020-07-271-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VF_BARn_REG register's Prefetchable and Type bit fields are overwritten by a write to VF's BAR Mask register. workaround: Before writing to the VF_BARn_MASK_REG register, write 0b to the PCIE_MISC_CONTROL_1_OFF register. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pcie_ep: layerscape: Add the multiple function supportXiaowei Bao2020-07-273-48/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the multiple function support for Layerscape platform, some PEXs of Layerscaple platform have more than one PF. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | armv8: dts: ls1046a: Add the PCIe EP nodeXiaowei Bao2020-07-271-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | Add the PCIe EP node for ls1046a. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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