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* dm: sandbox: Add a simple driver to test of-platdataSimon Glass2016-07-142-0/+58
| | | | | | | | Add a driver which uses of-platdata to obtain its platform data. This can be used to test the feature in sandbox. It displays the contents of its platform data. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: syscon: Add support for of-platdataSimon Glass2016-07-142-0/+24
| | | | | | | Provide a new function which can cope with obtaining information from of-platdata instead of the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: regmap: Add a dummy implementation for of-platdataSimon Glass2016-07-142-0/+12
| | | | | | | Add a placeholder for now so that this code will compile. It currently does nothing. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Don't use device tree with of-platdataSimon Glass2016-07-143-4/+4
| | | | | | | When CONFIG_SPL_OF_PLATDATA is enabled we should not access the device tree. Remove all references to this in the core driver-model code. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Makefile: Build of-platdata before SPLSimon Glass2016-07-141-1/+2
| | | | | | | Since SPL needs the of-platdata structures, build these before starting to build any SPL components. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spl: Don't set up device tree with of-platdataSimon Glass2016-07-141-1/+1
| | | | | | When this feature is enabled, we should not access the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add a test device that uses of-platdataSimon Glass2016-07-143-0/+50
| | | | | | | | | | Start up the test devices. These print out of-platdata contents, providing a check that the of-platdata feature is working correctly. The device-tree changes are made to sandbox.dts rather than test.dts. since the former controls the of-platdata generation. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add a new sandbox_spl boardSimon Glass2016-07-145-1/+237
| | | | | | | | | | | | It is useful to be able to build SPL for sandbox. It provides additional build coverage and allows SPL features to be tested in sandbox. However it does not need worthwhile to always create an SPL build. It nearly doubles the build time and the feature is (so far) seldom used. So for now, create a separate build target for sandbox SPL. This allows experimentation with this new feature without impacting existing workflows. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: serial: Don't sync video in SPLSimon Glass2016-07-141-0/+2
| | | | | | | SPL does not support an LCD display so there is no need to sync the video when there is serial output. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Don't use IDE and iotrace in SPLSimon Glass2016-07-141-0/+4
| | | | | | These functions are not supported in SPL, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add basic SPL implementationSimon Glass2016-07-143-0/+75
| | | | | | | Add an sandbox implementation for the generic SPL framework. This supports locating and running U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Don't include the main loop in SPLSimon Glass2016-07-141-0/+2
| | | | | | | SPL does not have a command interface so we should not include the main loop code. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Don't use PCI in SPLSimon Glass2016-07-142-1/+3
| | | | | | PCI is not supported in SPL for sandbox, so avoid using it. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add some missing headers in cpu.cSimon Glass2016-07-141-0/+2
| | | | | | These headers are needed in case they are not transitively included. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Correct header file order in cpu.cSimon Glass2016-07-141-1/+1
| | | | | | The dm/ file should go at the end. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Support building an SPL imageSimon Glass2016-07-141-0/+5
| | | | | | | When building an SPL image, override the link flags so that it uses the system libraries. This is similar to the way the non-SPL image is built. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Allow chaining from SPL to U-Boot properSimon Glass2016-07-142-0/+76
| | | | | | | | SPL is expected to load and run U-Boot. This needs to work with sandbox also. Provide a function to locate the U-Boot image, and another to start it. This allows SPL to function on sandbox as it does on other archs. Signed-off-by: Simon Glass <sjg@chromium.org>
* Makefile: Allow the SPL final link rule to be overriddenSimon Glass2016-07-141-2/+4
| | | | | | | | | | Overriding the final link rule is possible with U-Boot proper. It us used to create a sandbox image links with host libraries. To build a sandbox SPL image we need the same feature for SPL. To support this, update the SPL link rule so sandbox can override it. Signed-off-by: Simon Glass <sjg@chromium.org>
* spl: Drop include of i2c.hSimon Glass2016-07-141-1/+0
| | | | | | This file does not appear to use I2C, so drop this include. Signed-off-by: Simon Glass <sjg@chromium.org>
* README: Remove CONFIG_SYS_MALLOC_F_LEN commentSimon Glass2016-07-141-3/+0
| | | | | | | This option is now widely available, so remove the comment that it is only available on ARM and sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Don't print a warning for CONFIG_I2C_COMPATSimon Glass2016-07-141-1/+1
| | | | | | | | | | | Sandbox includes this code to provide build coverage. While we retain this feature we should have sandbox build it. Sandbox does not in fact use the I2C compatibility mode. Showing a warning for sandbox is just confusing, since no conversion is expected. Drop the warning for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
* Revert "armv8: Enable CPUECTLR.SMPEN for coherency"Tom Rini2016-07-141-8/+0
| | | | | | | | | Upon further review this breaks most other platforms as we need to check what core we're running on before touching it at all. This reverts commit d73718f3236c520a92efa401084c658e6cc067f3. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-07-1235-23/+773
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| * x86: link: Correct a failure in DRAM initSimon Glass2016-07-121-0/+5
| | | | | | | | | | | | | | | | | | | | With the change to set up pinctrl after relocation, link fails to boot. Add a special case in the link code to handle this. Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r()) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add Advantech SOM-DB5800/SOM-6867 supportGeorge McCollister2016-07-1214-1/+524
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Advantech SOM-DB5800 with the SOM-6867 installed. This is very similar to conga-qeval20-qa3-e3845 in that there is a reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867) installed. Currently supported: - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on SOM-DB5800. - 4x USB 2.0 (EHCI) - Video - SATA - Ethernet - PCIe - Realtek ALC892 HD Audio Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO HDA_SDI0 is set in DT to enable HD Audio codec. Pin defaults for codec pin complexs are not changed. Not supported: - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500) - USB 3.0 (XHCI) - TPM Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: acpi: Hide internal UART per GNVS settingBin Meng2016-07-121-11/+8
| | | | | | | | | | | | | | | | | | | | If global NVS says internal UART is not enabled, hide it in the ASL code so that OS won't see it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Pack global NVS into ACPI tableBin Meng2016-07-125-2/+32
| | | | | | | | | | | | | | | | | | | | Now that platform-specific ACPI global NVS is added, pack it into ACPI table and get its address fixed up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Introduce ACPI global NVSBin Meng2016-07-123-0/+41
| | | | | | | | | | | | | | | | This introduces quark-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Introduce ACPI global NVSBin Meng2016-07-124-0/+81
| | | | | | | | | | | | | | | | | | | | This introduces baytrail-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: conga-qeval20-qa3: Add support for internal UARTStefan Roese2016-07-122-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to enable and use the internal BayTrail UART instead of the one integrated in the Super IO Winbond chip. For this, a 2nd defconfig file is added. This is useful for tests done for the congatec SoM used on baseboards without such a Super IO chip. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Wrap setup_internal_uart() call with CONFIG_INTERNAL_UARTBin Meng2016-07-121-1/+1
| | | | | | | | | | | | | | | | | | | | For any FSP-enabled boards that want to enable debug UART support, setup_internal_uart() will be called, but this API is only available on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Introduce a Kconfig option for the internal UARTBin Meng2016-07-123-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | There are quite a number of BayTrail boards that uses an external SuperIO chipset to provide the legacy UART. For such cases, it's better to have a Kconfig option to enable the internal UART. So far BayleyBay and MinnowMax boards are using internal UART as the U-Boot console, enable this on these two boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * pci: Add board_ prefix to should_load_oprom() and make it weakBin Meng2016-07-121-2/+2
| | | | | | | | | | | | | | | | | | For consistency with board_should_run_oprom(), do the same to should_load_oprom(). Board support codes can provide this one to override the default weak one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * pci: Make load_oprom and run_oprom independentBin Meng2016-07-121-4/+1
| | | | | | | | | | | | | | | | | | At present should_load_oprom() calls board_should_run_oprom() to determine whether oprom should be loaded. But sometimes we just want to load oprom without running. Make them independent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * pci: Remove CONFIG_ALWAYS_LOAD_OPROMBin Meng2016-07-121-2/+0
| | | | | | | | | | | | | | This option is defined at nowhere. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-07-1123-117/+450
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| * | dm: spi: Read default speed and mode values from DTVignesh R2016-07-093-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of DT boot, don't read default speed and mode for SPI from CONFIG_*, instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHzVignesh R2016-07-092-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better throughput. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2g_evm_defconfig: Enable Cadence QSPI controllerVignesh R2016-07-092-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable Cadence QSPI controller support to use QSPI on K2G SoC. Also enable Spansion flash support to access s25fl512s flash present on K2G QSPI bus. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: K2G: Add support for QSPI controllerVignesh R2016-07-092-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | K2G SoC has a Cadence QSPI controller to communicate with NOR flash devices. Add DT nodes to support the same. Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor flash slave node for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: cadence_quadspi: Enable QUAD mode based on DT dataVignesh R2016-07-093-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: cadence_qspi_apb: Support 32 bit AHB addressVignesh R2016-07-091-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AHB address can be as long as 32 bit, hence remove the CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT and read as u32 value, it anyway does not make sense to mask upper bits. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2g_evm_defconfig: enable SPI driver modelVignesh R2016-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI and SPI Flash driver model as K2G SPI controller driver supports driver model. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2g: add support for Davinci SPI controllerVignesh R2016-07-092-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | K2G SoC has 4 SPI instances that are compatible with davinci_spi controller(present on previous generation of Keystone2 devices). Add DT nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on SPI-1. Add DT bindings for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2l_evm_defconfig: enable SPI driver modelVignesh R2016-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI and SPI Flash driver model as K2L SPI controller driver supports driver model. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2l: Enable Davinci SPI controllerVignesh R2016-07-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2e_evm_defconfig: enable SPI driver modelVignesh R2016-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI and SPI Flash driver model as K2E SPI controller driver supports driver model. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2e: Enable Davinci SPI controllerVignesh R2016-07-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2hk_evm_defconfig: enable SPI driver modelVignesh R2016-07-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI and SPI Flash driver model as K2HK SPI controller driver supports driver model. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2hk: Enable Davinci SPI controllerVignesh R2016-07-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
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