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* ARM: DT: stm32f7: add qspi pin contol nodeVikas Manocha2017-03-173-43/+12
| | | | | | | It also removes the qspi pin configuration done during the board initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* ARM: DT: stm32f7: add ethernet pin contol nodeVikas Manocha2017-03-173-32/+15
| | | | | | | It also removes the ethernet pin configuration done during the board initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* ARM: DT: stm32f7: add pin control node for serial port pinsVikas Manocha2017-03-173-24/+20
| | | | | | And remove the uart pin configuration from board initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* ARM: DT: stm32f7: add pin control device nodeVikas Manocha2017-03-171-1/+8
| | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* PINCTRL: stm32f7: add pin control driverVikas Manocha2017-03-175-0/+263
| | | | | | | | | This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* stm32f7: clk: remove usart1 clock enable from board initVikas Manocha2017-03-172-4/+0
| | | | | | | Before clock driver availability it was required to enable usart1 clock for serial init but now with clock driver is taking care of usart1 clock. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* ARM: DT: stm32f7: add usart1 & clock device tree nodesVikas Manocha2017-03-172-0/+32
| | | | | | | Also created alias for usart1 and specified oscillator clock for stm32f7 discovery board. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* stm32f7: serial: use clock driver to enable clockVikas Manocha2017-03-171-0/+18
| | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: stm32f7: add clock driver for stm32f7 familyVikas Manocha2017-03-176-6/+157
| | | | | | | | add basic clock driver support for stm32f7 to enable clocks required by the peripherals. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* serial: stm32f7: add device tree supportVikas Manocha2017-03-172-10/+24
| | | | | | | | This patch adds device tree support for stm32f7 serial driver & removes serial platform data structure. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: use common instructions applicable to armv7m & other arm archsVikas Manocha2017-03-171-18/+7
| | | | | | | | | This patch cleans the code by using instructions allowed for armv7m as well as other Arm archs. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* arm: Update our 'ret' assembler macro slightlyTom Rini2017-03-171-4/+4
| | | | | | | | | We only support cores that do Thumb-1 or later. So we add a comment to explain this and remove the architecture test. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Mans Rullgard <mans@mansr.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* gpt: Fix uuid string formatVincent Tinelli2017-03-172-2/+2
| | | | | | | Change GPT UUID string format from UUID to GUID per specification. Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* cmd: itest: correct calculus for long formatSebastien Colleur2017-03-171-1/+2
| | | | | | | | | itest shell command doesn't work correctly in long format when doing comparaison due to wrong mask value calculus that overflow on 32 bits values. Signed-off-by: Sebastien Colleur <sebastienx.colleur@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* configs: move CMD_MD5SUM definition to defconfigsAndre Przywara2017-03-1714-17/+7
| | | | | | | | | | | | | | | Boards with an apparent need for the md5sum command had the connected config symbol defined in their board header file. Move this over to the respective defconfig files now that md5sum is configured via Kconfig. (This is a manual effort, which differs from moveconfig.py, not sure who is right here. Boards except sandbox loose the md5sum command with moveconfig.py, though it was explicitly mentioned in their config.h's) Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: migrate stih410-b2260] Signed-off-by: Tom Rini <trini@konsulko.com>
* Kconfig: define MD5 dependency for FIT supportAndre Przywara2017-03-172-1/+1
| | | | | | | | | FIT images require MD5 support to verify image checksums. So far this was expressed by defining a CPP symbol in image.h. Since MD5 is now a first class Kconfig citizen, express that in Kconfig instead. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Kconfig: introduce md5sum command selectionAndre Przywara2017-03-172-0/+18
| | | | | | | | | | So far CONFIG_MD5SUM would need to be set by a board's include file. Since the command is really generic, move it over to Kconfig to allow it to be defined by either a board's defconfig, menuconfig or some config snippet merged via mergeconfig.sh. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* kirkwood: remove get_random_hex() and MD5 dependencyAndre Przywara2017-03-172-2/+0
| | | | | | | | | | | | Commit 19a5944fcd62 ("mvgbe: remove setting of ethaddr within the driver") removed the usage of get_random_hex() from the mvgbe driver about six years ago. However the prototype of that function survived till today in some kirkwood header file. Remove that prototype and the CONFIG_MD5 dependency triggered by that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-03-1618-699/+634
|\ | | | | | | | | | | | | Xilinx changes for v2017.05 - Move to DM clk driver - Add clk support for zynq_sdhci
| * mmc: zynq: Add fdt max-frequency supportStefan Herbrechtsmeier2017-02-171-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | The maximum supported peripheral clock frequency of the zynq depends on the IO routing. The MIO and EMIO support a maximum frequency of 50 MHz respectively 25 MHz. Use the max-frequency value of the device tree to determine the maximal supported peripheral clock frequency. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * mmc: zynq: Determine base clock frequency via clock frameworkStefan Herbrechtsmeier2017-02-171-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | The zynq_sdhci controller driver use CONFIG_ZYNQ_SDHCI_MAX_FREQ as base clock frequency but this clock is not fixed and depends on the hardware configuration. Additionally the value of CONFIG_ZYNQ_SDHCI_MAX_FREQ doesn't match the real base clock frequency of SDIO_FREQ. Use the clock framework to determine the frequency at run time. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * clk: zynq: Add optional ethernet emio clock source supportStefan Herbrechtsmeier2017-02-171-0/+29
| | | | | | | | | | | | | | | | Add support for the optional ethernet emio clock source to the zynq clock framework driver. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: Move zynq to clock frameworkStefan Herbrechtsmeier2017-02-1713-651/+59
| | | | | | | | | | | | | | | | Move the zynq to clock framework and remove unused functions as well as the CONFIG_ZYNQ_PS_CLK_FREQ configuration. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * clk: zynq: Add zynq clock framework driverStefan Herbrechtsmeier2017-02-173-0/+468
| | | | | | | | | | | | | | | | | | | | | | Add a clock framework driver for the zynq platform. The driver is based on the platform zynq clock driver but reworked to use static functions instead of run-time generated objects even for unused clocks. Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the ps-clk-frequency from the device tree. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: Remove zynq_clk_get_name functionStefan Herbrechtsmeier2017-02-172-12/+1
| | | | | | | | | | | | | | | | | | The zynq_clk_get_name function is only used once inside the clock driver. Replace the function call with the one-line code. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: Move static clock names into separate arrayStefan Herbrechtsmeier2017-02-171-61/+60
| | | | | | | | | | | | | | | | | | The clock names are static and correspond to the clock id. Separate them from the dynamic filled clock array. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: Add clk framework support to zynq timerStefan Herbrechtsmeier2017-02-171-0/+25
| | | | | | | | | | | | | | | | If available use the clock framework to calculate the clock rate of the zynq timer. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq: Add clk framework support to zynq ethernet driverStefan Herbrechtsmeier2017-02-172-14/+15
| | | | | | | | | | | | | | | | | | If available use the clock framework to set the tx clock rate of the zynq ethernet controller. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq: Don't overwrite gem_rclk_ctrl with default valueStefan Herbrechtsmeier2017-02-172-18/+5
| | | | | | | | | | | | | | | | | | | | The gem[0-1]_rclk_ctrl registers control the source of the rx clock, control and data signals and configure via ps7_init function. Don't overwrite the register with the default value. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-03-1642-579/+750
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| * | LS1021ATWR: Modify u-boot size for sd secure bootVinitha Pillai2017-03-142-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raw uboot image is used in place of FIT image in secure boot. The maximum allocated size of raw u-boot bin is 1MB in memory map. Hence , CONFIG_SYS_MONITOR_LEN has been modified to 1 MB. The bootscript (BS_ADDR) and its header (BS_HDR_ADDR) offset on MMC have also been modified to accommodate the increase in uboot size. Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Reviewed-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Add vid support for LS2080AQDSPriyanka Jain2017-03-141-0/+9
| | | | | | | | | | | | | | | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Arpit Goel <arpit.goel@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Update VID supportPriyanka Jain2017-03-142-14/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like LS2088A, LS2080A differs from existing logic. -VDD voltage array is different -Registers are different -VDD calculation logic is different Add new function adjust_vdd() for LSCH3 compliant SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Arpit Goel <arpit.goel@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Updates DCFG register mapPriyanka Jain2017-03-141-19/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | Based on latest hardware documentation, update ccsr_gur structure (represents DCFG register map) Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Arpit Goel <arpit.goel@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls104xa: remove the DDR interactive debugging info from SPLHou Zhiqiang2017-03-144-0/+8
| | | | | | | | | | | | | | | | | | | | | Remove the DDR interactive debugging to reduce the size of spl image. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch2: add workaround for erratum A-010635Tang Yuantian2017-03-141-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Read DMA operations causes CRC error on armv8 chassis 2 platforms due to the erratum A-010635. In order to support sata on these platforms, ECC needs to be disabled. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: layerscape: Update early MMU for DDR after initializationYork Sun2017-03-1413-38/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | In early MMU table, DDR has to be mapped as device memory to avoid speculative access. After DDR is initialized, it needs to be updated to normal memory to allow code execution. To simplify the code, dram_init() is moved into a common file as a weak function. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: mmu: Add a function to change mapping attributesYork Sun2017-03-143-4/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: Drop early MMU for SPL buildYork Sun2017-03-141-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Early MMU improves performance especially on emulators. However, the early MMU is left enabled after the first stage of SPL boot. Instead of flushing D-cache and dealing with re-enabling MMU for the second stage U-Boot, disabling it for SPL build simplifies the process. The performance penalty is unnoticeable on the real hardware. As of now, SPL boot is not supported by existing emulators. So this should have no impact on emulators. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: layerscape: Fix the sequence of changing MMU tableYork Sun2017-03-141-11/+4
| | | | | | | | | | | | | | | | | | | | | | | | This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: layerscape: Update MMU mapping with actual DDR sizeYork Sun2017-03-141-2/+40
| | | | | | | | | | | | | | | | | | | | | Update mapping with actual DDR size. Non-existing memory should not be mapped as "normal" memory to avoid speculative access. Signed-off-by: York Sun <york.sun@nxp.com>
| * | driver: net: fsl-mc: Update calculation of MC RAMYork Sun2017-03-141-51/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the reserved RAM is tracked by gd->arch.resv_ram, calculation of MC memory blocks can be simplified. The MC RAM is guaranteed to be aligned by the reservation process. Signed-off-by: York Sun <york.sun@nxp.com> CC: Priyanka Jain <priyanka.jain@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | armv8: layerscape: Rewrite memory reservationYork Sun2017-03-1417-423/+233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun <york.sun@nxp.com>
| * | efi: Add a hook to allow adding memory mappingYork Sun2017-03-141-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of adding all memory banks, add a hook so individual SoC/board can has its own implementation. Signed-off-by: York Sun <york.sun@nxp.com> CC: Alexander Graf <agraf@suse.de> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | armv8: ls2080a: Move CONFIG_SYS_MC_RSV_MEM_ALIGN to KconfigYork Sun2017-03-143-2/+8
| | | | | | | | | | | | | | | | | | Use Kconfig option instead of config macro in header file. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: Move CONFIG_FSL_MC_ENET to KconfigYork Sun2017-03-143-2/+8
| | | | | | | | | | | | | | | | | | | | | Use Kconfig option instead of config macro in header file. Clean up existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8: Add global variable resv_ramYork Sun2017-03-143-0/+21
| | | | | | | | | | | | | | | | | | | | | Use gd->arch.resv_ram to track reserved memory allocation. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | arm64: booti: allow to place kernel image anywhere in physical memoryMasahiro Yamada2017-03-141-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At first, the ARM64 Linux booting requirement recommended that the kernel image be placed text_offset bytes from 2MB aligned base near the start of usable system RAM because memory below that base address was unusable at that time. This requirement was relaxed by Linux commit a7f8de168ace ("arm64: allow kernel Image to be loaded anywhere in physical memory"). Since then, the bit 3 of the flags field indicates the tolerance of the kernel physical placement. If this bit is set, the 2MB aligned base may be anywhere in physical memory. For details, see Documentation/arm64/booting.txt of Linux. The booti command should be also relaxed. If the bit 3 is set, images->ep is respected, and the image is placed at the nearest bootable location. Otherwise, it is relocated to the start of the system RAM to keep the original behavior. Another wrinkle we need to take care of is the unknown endianness of text_offset for a kernel older than commit a2c1d73b94ed (i.e. v3.16). We can detect this based on the image_size field. If the field is zero, just use a fixed offset 0x80000. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | tools: fix cross-compiling tools when HOSTCC is overriddenMasahiro Yamada2017-03-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Richard reported U-Boot tools issues in OpenEmbedded/Yocto project. OE needs to be able to change the default compiler. If we pass in HOSTCC through the make command, it overwrites all HOSTCC instances, including ones in tools/Makefile and tools/env/Makefile, which breaks "make cross_tools" and "make env", respectively. Add "override" directives to avoid overriding HOSTCC instances that really need to point to the cross-compiler. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Richard Purdie <richard.purdie@linuxfoundation.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | tiny-printf: add static to locally used functionsMasahiro Yamada2017-03-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | These two functions are only used in lib/tiny-printf.c . Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Roese <sr@denx.de>
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