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* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2019-10-3056-94/+359
|\ | | | | | | | | | | | | | | - H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil)
| * sunxi: set PIO voltage to hardware-detected value on startup on H6Icenowy Zheng2019-10-252-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC has a register to set the PIO banks' voltage. When it mismatches the real voltage supplied to the VCC to the PIO supply, the PIO will work improperly. The PIO controller also has a register that contains the status of each VCC rail of the PIO supplies, and it has the same definition with the configuration register. so we can just copy the content of this register to the configuration register at startup, to ensure the configuration is correct at startup stage. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> [jagan: s/__maybe__unused/__maybe_unused] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: dts: sync dts for Allwinner H6Clément Péron2019-10-253-3/+131
| | | | | | | | | | | | | | | | | | | | | | | | Sync Kernel DTS for Allwinner H6 boards. Drop /omit-if-no-ref/ keyword as it's not supported by U-boot. commit <d45331b00ddb> Linux 5.3-rc4 Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: Fix pll1 clock calculationStefan Mavrodiev2019-10-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clock_sun6i.c is used for sun6i, sun8i and sun50i SoC families. PLL1 clock sets the default system clock, defined as: sun6i: 1008000000 sun8i: 1008000000 sun50i: 816000000 With the current calculation, m = 2 and k = 3. Solving for n, this results 28. Solving back: (24MHz * 28 * 3) / 2 = 1008MHz However if the requested clock is 816, n is 22.66 rounded to 22, which results: (24MHz * 28 * 3) / 2 = 792MHz Changing k to 4 satisfies both system clocks: (24E6 * 21 * 4) / 2 = 1008MHz (24E6 * 17 * 4) / 2 = 816MHz Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm64: dts: sun50i: Add support for A64 OLinuXino (with eMMC)Sunil Mohan Adapa2019-10-254-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A64 OLinuXino board from Olimex has three variants with onboard eMMC: A64-OLinuXino-1Ge16GW, A64-OLinuXino-1Ge4GW and A64-OLinuXino-2Ge8G-IND. In addition, there are two variants without eMMC. One without eMMC and one with SPI flash. This suggests the need for separate device tree for the three eMMC variants. The Linux kernel upstream has chosen to create and use a separate device tree for the eMMC variants instead of adding eMMC support existing device tree. These changes to Linux kernel are queued for Linux 5.4. commit <02bb66b347ff8115f53948f86b884e008ba385b9> ("arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)") This patch has been tested on A64-OLinuXino-1Ge16GW and is based on Linux device-tree and a64-olinuxino_defconfig. Signed-off-by: Sunil Mohan Adapa <sunil@medhas.org> [jagan: updated linux-next commit details] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: H6: DRAM: Add support for half DQJernej Skrabec2019-10-252-25/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Half DQ configuration seems to be very rare for H6 based boards/STBs, but exists nevertheless. Currently the only known product which needs this support is Tanix TX6 mini. This commit adds support for half DQ configuration. Code was tested for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix TX6 4 GiB/DDR3) and none were found. Thanks to Icenowy Zheng for help with this code. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: thomas graichen <thomas.graichen@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Maxime Ripard <mripard@kernel.org>
| * spi-nor-ids: Add support for Adesto AT25SL321Fabio Estevam2019-10-251-0/+1
| | | | | | | | | | | | | | | | | | Add an entry for the Adesto AT25SL321 SPI NOR chip. This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi: Clean up usage of CONFIG_SPI_FLASH_MTDFrieder Schrempf2019-10-2526-37/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most boards currently use SPI_FLASH_MTD only in U-Boot proper, not in SPL. They often rely on hacks in the board header files to include this option conditionally. To be able to fix this, we previously introduced a separate option SPL_SPI_FLASH_MTD. Therefore we can now adjust the Makefile and change the code in sf_probe.c and sf_internal.h to use CONFIG_IS_ENABLED(SPI_FLASH_MTD). We also need to move all occurences of CONFIG_SPI_FLASH_MTD from the header files to the according defconfigs. The affected boards are socfpga, aristainetos, cm_fx6, display5, ventana, rcar-gen2, dh_imx6 and da850evm. We do this all in one patch to guarantee bisectibility. This change was tested with buildman to make sure it does not introduce any regressions by comparing the resulting binary sizes. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entryVignesh Raghavendra2019-10-251-5/+6
| | | | | | | | | | | | | | | | | | | | | | n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi-nor: spi-nor-ids: Add entries for mt25q variantsVignesh Raghavendra2019-10-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*Vignesh Raghavendra2019-10-251-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: designware_spi: Disable and free clock when remove driverLey Foon Tan2019-10-251-1/+15
| | | | | | | | | | | | | | | | Disable and free clock when remove driver. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with ↵Vignesh Raghavendra2019-10-252-2/+2
| | | | | | | | | | | | | | | | | | | | | | SPI_FLASH_USE_4K_SECTORS U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS. Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor-core: Use dev_err for reporting erase/write failuresVignesh Raghavendra2019-10-251-3/+3
| | | | | | | | | | | | | | | | Use dev_err() when reporting reason for erase/write failures so that users can be made aware of the reason for failure. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * stm32mp1: configs: Add CONFIG_SPL_SPI_FLASH_MTDFrieder Schrempf2019-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | As SPI_FLASH_MTD is used in SPL and U-Boot proper, we enable both, now that a separate option for SPL was introduced. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> [jagan: drop unrelated change] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi: Add a new option SPL_SPI_FLASH_MTD to KconfigFrieder Schrempf2019-10-251-0/+8
| | | | | | | | | | | | | | | | | | To allow SPI_FLASH_MTD being enabled separately in SPL we add a new option. The only user currently is the stm32mp15_basic board. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Acked-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * configs: sopine-baseboard: Enable SPI-FLASHJagan Teki2019-10-252-0/+13
| | | | | | | | | | | | | | SoPine has winbond SPI-FLASH, so enable the same in defconfig and add aliases for spi0 in -u-boot.dtsi Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: sunxi: Enable SPI/SPI-FLASH support for A64Jagan Teki2019-10-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | SPI is available in Allwinner A64 SoC, so enable it globally in Kconfig. - CONFIG_SPI - CONFIG_DM_SPI - CONFIG_DM_SPI_FLASH Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: Kconfig: Enable SPI_SUNXI for SUNXIJagan Teki2019-10-251-0/+1
| | | | | | | | | | | | | | | | | | SPI_SUNXI driver is fully dm-aware and the Allwinner architecture kconfig would have logic to enable the DM_SPI. So, select default spi sunxi driver for sunxi architecture. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi: Kconfig: Imply SPI_FLASH if DM_SPI_FLASHJagan Teki2019-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | DM_SPI_FLASH should require spi flash interface code for dm version, so imply SPI_FLASH core by default if any board enabled DM_SPI_FLASH. This overcome the explicit enablement of CONFIG_SPI_FLASH on respective boards when DM_SPI_FLASH being used. Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * cmd: sf: Mark it default if DM_SPI_FLASH enabledJagan Teki2019-10-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If DM_SPI_FLASH enabled that means it is using sf command for flash interface to access. SPI_FLASH can be used via sf command and board/driver functions to call spi flash ops, so mark it default only for DM_SPI_FLASH. This would prevent explicit adding of CONFIG_CMD_SF when DM_SPI_FLASH being enabled. Cc: Tom Rini <trini@konsulko.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * dm: spi: Change cs_info op to return -EINVAL for invalid cs numBin Meng2019-10-257-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need distinguish the following two situations in various SPI APIs: - given chip select num is invalid - given chip select num is valid, but no device is attached Currently -ENODEV is returned for both cases. For the first case, it's more reasonable to return -EINVAL instead of -ENODEV for invalid chip select numbers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * dm: spi: Return 0 if driver does not implement ops->cs_infoBin Meng2019-10-252-6/+5
| | | | | | | | | | | | | | | | | | | | If an SPI controller driver does not implement ops->cs_info, that probably means any chip select number could be valid, hence let's return 0 for spi_cs_info(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: Kconfig: Add help textJagan Teki2019-10-251-0/+17
| | | | | | | | | | | | Add detailed help text for SPI support. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor: ids: Add is25wp256 chipJagan Teki2019-10-251-0/+2
| | | | | | | | | | | | | | | | | | | | Add is25wp256, chip to spi-nor id table. Tested on SiFive FU540 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * mtd: spi: Kconfig: Update CONFIG_SPI_FLASHJagan Teki2019-10-251-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | 1) CONFIG_SPI_FLASH is not just a legacy code, but it has common core code which handle both dm and non-dm spi flash code. So fix the info text to make it clear globally. 2) Since it's flash core it shouldn't depends on legacy SPI, so remove the 'depends on SPI' Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsWIP/25Oct2019Tom Rini2019-10-2575-545/+2327
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
| * | configs: mtmips: remove configs which are selected in Kconfig or uselessWeijie Gao2019-10-254-28/+0
| | | | | | | | | | | | | | | | | | | | | Some configs are selected in Kconfig and is no longer needed in the defconfig files. Some configs (power domain, ram) are never used. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | mips: mtmips: select essential drivers in KconfigWeijie Gao2019-10-252-0/+8
| | | | | | | | | | | | | | | | | | | | | Some drivers (clk, pinctrl, reset, ...) are necessary for reset of the system, they should be always selected. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | mips: mtmips: change baudrate table for all boardsWeijie Gao2019-10-252-2/+2
| | | | | | | | | | | | | | | | | | | | | This patch changes baudrate table for all boards preparing for using mtk highspeed uart driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | dts: mtmips: add default pinctrl to eth nodes for all boardsWeijie Gao2019-10-252-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds default eth pinctrl for all boards. There are two pinctrl nodes used for two scenarios: ephy_iot_mode - for IOT boards which have only one port (PHY0) ephy_router_mode - For routers which have more than one ports Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | dts: mtmips: add default pinctrl for gardena-smart-gateway-mt7688Weijie Gao2019-10-251-0/+3
| | | | | | | | | | | | | | | | | | | | | This adds default pinctrl (dual SPI chip select) for gardena smart gateway Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | dts: mtmips: add mmc related nodes for mt7628an.dtsiWeijie Gao2019-10-251-0/+22
| | | | | | | | | | | | | | | | | | This patch adds mmc related nodes for mt7628an.dtsi Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | mmc: mtk-sd: add a dts property cd-active-high for builtin-cd modeWeijie Gao2019-10-251-1/+5
| | | | | | | | | | | | | | | | | | | | | This patch adds a dts property cd-active-high for builtin-cd mode to make it configurable instead of using hardcoded active-low. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | mmc: mtk-sd: add support for MediaTek MT7620/MT7628 SoCsWeijie Gao2019-10-252-4/+21
| | | | | | | | | | | | | | | | | | This patch adds mmc support for MediaTek MT7620/MT7628 SoCs. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | dts: mtmips: enable eth port0 led and link poll functions for all boardsWeijie Gao2019-10-253-1/+27
| | | | | | | | | | | | | | | | | | | | | This patch adds default p0led status and phy0 link polling for all boards. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | net: mt7628-eth: add support to isolate LAN/WAN portsWeijie Gao2019-10-251-0/+32
| | | | | | | | | | | | | | | | | | | | | This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to prevent LAN devices from getting IP address from WAN. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | net: mt7628-eth: free rx descriptor on receiving failureWeijie Gao2019-10-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When received a packet with an invalid length recorded in rx descriptor, we should free this rx descriptor to allow us to continue to receive following packets. Without doing so, u-boot will stuck in a dead loop trying to process this invalid rx descriptor. This patch adds a call to mt7628_eth_free_pkt() after received an invalid packet length. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | net: mt7628-eth: make phy link up detection optional via DTWeijie Gao2019-10-252-29/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port). Although in IOT mode only port0 is usable, the phy0 is still connected to the switch, not the ethernet gmac directly. This patch rewrites it and makes it optional. It can be turned on by adding mediatek,poll-link-phy = <?> explicitly into the eth node. By default the driver is switch mode with all 5 phy ports working without link detection. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy resetWeijie Gao2019-10-251-37/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes hardcoded gpio settings as they have been replaced by pinctrl in dts, and also replaces regmap-based phy reset with a more generic reset controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 partWeijie Gao2019-10-252-68/+158
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | dts: mtmips: update reset controller node for mt7628Weijie Gao2019-10-251-12/+24
| | | | | | | | | | | | | | | | | | This patch updates reset controller node for mt7628 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | reset: add reset controller driver for MediaTek MIPS platformWeijie Gao2019-10-254-0/+126
| | | | | | | | | | | | | | | | | | | | | This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | dts: mtmips: add default pinctrl for uart nodesWeijie Gao2019-10-251-0/+9
| | | | | | | | | | | | | | | | | | This patch adds default pinctrl for uart nodes Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | dts: mtmips: add pinctrl node for mt7628Weijie Gao2019-10-251-0/+150
| | | | | | | | | | | | | | | | | | This patch adds pinctrl node with default pin state for mt7628an.dtsi. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | pinctrl: add support for MediaTek MT7628Weijie Gao2019-10-257-0/+747
| | | | | | | | | | | | | | | | | | | | | This patch adds pinctrl support for mt7628, with a file for common pinmux functions and a file for mt7628 which has additional support for pinconf. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | spi: mt7621-spi: restore default register value after each xferWeijie Gao2019-10-251-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver. This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | spi: mt7621-spi: remove data cache and rewrite its xfer functionWeijie Gao2019-10-251-106/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mt7621 spi controller supports continuous generic half-duplex spi transaction. There is no need to cache xfer data at all. To achieve this goal, the OPADDR register must be used as the first data to be sent. And follows the eight generic DIDO registers. But one thing different between OPADDR and DIDO registers is OPADDR has a reversed byte order. With this patch, any amount of data can be read/written in a single xfer function call. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | spi: mt7621-spi: use clock frequency from clk driverWeijie Gao2019-10-251-7/+13
| | | | | | | | | | | | | | | | | | | | | This patch lets the spi driver to use clock provided by the clk driver since the new clk-mt7628 driver provides accurate sys clock frequency. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | dts: mtmips: add clock node for mt7628Weijie Gao2019-10-251-4/+17
| | | | | | | | | | | | | | | | | | | | | This patch adds clkctrl node for mt7628 and adds clocks property for some node. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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