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* arm: qemu: fix failure in flash initialization if booting from TF-AAKASHI Takahiro2019-07-182-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | If U-Boot is loaded and started from TF-A (you need to change SYS_TEXT_BASE to 0x60000000), it will hang up at flash initialization. If secure mode is off (default, or -machine virt,secure=off) at qemu, it will provide dtb with two flash memory banks: flash@0 { bank-width = <0x4>; reg = <0x0 0x0 0x0 0x4000000 0x0 0x4000000 0x0 0x4000000>; compatible = "cfi-flash"; }; If secure mode is on, on the other hand, qemu provides dtb with 1 bank: flash@0 { bank-width = <0x4>; reg = <0x0 0x4000000 0x0 0x4000000>; compatible = "cfi-flash"; }; As a result, flash_init()/flash_get_size() will eventually fail. With this patch applied, relevant CONFIG values are modified. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* arm: move CONFIG_TFABOOT to generic KconfigAKASHI Takahiro2019-07-182-7/+29
| | | | | | | | | | | | | | | | | | | | | | | Currently, CONFIG_TFABOOT is located in armv8/fsl-layerscape Kconfig, but it will be also useful for other targets if some additional configuration are necessary. So move it to arch/arm/Kconfig. Please note that CONFIG_TFABOOT still depends on CONFIG_ARCH_SUPPORT_TFABOOT and so the menu won't come up if any target doesn't need its own customization for TF-A boot. This will maintain the compatibility. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Sriram Dash <sriram.dash@nxp.com> Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Cc: Peng Ma <peng.ma@nxp.com> Cc: Yuantian Tang <andy.tang@nxp.com> Cc: Pankit Garg <pankit.garg@nxp.com>
* doc: Move fastboot protocol doc to android dirSam Protsenko2019-07-182-2/+2
| | | | Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
* cmd: mem: Add a command to fill the memory with random dataJean-Jacques Hiblot2019-07-182-0/+59
| | | | | | This command fills the memory with data produced by rand(). Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* tools: mkenvimage: Always consider non-regular filesAndre Przywara2019-07-181-49/+21
| | | | | | | | | | | | | | | | | | | At the moment mkenvimage has two separate read paths: One to read from a potential pipe, while dynamically increasing the buffer size, and a second one using mmap(2), using the input file's size. This is problematic for two reasons: - The "pipe" path will be chosen if the input filename is missing or "-". Any named, but non-regular file will use the other path, which typically will cause mmap() to fail: $ mkenvimage -s 256 -o out <(echo "foo=bar") - There is no reason to have *two* ways of reading a file, since the "pipe way" will always work, even for regular files. Fix this (and simplify the code on the way) by always using the method of dynamically resizing the buffer. The existing distinction between the two cases will merely be used to use the open() syscall or not. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* tools: mkenvimage: Fix reading from slow pipeAndre Przywara2019-07-181-2/+1
| | | | | | | | | | | | | | | | | | | | | It is perfectly fine for the read(2) syscall to return with less than the requested number of bytes read (short read, see the "RETURN VALUE" section of the man page). This typically happens with slow input (keyboard, network) or with complex pipes. So far mkenvimage expects the exact number of requested bytes to be read, assuming an end-of-file condition otherwise. This wrong behaviour can be easily shown with: $ (echo "foo=bar"; sleep 1; echo "bar=baz") | mkenvimage -s 256 -o out - The second line will be missing from the output. Correct this by checking for any positive, non-zero return value. This fixes a problem with a complex pipe in one of my scripts, where the environment consist of two parts. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Alexander Dahl <ada@thorsis.com>
* test/py: gpt: Use long options for sgdiskSam Protsenko2019-07-181-4/+7
| | | | | | | | | | | | | sgdisk 0.8.10.2 from AOSP doesn't support short options, failing with errors like this: sgdisk: invalid option -- 'U' Test fails due to that error. Let's use long options to make the test work with any sgdisk version. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com>
* env: mmc: add erase-functionFrank Wunderlich2019-07-181-0/+51
| | | | | | | | | | | | | | this adds erase environment for mmc storage squashed fixes: - add CONFIG_CMD_ERASEENV - env: erase redundant offset if defined - changes mentioned by Simon - fix whitespaces around errmsg Suggested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* env: register erase commandFrank Wunderlich2019-07-184-0/+75
| | | | | | | | | | | | | | | | | this patch adds basic changes for adding a erase-subcommand to env with this command the environment stored on non-volatile storage written by saveenv can be cleared. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> squashed fixes - start message with "Erasing" - mark erase-function as optional - env: separate eraseenv from saveenv Suggested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* common: Fix autocompletion with CONFIG_CMDLINE_PS_SUPPORTMarek Vasut2019-07-181-1/+6
| | | | | | | | | | | The autocompletion did not work if CONFIG_CMDLINE_PS_SUPPORT was enabled because U-Boot was comparing the prompt string with CONFIG_SYS_PROMPT . While this works if CONFIG_CMDLINE_PS_SUPPORT is disabled, this no longer works if it's enabled because user can override the PS1 . Fix this by checking prompt string against the current PS1 value. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com>
* regulator: Allow enabling GPIO regulatorSven Schwermer2019-07-182-1/+19
| | | | | | | | | | Drivers need to be able to enable regulators that may be implemented as GPIO regulators. Example: fsl_esdhc enables the vqmmc supply which is commonly implemented as a GPIO regulator in order to switch between I/O voltage levels. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* regulator: Factor out common enable codeSven Schwermer2019-07-185-69/+124
| | | | | | | | | In preparation of being able to enable/disable GPIO regulators, the code that will be shared among the two kinds to regulators is factored out into its own source files. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* ARM: correct detection of thumb modeHeinrich Schuchardt2019-07-182-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a crash occurs in thumb mode the crash dump is incorrect. This is due to the usage of a non-existing configuration variable CONFIG_ARM_THUMB in the definition of macro thumb_mode(regs). Use CONFIG_IS_ENABLED(SYS_THUMB_BUILD) to detect that the code has been compiled for thumb mode. Remove ARM_THUMB from config_whitelist.txt. With the patch crash dumps indicate thumb mode correctly. On a system with thumb mode: => exception unaligned data abort pc : [<8f7a2b52>] lr : [<8f7ab1ef>] reloc pc : [<1780cb52>] lr : [<178151ef>] sp : 8ed8c3f8 ip : 8f7a2b4d fp : 00000002 r10: 8f7f8228 r9 : 8ed95ea8 r8 : 8ed99488 r7 : 8f7ab141 r6 : 00000000 r5 : 8ed8c3f9 r4 : 8f7f6390 r3 : 8ed9948c r2 : 00000001 r1 : 00000000 r0 : 8f7f6390 Flags: nzCv IRQs off FIQs off Mode SVC_32 (T) Code: 8f7e 466d f105 0501 (e9d5) 6700 The Flags line has '(T)' and in the Code line the output is in u16 groups. On a system without thumb mode: => exception breakpoint prefetch abort pc : [<7ff5a5c8>] lr : [<7ff675ec>] reloc pc : [<0000e5c8>] lr : [<0001b5ec>] sp : 7ee0ad80 ip : 7ff5a5cc fp : 7ff674cc r10: 00000002 r9 : 7ef0bed8 r8 : 7ffd6214 r7 : 7ef0e080 r6 : 00000000 r5 : 7ffd4090 r4 : 00000000 r3 : 7ef0e084 r2 : 00000001 r1 : 00000000 r0 : 7ffd4090 Flags: nzCv IRQs off FIQs off Mode SVC_32 Code: e1a0500d e2855001 e1c560d0 e3a00001 (e12fff1e) The Flags line does not show '(T)' and in the Code line the output is in u32 groups. Reported-by: Marek Vasut <marex@denx.de> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Marek Vasut <marex@denx.de>
* ext4: add support for filesystems without JOURNALMarek Szyprowski2019-07-182-0/+6
| | | | | | | | | JOURNAL is optional for EXT4 (and EXT3) filesystems, so add support for skipping it. This fixes corrupting EXT4 volumes without JOURNAL after using uboot's 'ext4write' command. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* ext4: fix calculating inode blkcount for non-512 blocksize filesystemsMarek Szyprowski2019-07-183-2/+3
| | | | | | | | | | | | | | The block count entry in the EXT4 filesystem disk structures uses standard 512-bytes units for most of the typical files. The only exception are HUGE files, which use the filesystem block size, but those are not supported by uboot's EXT4 implementation anyway. This patch fixes the EXT4 code to use proper unit count for inode block count. This fixes errors reported by fsck.ext4 on disks with non-standard (i.e. 4KiB, in case of new flash drives) PHYSICAL block size after using 'ext4write' uboot's command. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* rtc: Add DM support to ds3231Chuanhua Han2019-07-181-0/+107
| | | | | | | | Add an implementation of the ds3231 driver that uses the driver model i2c APIs. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* lib: rsa: add support to other openssl engine types than pkcs11Vesa Jääskeläinen2019-07-183-5/+52
| | | | | | | | | | | There are multiple other openssl engines used by HSMs that can be used to sign FIT images instead of forcing users to use pkcs11 type of service. Relax engine selection so that other openssl engines can be specified and use generic key id definition formula. Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> Cc: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2019-07-16165-328/+719
|\ | | | | | | | | | | - Beelink-x2 STB support (Marcus) - H6 DDR3, LPDDR3 changes (Andre, Jernej) - H6 pin controller, USB PHY (Andre)
| * sunxi: H6: Enable USB for existing boardsAndre Przywara2019-07-165-0/+10
| | | | | | | | | | | | | | | | | | | | | | So far USB was not enabled for the Allwinner H6 boards, as the PHY driver was not ready and the clock gates were missing. Since this is now fixed, let's add the PHY and the OHCI/EHCI drivers to the build, for all existing H6 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: phy: Add USB PHY support for Allwinner H6Andre Przywara2019-07-161-0/+20
| | | | | | | | | | | | | | | | | | | | | | The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual), which require a small addition to the USB PHY driver: In this case the second PHY is PHY3, not PHY1, so we need to skip number 1 and 2 in the code. Just use the respective code from Linux for that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: clocks: Add H6 USB clock gates and resetsAndre Przywara2019-07-161-0/+29
| | | | | | | | | | | | | | | | | | | | To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: gpio: Enable support for H6 pin controllerAndre Przywara2019-07-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 pin controller is not really special, at least not when it comes to normal GPIO operation. Add the H6 compatible strings to the list of recognised strings, to make GPIOs work for H6 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: move SUNXI_GPIO to KconfigAndre Przywara2019-07-164-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | Probably for no particular reason SUNXI_GPIO was still defined the "old way", in header files only. Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove another line from our dreadful config_whitelist.txt. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: H6: Add DDR3 DRAM delay valuesJernej Skrabec2019-07-161-6/+17
| | | | | | | | | | | | | | | | | | | | | | Add some basic line delay values to be used with DDR3 DRAM chips on some H6 TV boxes. Taken from a register dump after boot0 initialised the DRAM. Put them as the default delay values for DDR3 DRAM until we know better. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: H6: Add DDR3-1333 timingsAndre Przywara2019-07-163-0/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a routine to program the timing parameters for DDR3-1333 DRAM chips connected to the H6 DRAM controller. The values were gathered from doing back-calculations from a register dump, trying to match them up with the official JEDEC DDDR3 spec. If in doubt, the register dump values were taken for now, but the JEDEC recommendation were added as a comment. Many thanks to Jernej for contributing fixes! Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: H6: Add DDR3 support to DRAM controller driverAndre Przywara2019-07-162-28/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment the H6 DRAM driver only supports LPDDR3 DRAM. Extend the driver to cover DDR3 DRAM as well. The changes are partly motivated by looking at the ZynqMP register documentation, partly by looking at register dumps after boot0/libdram has initialised the controller. Many thanks to Jernej for contributing some fixes! Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: H6: move LPDDR3 timing definition into separate fileAndre Przywara2019-07-1610-148/+177
| | | | | | | | | | | | | | | | | | | | | | | | Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM. Split the timing parameters for this LPDDR3 configuration into a separate file, to allow selecting an alternative later at compile time (as the sunxi-dw driver does). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: H6: DRAM: follow recommended PHY init algorithmAndre Przywara2019-07-161-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The DRAM controller manual suggests to first program the PHY initialisation parameters to the PHY_PIR register, and then set bit 0 to trigger the initialisation. This is also used in boot0. Follow this recommendation by setting bit 0 in a separate step. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: H6: DRAM: avoid memcpy() on MMIO registersAndre Przywara2019-07-161-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Using memcpy() is, however tempting, not a good idea: It depends on the specific implementation of memcpy, also lacks barriers. In this particular case the first registers were written using 64-bit writes, and the last register using four separate single-byte writes. Replace the memcpy with a proper loop using the writel() accessor. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sun8i: h3: Add support for the Beelink-x2 STBMarcus Cooper2019-07-154-0/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot, 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a dual colour LED and an optical S/PDIF connector. Linux commit details about the sun8i-h3-beelink-x2.dts sync: "ARM: dts: sun8i: h3: Add ethernet0 alias to Beelink X2" (sha1: cc4bddade114b696ab27c1a77cfc7040151306da) Signed-off-by: Marcus Cooper <codekipper@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * sunxi: move CONFIG_SPL_TEXT_BASE from *_defconfig to KconfigAndre Przywara2019-07-15147-146/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The choice of the SPL_TEXT_BASE is not really a decision that should be specified by each board's defconfig, as this setting is actually dictated by the SoC's memory map and the BootROM behaviour. To make this obvious and reduce the clutter in the defconfig files, let's specify the SoC constraints in the Kconfig stanza. This allows us to remove these lines from the defconfig files again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2019-07-1532-625/+1506
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| * | net: macb: Add support for 1000-baseXRadu Pirea2019-07-151-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and LPA_1000XHALF bits. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: macb: Fixed reading MII_LPA registerRadu Pirea2019-07-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | If macb is gem and is gigabit capable, lpa value is not read from the right register(MII_LPA) and is read from MII_STAT1000. This patch fixes reading of the lpa value. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | configs: am65x_evm_a53: enable networkingGrygorii Strashko2019-07-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable TI K3 AM65x CPSW NUSS driver. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defsGrygorii Strashko2019-07-151-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add mcu cpsw nuss pinmux and phy defs required by cpsw. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | arm64: dts: ti: k3-am65: add mcu cpsw nodeGrygorii Strashko2019-07-152-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mcu cpsw and its components along with scm_conf node to have ethernet functional. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driverKeerthy2019-07-153-0/+801
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addrKeerthy2019-07-152-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use phys_addr_t for mdio_base address to avoid build warnings on arm64 and dra7. Cast it to uintprt_t before assigning to regs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: cortina: Use block layer to read from mmcYinbo Zhu2019-07-151-0/+5
| | | | | | | | | | | | | | | | | | | | | This patch is to use block layer to read from mmc in cortina Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mscc: refactor mscc_miimHoratiu Vultur2019-07-158-516/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because all MSCC SoC use the same MDIO bus, put the implementation in one common file(mscc_miim) and make all the other MSCC network drivers to use these functions. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | test: dm: add MDIO testAlex Marginean2019-07-157-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A very simple test for DM_MDIO, mimicks a register write/read through the sandbox bus to a dummy PHY. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: introduce MDIO DM class for MDIO devicesAlex Marginean2019-07-156-0/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as stand-alone devices. Useful in particular for systems that support DM_ETH and have a stand-alone MDIO hardware block shared by multiple Ethernet interfaces. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: mscc: serval: Remove delay when serdes is configuredHoratiu Vultur2019-07-151-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When serdes configuration was written in hardware there was a delay of 100ms to be sure that configuration was written. But the delay is not needed because already the function serdes_write it is checking that the operation finished. Therefore remove the mdelay. This improves the speed of configuring the network driver. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: ti: Fix clock output DT propertyTrent Piepho2019-07-151-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code block reading the DT property for the clock output control was before the phy's DT node pointer was set, so it could never work. Move it after the node pointer is set. Also store the unsigned 32-bit property into an unsigned value, not a signed value, as the former will cause a problem if value overflows. For instance, if one were to add 0xffffffff as a code to mean the clock output should be turned off. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: ti: Use default values for tx/rx delay and fifo sizeTrent Piepho2019-07-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When not using DM_ETH, these PHY settings are programmed with default values hardcoded into the driver. When using DM_ETH, they should come from the device tree. However, if the device tree does not have the properties, the driver will silent use -1. Which is entirely out of range, programs nonsense into the PHY's registers, and does not work. Change this to use the same defaults as non-DM_ETH if the device tree is lacking the properties. As an alternative, the kernel driver for the phy will display an error message and fail if the device tree is lacking. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | cmd: mii: Add the standard 1000BASE-T registersTrent Piepho2019-07-151-5/+29
| | | | | | | | | | | | | | | | | | | | | | | | These are standard across gigabit phys. These mostly extend the auto-negotiation information with gigabit fields. Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | cmd: mii: Refactor some of the MII reg dump codeTrent Piepho2019-07-151-85/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Share the code that prints out a register field with the function that prints out the "special" fields. There were two arrays the register dump list, one with reg number and name, another with a pointer to the field table and the table size. These two arrays had have each entry match what register is referred to. Combine them into just one table. Now they can't not match and there is just one table. Add some missing consts to pointers to string literals. The dump code was ignoring the regno field in the description table and assuming register 0 was at index 0, etc. Have it use the field. Change reg > max+1 into reg >= max, which doesn't fail if max+1 could overflow, besides just making more sense. Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Merge tag 'mmc-2019-7-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini2019-07-1517-419/+659
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | - mmc spi driver model support - drop mmc_spi command - enhanced Strobe mmc HS400 support - minor mmc bug/fixes and optimization - omap hsmmc and mvbeu update - sdhci card detect support
| * | mmc: fsl_esdhc_imx: enlarge mmc timeoutPeng Fan2019-07-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Flash system partition with fastboot will earse the partition firstly The 600ms timeout will fail on some SD Card. Enlarge it to 5s to make it works for most of sdcard Cc: guoyin.chen <guoyin.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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