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* phy: atheros: consolidate {ar8031|ar8035}_config()WIP/2020-05-07-atheros-phy-improvementsMichael Walle2020-05-071-27/+3
| | | | | | | The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: ar8035: remove static clock configMichael Walle2020-05-071-13/+0
| | | | | | | | | | | | | | | We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: add device tree bindings and configMichael Walle2020-05-073-2/+270
| | | | | | | | | | | | | | | | | Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: move delay config to common functionMichael Walle2020-05-071-16/+22
| | | | | Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: introduce debug read and write functionsMichael Walle2020-05-071-16/+41
| | | | | | | Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: use defines for PHY IDsMichael Walle2020-05-071-3/+7
| | | | | Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: fix AR8021 PHY ID maskMichael Walle2020-05-071-1/+1
| | | | | | | The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Clarify the intention of ar8021_configVladimir Oltean2020-05-071-4/+4
| | | | | | | | | | | Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Explicitly disable RGMII delaysVladimir Oltean2020-05-071-0/+8
| | | | | | | | | | | | To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Clarify the configuration of the CLK_25M output pinVladimir Oltean2020-05-071-5/+14
| | | | | | | | Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Use common functions for RGMII internal delaysVladimir Oltean2020-05-071-28/+41
| | | | | Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: Make RGMII Tx delays actually configurable for AR8035Vladimir Oltean2020-05-071-4/+0
| | | | | | | | | | | | | | | | | | | | | Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch '2020-05-06-master-imports'Tom Rini2020-05-0717-91/+200
|\ | | | | | | | | - ARM Juno updates - Assorted bugfixes
| * menu: add support for client defined statusline functionThirupathaiah Annapureddy2020-05-074-37/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently displaying status line is done in a weak function menu_display_statusline(). bootmenu.c overrides the weak default function. It calls menu_default_choice() and interprets the data as struct bootmenu_entry. pxe boot also uses common menu code for pxe menus. If there is a system that enables both bootmenu and pxe, menu_display_statusline() defined in bootmenu.c will be called and it will interpret struct pxe_label as struct bootmenu_entry. This leads to data aborts and pxe menu corruptions. This patch adds support for client defined statusline function to resolve the above bug. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
| * rsa: fix alignment issue when getting public exponentHeiko Stuebner2020-05-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To fill the exponent field of the rsa_public_key struct, rsa_mod_exp_sw did a cast to uint64_t of the key_prop->public_exponent field. But that alignment is not guaranteed in all cases. This came to light when in my spl-fit-signature the key-name exceeded a certain length and with it the verification then started failing. (naming it "integrity" worked fine, "integrity-uboot" failed) key_prop.public_exponent itself is actually a void-pointer, fdt_getprop() also just returns such a void-pointer and inside the devicetree the 64bit exponent is represented as 2 32bit numbers, so assuming a 64bit alignment can lead to false reads. So just use the already existing rsa_convert_big_endian() to do the actual conversion from the dt's big-endian to the needed uint64 value. Fixes: fc2f4246b4b3 ("rsa: Split the rsa-verify to separate the modular exponentiation") Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * cmd: cache: Fix non-cached memory cachabilityPatrice Chotard2020-05-072-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If dcache is switched OFF to ON state and if non-cached memory is used, this non-cached memory must be re-declared as uncached to mmu each time dcache is set ON. Introduce noncached_set_region() to set this non-cached region's mmu settings. Let architecture override it by defining it as a weak function. For ARM architecture, noncached_set_region() defines all noncached region as non-cacheable. Issue found on STM32MP1 platform using dwc_eth_qos ethernet driver, when going from dcache OFF to dcache ON state, ethernet driver issued TX timeout errors when performing dhcp or ping. It can be reproduced with the following sequence: dhcp while true ; do ping 192.168.1.300 ; dcache off ; ping 192.168.1.300 ; dcache on ; done Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Cc: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * arm: vexpress64: Remove unneeded CONFIG_ checkAndre Przywara2020-05-071-6/+0
| | | | | | | | | | | | | | | | | | CONFIG_SEMIHOSTING is selected for the VFP target by the means of Kconfig already, there is no need to check this in the header file. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: juno: enable USBAndre Przywara2020-05-073-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Juno board features a standard compliant EHCI/OHCI USB host controller pair, which we can just enable. The platform data is taken from the device tree. This allows to use USB mass storage (the only storage on a Juno r0) for loading. At least on my board USB seems a bit flaky, I need two "usb reset" sequences after the "usb start" to detect an USB hard drive. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: juno: Use PSCI based resetAndre Przywara2020-05-072-3/+3
| | | | | | | | | | | | | | | | | | So far the Juno board wasn't implementing reset. Let's just use the already existing PSCI_RESET based method to avoid any extra code. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: juno: Enable OF_CONTROLAndre Przywara2020-05-074-3/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arm Juno board was still somewhat stuck in "hardcoded land", even though there are stable DTs around, and one happens to actually be on the memory mapped NOR flash. Enable the configuration options to let the board use OF_CONTROL, and add a routine to find the address of the DTB partition in NOR flash, to use that for U-Boot's own purposes. This can also passed on via $fdtcontroladdr to any kernel or EFI application, removing the need to actually load a device tree. Since the existing "afs" command and its flash routines require flash_init() to be called before being usable, and this is done much later in the boot process, we introduce a stripped-down partition finder routine in vexpress64.c, to scan the NOR flash partitions for the DT partition. This location is then used for U-Boot to find and probe devices. The name of the partition can be configured, if needed, but defaults to "board.dtb", which is used by Linaro's firmware image provided. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: juno: Fix UART clock rateAndre Przywara2020-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The UART base clock rate was typo-ed in the header file, probably because the reference (the Linux .dts) was also wrong[1]. Fix the number to make the baud rate more correct. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=39a1a8941b2 Reviewed-by: Simon Glass <sjg@chromium.org>
| * uart: pl011: Add proper DM clock supportAndre Przywara2020-05-071-16/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though the PL011 UART driver claims to be DM compliant, it does not really a good job with parsing DT nodes. U-Boot seems to adhere to a non-standard binding, either requiring to have a "skip-init" property in the node, or to have an extra "clock" property holding the base *frequency* value for the baud rate generator. DTs in the U-Boot tree seem to have been hacked to match this requirement. The official binding does not mention any of these properties, instead recommends a standard "clocks" property to point to the baud base clock. Some boards use simple "fixed-clock" providers, which U-Boot readily supports, so let's add some simple DM clock code to the PL011 driver to learn the rate of the first clock, as described by the official binding. These clock nodes seem to be not ready very early in the boot process, so provide a fallback value, by re-using the already existing CONFIG_PL011_CLOCK variable. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [trini: Add <clock_legacy.h> for get_bus_freq() for layerscape platforms] Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: juno: Fix Juno address variablesAndre Przywara2020-05-071-15/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The U-Boot documentation explains that variables ending with "_r" hold addresses in DRAM, while those without that ending point to flash/ROM. The default variables for the Juno board pointing to the kernel and DTB load addresses were not complying with this scheme: they lack the extension, but point to DRAM. This is particularly confusing since the Juno board features parallel NOR flash, so there *is* a memory mapped NOR address holding a DTB, for instance. Fix the variables to use the proper names, changing initrd_addr to ramdisk_addr_r on the way, which seems to be more prevelant and documented. On the way adjust the FDT load address to be situated *before* the kernel, since users happened to overwrite the DTB by the kernel clearing its .BSS section during initialisation. Also remove the fdt_high and initrd_high variables (which were set to -1), to allow U-Boot moving those images around. This should avoid many problems in the future, but breaks loading Linux kernels < v4.2, since they expect the DTB to be loaded in the same 512MB region as the kernel. If you need to load such an old kernel, please set fdt_high to either 0xffffffffffffffff or 0xa0000000 (if you load the kernel to the beginning of DRAM). That fixes loading debug kernels, which happened to overwrite the DTB on certain setups. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * include/eeprom.h: fix build errorsRasmus Villemoes2020-05-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CMD_EEPROM and ENV_IS_IN_EEPROM can be selected independently, and cmd/eeprom.o gets built in either case, so whether to declare the real prototypes needs to follow the same logic as whether cmd/eeprom.c is built. Otherwise a ENV_IS_IN_EEPROM=y, CMD_EEPROM=n build fails cmd/eeprom.c:73:1: error: expected identifier or ‘(’ before ‘{’ token { While at it, fix the dummy replacements (at least assuming they are meant to allow the code to compile) - they need to have the same type as the expression they replace, or one gets errors such as env/eeprom.c: In function ‘eeprom_bus_read’: env/eeprom.c:37:8: error: void value not ignored as it ought to be rcode = eeprom_read(dev_addr, offset, buffer, cnt); Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Tom Rini <trini@konsulko.com>
| * Revert "mkimage: fit: Do not tail-pad fitImage with external data"Tom Rini2020-05-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This has been reported to break booting of U-Boot from SPL on a number of platforms due to a lack of alignment of the external data. The issues this commit is addressing will need to be resolved another way. Re-introduce a data leak in the padding for now. This reverts commit 20a154f95bfe0a3b5bfba90bea7f001c58217536. Reported-by: Alex Kiernan <alex.kiernan@gmail.com> Reported-by: Michael Walle <michael@walle.cc> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Rini <trini@konsulko.com>
| * cache: l2x0: Fix missing write to Auxiliary Control RegisterLey Foon Tan2020-05-061-0/+2
| | | | | | | | | | | | | | | | | | In commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") we removed writel to regs->pl310_aux_ctrl by accident. This commit restores it back. Fixes: f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * scripts/get_default_envs.sh: preserve order of multiple entries for same ↵Rasmus Villemoes2020-05-061-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | variable It's possible that the default_environment[] array contains multiple entries for the same variable, e.g. a setting from env_default.h based on some CONFIG_* variable, and another from CONFIG_EXTRA_ENV_SETTINGS. In such a case, the last setting takes effect. Hence, in order to be able to use the output from this script as an CONFIG_DEFAULT_ENV_FILE and get the same default environment as one currently has, we need to preserve the order. So only sort by the variable name, and disable the last-resort comparison. We could pipe the result through uniq to remove duplicate lines, but I think there's some value in seeing that certain variables are defined multiple times. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-usbWIP/05May2020Tom Rini2020-05-0525-188/+1135
|\ | | | | | | - MediaTek USB host support
| * MAINTAINERS: MediaTek: add USB related filesChunfeng Yun2020-05-021-0/+3
| | | | | | | | | | | | | | | | | | Add dt-binding files of xhci-mtk and phys, C files of phys. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * dt-bindings: usb: mtk-xhci: Add binding for MediaTek xHCI host controllerChunfeng Yun2020-05-021-0/+40
| | | | | | | | | | | | | | | | Add dt-binding for MediaTek xHCI host controller Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * dt-bindings: phy-mtk-tphy: add properties of address mapping and clocksChunfeng Yun2020-05-021-10/+68
| | | | | | | | | | | | | | | | | | | | 1. add the address mapping related properties; 2. make "ref" clock optional, and add optional clock "da_ref"; 3. add the banks layout of TPHY V1 and V2; Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * arm: dts: mt7629: add usb related nodesChunfeng Yun2020-05-022-0/+49
| | | | | | | | | | | | | | | | Add usb, phy and clock nodes Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * xhci: mediatek: Add support for MTK xHCI host controllerChunfeng Yun2020-05-025-0/+323
| | | | | | | | | | | | | | | | | | | | | | This patch is used to support the on-chip xHCI controller on MediaTek SoCs, currently control/bulk/interrupt transfers are supported. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * phy: phy-mtk-tphy: add a new reference clockChunfeng Yun2020-05-021-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * phy: phy-mtk-tphy: add support new versionChunfeng Yun2020-05-021-5/+63
| | | | | | | | | | | | | | | | The new version removes all shared banks between multi-phys Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * phy: phy-mtk-tphy: add support USB physChunfeng Yun2020-05-021-9/+218
| | | | | | | | | | | | | | | | Support USB2 and USB3 PHY with shared banks when support multi-phys Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * usb: dwc2_udc_otg: use the phy bulk API to get physChunfeng Yun2020-05-021-76/+17
| | | | | | | | | | | | | | | | Use the phy bulk API to get a group of phys Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * usb: dwc3: use the phy bulk API to get physChunfeng Yun2020-05-024-85/+27
| | | | | | | | | | | | | | | | Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * test: dm: phy: add a test item for the phy_bulk APIChunfeng Yun2020-05-022-0/+44
| | | | | | | | | | | | | | | | | | | | Add a test item for the phy_bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * phy: Add API for a bulk of physChunfeng Yun2020-05-022-0/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a "bulk" API to the phy API in order to get/init/exit/power on/off a group of phys associated with a device. The bulk API will avoid adding a copy of the same code to manage a group of phys in drivers. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * test: dm: add test item for ofnode_get_child_count()Chunfeng Yun2020-05-022-0/+39
| | | | | | | | | | | | | | | | | | Add a test item for ofnode_get_child_count() Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
| * dm: core: Add function to get child count of ofnode or deviceChunfeng Yun2020-05-024-0/+37
| | | | | | | | | | | | | | | | | | | | This patch add function used to get the child count of a ofnode or a device Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'efi-2020-07-rc2-2' of ↵Tom Rini2020-05-0516-286/+174
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc2-2 This patch contains error corrections and code simplifications for the UEFI sub-system.
| * | efi_loader: change setup sequenceHeinrich Schuchardt2020-05-041-5/+5
| | | | | | | | | | | | | | | | | | | | | If we want to restore variables from disk, we need to initialize block devices before variables. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | test: stabilize test_efi_secbootHeinrich Schuchardt2020-05-043-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting up the console via function efi_console_register() we call query_console_serial(). This functions sends an escape sequence to the terminal to query the display size. The response is another escape sequence. console.run_command_list() is looking for a regular expression '^==>'. If the escape sequence for the screen size precedes the prompt without a line break, no match is found. When efi_disk_register() is called before efi_console_register() this leads to a test failuere of the UEFI secure boot tests. We can avoid the problem if the first UEFI command passed to u_boot_console.run_command_list() produces output. This patch achieves this by appending '; echo' to the first UEFI related command of the problematic tests. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | efi_loader: correct comments for efi_status_tHeinrich Schuchardt2020-05-043-5/+5
| | | | | | | | | | | | | | | | | | | | | EFI_STATUS is unsigned (UINTN). Hence it cannot be negative. Correct comments for 'Return:'. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | efi_loader: eliminate efi_set_(non)volatile_variableHeinrich Schuchardt2020-05-041-104/+37
| | | | | | | | | | | | | | | | | | | | | Eliminate superfluous functions efi_set_volatile_variable() and efi_set_nonvolatile_variable(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | efi_loader: eliminate efi_get_(non)volatile_variableHeinrich Schuchardt2020-05-041-29/+3
| | | | | | | | | | | | | | | | | | | | | Eliminate superfluous functions efi_get_volatile_variable() and efi_get_nonvolatile_variable(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | cmd: efidebug: simplify UEFI protocol callsHeinrich Schuchardt2020-05-041-21/+19
| | | | | | | | | | | | | | | | | | | | | We should not to refer to a function via the run-time or boot services tables if the function is exported. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | efi_loader: disk: add efi_disk_is_system_part()AKASHI Takahiro2020-05-042-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | This function will check if a given handle to device is an EFI system partition. It will be utilised in implementing capsule-on-disk feature. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Add function description. Return bool. Reviewed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
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