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* configs: Migrate CONFIG_FMAN_ENET and some related options to KconfigTom Rini2019-05-26219-126/+369
| | | | | | | | | Move the main symbol for Freescale Fman Ethernet controller option to Kconfig. Also migrate the CONFIG_SYS_QE_FMAN_FW_IN_xxx macros and rename the SPIFLASH one to follow the same format as all of the others. To do this fully we need to migrate CONFIG_QC, do so. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'efi-2019-07-rc3-3' of git://git.denx.de/u-boot-efiTom Rini2019-05-257-40/+174
|\ | | | | | | | | | | | | Pull request for UEFI sub-system for v2019.07-rc3 (3) Several bug fixes for the UEFI sub-system are provided. The SetTime() boottime service is implemented.
| * efi_loader: variable: attributes may not be changed if a variable existsAKASHI Takahiro2019-05-241-2/+11
| | | | | | | | | | | | | | | | If a variable already exists, efi_set_variable() should not change the variable's attributes. This patch enforces it. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: variable: return error for APPEND_WRITEAKASHI Takahiro2019-05-241-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The current efi_st_variable() doesn't support EFI_VARIABLE_APPEND_WRITE attiribute for now, and so should return an error. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Fix typos is commit message. Add TODO comment. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi: selftest: APPEND_WRITE is not supportedAKASHI Takahiro2019-05-241-14/+14
| | | | | | | | | | | | | | The error here should be marked *todo*. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: DEL is an illegal file name characterHeinrich Schuchardt2019-05-241-1/+1
| | | | | | | | | | | | | | According to the FAT32 specification 0x7f (DEL) is not a legal character for file names. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: comments for structsHeinrich Schuchardt2019-05-241-5/+14
| | | | | | | | | | | | | | Change comments for struct efi_open_protocol_info_item and struct efi_handler to Sphinx format. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: correct device path checkHeinrich Schuchardt2019-05-241-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 226cddbe32f0 ("efi_loader: check device path in InstallMultipleProtocolInterfaces") iPXE fails to access the network. LocateDevicePath() returns EFI_SUCCESS even if a shorter path is found as a partial match. It returns the remaining path. So to be sure that we found a complete match we need to check that the remaining path refers to an end node. Provide debug output if a device path has already been installed. Fixes: 226cddbe32f0 ("efi_loader: check device path in InstallMultipleProtocolInterfaces") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: return values of GetTime()Heinrich Schuchardt2019-05-241-7/+7
| | | | | | | | | | | | | | According to the UEFI spec 2.8 the GetTime() runtime service should return EFI_UNSUPPORTED if the real time clock is not available. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * efi_loader: implement SetTimeHeinrich Schuchardt2019-05-242-9/+120
| | | | | | | | | | | | | | | | Implement the SetTime() runtime service. Extend the real time clock selftest to check setting the clock. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'mips-pull-2019-05-24' of git://git.denx.de/u-boot-mipsTom Rini2019-05-254-16/+5
|\ \ | | | | | | | | | | | | - mtmips: network stability fixes for gardena-smart-gateway - mtmips: enable CONFIG_USE_PREBOOT and CONFIG_CMD_WDT
| * | mips: mt76xx: gardena-smart-gateway: Enable CONFIG_USE_PREBOOTStefan Roese2019-05-242-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_USE_PREBOOT on for the gardena mt7688 platforms, so that this feature can be used here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | mips: mt76xx: Remove cache workaround and select SYS_MALLOC_CLEAR_ON_INITStefan Roese2019-05-242-16/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 06985289d452 ("watchdog: Implement generic watchdog_reset() version") the init sequence has changed in arch_misc_init(), resulting in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena). When this happens, the first (or sometimes later ones as well) TFTP command hangs and does not complete correctly. This leads to the assumption that the d-cache is not in a clean state once the ethernet driver is called (d-cache is used here for the buffers). The old work- around with the cache flush somehow does not work any more now with the new code change. To fix this issue, this patch now removes the old workaround and selects CONFIG_SYS_MALLOC_CLEAR_ON_INIT for ARCH_MTMIPS. With this option the complete malloc area is initialized with zeros (cache lines are touched). Testing has shown that this also fixes the issue on the MT7688 boards. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | mips: mt7688: gardena-smart-gateway-mt7688: Enable CMD_WDTStefan Roese2019-05-242-0/+2
| |/ | | | | | | | | | | | | | | This patch enables the "wdt" command, which is quite useful for watchdog testing. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-bootTom Rini2019-05-2432-268/+4316
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add various STM32MP1 fixes for serial, env, clk, board, i2c ... - Add STM32MP1 DDR driver update: These update introduce the DDR interactive mode described in: https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode This mode is used by the CubeMX: DDR tuning tool. https://wiki.st.com/stm32mpu/index.php/STM32CubeMX The DDR interactive mode is NOT activated by default because it increase the SPL size and slow down the boot time (200ms wait added).
| * | stm32mp1: ram: add tuning in DDR interactive modePatrick Delaunay2019-05-236-1/+1414
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add command tuning for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to execute software tuning for the DDR configuration: - software read DQS Gating (replace the built-in one) - Bit de-skew - Eye Training or DQS training Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: ram: add tests in DDR interactive modePatrick Delaunay2019-05-235-0/+1541
| | | | | | | | | | | | | | | | | | | | | | | | Add command tests for DDR interactive mode, used during board bring-up or with CubeMX DDR tools to verify the DDR configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: ram: add interactive mode for DDR configurationPatrick Delaunay2019-05-235-0/+714
| | | | | | | | | | | | | | | | | | | | | | | | | | | This debug mode is used by CubeMX DDR tuning tools or manualy for tests during board bring-up. It is simple console used to change DDR parameters and check initialization. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: ram: add support for LPDDR2/LPDDR3Patrick Delaunay2019-05-234-52/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | Manage power supply configuration for board using stpmic1 with LPDDR2 or with LPDDR3: + VDD_DDR1 = 1.8V with BUCK3 (bypass if possible) + VDD_DDR2 = 1.2V with BUCK2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: ram: update parameter array initializationPatrick Delaunay2019-05-233-17/+34
| | | | | | | | | | | | | | | | | | | | | | | | Force alignment of the size of parameters array with the expected value in the binding, that allows compilation error when the array size change. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | ARM: dts: stm32mp1: DDR config v1.44Patrick Delaunay2019-05-232-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update DDR configuration with the latest update: - PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte lane 2/3 in 16bit - fix LPDDR2/3 timing_calc to step RL/WL in relaxed timings mode - remove LPDDR3 RL3 (optional) support vs MR0[7] because MR0[7] can't be read instead always apply worse RL/WL for LPDDR3 when freq < 166MHz) - change MR3 to 48ohm drive for LPDDR2/3 - change default ZPROG[7:4] = 0x1 for LPDDR2/3 , '0' is not allowed even when ODT not used - use DQSTRN for LPDDR2/3 (it was not set in PIR) - LPDDR3: set dqsge/dwsgx gate extension to 2,2 like LPDDR2 -DDRCTRL.dfitmg0: + for LPDDR3 tphy_wrlat = WL (as LPDDR2) + improvement for relaxed mode vs RL/Wl at corner case. For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3 and correction to MR2 accordingly - DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40, for LTDC. - DDR_PCFGWQOS0_0: change vpr level from 11 to 12 in order to include the CPU on the variable priority queue. - DDR_SCHED: fix to consider 13 levels (13 levels - 1 = 0xC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: ram: change ddr speed to kHzPatrick Delaunay2019-05-236-15/+15
| | | | | | | | | | | | | | | | | | Allow fractional support in DDR tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: ram: increase the delay after reset to 128 cyclesPatrick Delaunay2019-05-231-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | Component Notification DDR controller errata (3.00a):9001313030 Synchronization Time Waited After De-assertion of presetn is 128 pclk Cycles. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: ram: update mask for operating modePatrick Delaunay2019-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | Regression introduced by rebase, when loop was replaced by readl_poll_timeout() function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | serial: stm32: remove watchog reset in debug putcPatrick Delaunay2019-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For STM32MP, the watchdog is based on DM and the function watchod_reset call the function uclass_get_device(UCLASS_WDT) to found the driver associated IWDG2. As this reset is not mandatory in debug putc (the uart fifo will be empty after some us), we can simplify the code by removing this call. And this patch avoid issue when putc is called before initialization of DM core, before the parsing of the device tree parsing and each node bound to driver; that also avoid memory leak. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | serial: stm32: remove unnecessary tracePatrick Delaunay2019-05-231-1/+0
| | | | | | | | | | | | | | | | | | Remove the trace indicating the end of the DEBUG initialization Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | env: solve compilation error in SPLPatrick Delaunay2019-05-231-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Solve compilation issue when cli_simple.o is used in SPL and CONFIG_SPL_ENV_SUPPORT is not defined. env/built-in.o:(.data.env_htab+0xc): undefined reference to `env_flags_validate' u-boot/scripts/Makefile.spl:384: recipe for target 'spl/u-boot-spl' failed make[2]: *** [spl/u-boot-spl] Error 1 u-boot/Makefile:1649: recipe for target 'spl/u-boot-spl' failed make[1]: *** [spl/u-boot-spl] Error 2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | clk: stm32mp1: add set_rate for DDRPHYC clockPatrick Delaunay2019-05-231-0/+83
| | | | | | | | | | | | | | | | | | Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: add bootstage supportPatrick Delaunay2019-05-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the needed configurations for bootstage and activate bootstage command. BOOTSTAGE_REPORT is not activated by default. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | armv7: timer: init timer with bootstagePatrick Delaunay2019-05-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In initf_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us() before timer_init(); that cause crash for stm32mp1. This patch solve the issue without changing the initialization sequence. See also commit 97d20f69f53e ("Enable CONFIG_TIMER_EARLY with bootstage") for other solution when DM is activated for TIMER. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: add bootcount supportPatrick Delaunay2019-05-232-0/+12
| | | | | | | | | | | | | | | | | | Activate bootcount and use TAMP register to store the count value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | mkimage: change stm32image header to manage binary informationPatrick Delaunay2019-05-231-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | To get more information from STM32 Header about the generated binary, we will add a new byte with the following field: replace padding byte 255 with 0x00 for "U-Boot" Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | i2c: stm32f7: improve loopback in timing algorithmNicolas Le Bayon2019-05-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This avoids useless loops inside the I2C timing algorithm. Actually, we support only one possible solution per prescaler value. So after finding a solution with a prescaler, the algorithm can switch directly to the next prescaler value. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | i2c: stm32f7: Fix SDADEL minimum formulaNicolas Le Bayon2019-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | It conforms with Reference Manual I2C timing section. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: update RCC binding after kernel realignmentPatrick Delaunay2019-05-231-140/+287
| | | | | | | | | | | | | | | | | | | | | RCC is no more a mfd and add a complete example and alignment with latest TF-A binding Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: psci: add synchronization with ROM codePatrick Delaunay2019-05-231-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use SGI0 interruption and TAMP_BACKUP_MAGIC_NUMBER to synchronize the core1 boot sequence requested by core0 in psci_cpu_on(): - a initial interruption is needed in ROM code after RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off) - the ROM code set to 0 the 2 registers + TAMP_BACKUP_BRANCH_ADDRESS + TAMP_BACKUP_MAGIC_NUMBER when magic is not egual to BOOT_API_A7_CORE0_MAGIC_NUMBER This patch solve issue for cpu1 restart in kernel. echo 0 > /sys/devices/system/cpu/cpu1/online echo 1 > /sys/devices/system/cpu/cpu1/online Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: cosmetic: bsec: reorder include filesPatrick Delaunay2019-05-231-1/+1
| | | | | | | | | | | | | | | | | | Reorder the include files in alphabetic order. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: migrate PREBOOT to KconfigPatrick Delaunay2019-05-233-2/+2
| | | | | | | | | | | | | | | | | | Use Kconfig to activate CONFIG_PREBOOT (empty by default). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: Move ENV_SIZE and ENV_OFFSET to KconfigPatrick Delaunay2019-05-233-6/+4
| | | | | | | | | | | | | | | | | | | | | Add arch stm32mp for ENV migration step and drop more items from include/configs/xxx.h. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | stm32mp1: Move config SYS_MALLOC_LEN to KconfigPatrick Delaunay2019-05-233-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the the config SYS_MALLOC_LEN to Kconfig as it is already done for zynq arch in commit 01aa5b8f0503 ("Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2019-05-2414-7/+1154
|\ \ \ | | | | | | | | | | | | - Enable DM for SATA, SDHC, USB in T2080QDS
| * | | configs: enable sata, eSDHC, USB device module in T2080QDSPeng Ma2019-05-236-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable eSDHC, SATA and USB DM for T2080QDS in uboot Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | powerpc: mpc85xx: delete FSL_SATA for T2080QDS board.Peng Ma2019-05-231-3/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arch: powerpc: add sata node for t2080 dtsPeng Ma2019-05-231-0/+16
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | ata: fsl_ahci: Add sata DM support for Freescale powerpc socsPeng Ma2019-05-234-0/+1042
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support Freescale sata driver with dts initialized. Also resolved the following problems. ===================== WARNING ====================== This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | usb: ehci: adopt 32 bit address for CONFIG_PPCYinbo Zhu2019-05-231-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | adopt 32 bit addr in fsl_esdhc for CONFIG_PPC. So adopt 32 bit address for CONFIG_PPC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arch: powerpc: add usb node in t2080 dtsYinbo Zhu2019-05-231-0/+19
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | configs: T2080QDS: enable device tree support for pcieboot & secure bootYinbo Zhu2019-05-232-2/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | driver: mmc: adopt 32 bit addr in fsl_esdhc for CONFIG_PPCYinbo Zhu2019-05-231-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PowerPC supports 32 bit address. So adopt 32 bit addr in fsl_esdhc for CONFIG_PPC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | driver: mmc: set sdhc clock in fsl_esdhc for CONFIG_PPCYinbo Zhu2019-05-231-0/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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