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* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-11-06144-590/+1645
|\ | | | | | | | | | | | | | | | | - Add a new SMBIOS parser and enable it when booting from coreboot - Fix up various driver names to avoid dtoc warnings - Fully enable ACPI support on Google Chromebook Coral - Add a way to set SMBIOS properties using the devicetree - Update existing boards to use devicetree for SMBIOS using a new default sysinfo driver
| * smbios: Drop the unused Kconfig optionsSimon Glass2020-11-0612-68/+13
| | | | | | | | | | | | | | | | Now that we can use devicetree to specify this information, drop the old CONFIG options. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Provide default SMBIOS manufacturer/productSimon Glass2020-11-0617-1/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a file containing defaults for these, using the existing CONFIG options. This file must be included with #include since it needs to be passed through the C preprocessor. Enable the driver for all x86 boards that generate SMBIOS tables. Disable it for coral since it has its own driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: reword the commit message a little bit] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: galileo: Use devicetree for SMBIOS settingsSimon Glass2020-11-062-11/+28
| | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * arm64: mvebu: Use devicetree for SMBIOS settings on uDPUSimon Glass2020-11-062-1/+22
| | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * odroid-c2: Use devicetree for SMBIOS settingsSimon Glass2020-11-062-2/+25
| | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULXSimon Glass2020-11-062-1/+27
| | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * rockchip: Use devicetree for SMBIOS settingsSimon Glass2020-11-068-8/+93
| | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * sysinfo: Provide a default driver to set SMBIOS valuesSimon Glass2020-11-064-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | Some boards want to specify the manufacturer or product name but do not need to have their own sysinfo driver. Add a default driver which provides a way to specify this SMBIOS information in the devicetree, without needing any board-specific functionality. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * smbios: Add documentation and devicetree bindingSimon Glass2020-11-062-0/+85
| | | | | | | | | | | | | | Add information about how to set SMBIOS properties using the devicetree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * smbios: Add more propertiesSimon Glass2020-11-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The current tables only support a subset of the available fields defined by the SMBIOS spec. Add a few more. We could use CONFIG_SYS_CPU or CONFIG_SYS_SOC as a default for family, but the meaning of that value relates more to the whole system rather than just the SoC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * smbios: Allow properties to come from the device treeSimon Glass2020-11-061-17/+81
| | | | | | | | | | | | | | | | Support a way to put SMBIOS properties in the device tree. These can be placed in a 'board' device in an 'smbios' subnode. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Pass an ofnode into each SMBIOS functionSimon Glass2020-11-062-19/+30
| | | | | | | | | | | | | | | | As a first step to obtaining SMBIOS information from the devicetree, add an ofnode parameter to the writing functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * doc: Add a binding for sysinfoSimon Glass2020-11-061-0/+19
| | | | | | | | | | | | | | | | Add a simple binding file for this, so that it is clear what this binding directory is for. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * board: Rename uclass to sysinfoSimon Glass2020-11-0629-308/+314
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uclass is intended to provide a way to obtain information about a U-Boot board. But the concept of a U-Boot 'board' is the whole system, not just one circuit board, meaning that 'board' is something of a misnomer for this uclass. In addition, the name 'board' is a bit overused in U-Boot and we want to use the same uclass to provide SMBIOS information. The obvious name is 'system' but that is so vague as to be meaningless. Use 'sysinfo' instead, since this uclass is aimed at providing information on the system. Rename everything accordingly. Note: Due to the patch delta caused by the symbol renames, this patch shows some renamed files as being deleted in one place and created in another. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: zimage: Quieten down the zimage boot processSimon Glass2020-11-061-5/+6
| | | | | | | | | | | | | | | | | | Much of the output is not very useful. The bootm command is quite a bit quieter. Convert some output to use log_debug(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
| * x86: zimage: Sanity-check the kernel version before printing itSimon Glass2020-11-061-0/+9
| | | | | | | | | | | | | | | | | | | | | | With Chrome OS the kernel setup block is stored in a separate place from the kernel, so it is not possible to access the kernel version string. At present, garbage is printed. Add a sanity check to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: zimage: Add a little more loggingSimon Glass2020-11-063-0/+8
| | | | | | | | | | | | | | | | Add logging for each part of the boot process, using a new Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
| * x86: fsp: Adjust calculations for MTRR range and DRAM topSimon Glass2020-11-061-13/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the top of available DRAM is the same as the top of the range of the low-memory MTRR. In fact, U-Boot is allowed to use memory up until the start of the FSP reserved memory. Use that value for low_end, since it makes more memory available. Keep the same calculation as before for mtrr_top, i.e. the top of reserved memory. A side-effect of this change is that the E820 tables have a single entry that extends from the bottom of the memory used by U-Boot to the bottom of the FSP reserved memory. This includes the bloblist, if ACPI tables are placed there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: pinctrl: Silence the warning when a pin is not foundSimon Glass2020-11-061-1/+1
| | | | | | | | | | | | | | | | This does not necessarily indicate a problem, since some pins are optional. Let the caller show an error if necessary. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Don't show the UART address by defaultSimon Glass2020-11-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This is useful when using Linux's earlycon since the MMIO address must be provided on some platforms, e.g.: earlycon=uart8250,mmio32,0xddffc000,115200n8 However this is only for debugging, so don't show it by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: acpi: Include the TPMv1 table only if neededSimon Glass2020-11-061-8/+11
| | | | | | | | | | | | | | | | This table is not needed if a v2 TPM is in use. Add a condition to avoid adding it when not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Silence some logging statementsSimon Glass2020-11-065-11/+11
| | | | | | | | | | | | | | | | Quite a few log_info() calls are included in the x86 code which should use log_debug() instead. Convert them to reduce unwanted output. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: fsp: Convert fsp_dram to use log_debug()Simon Glass2020-11-061-2/+6
| | | | | | | | | | | | | | | | Use log_debug() instead of debug() in this file, to enable the extra features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Boot coral into Chrome OS by defaultSimon Glass2020-11-062-4/+15
| | | | | | | | | | | | | | | | Add a script to boot Chrome OS from the internal MMC. This involved adding a few commands and options. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Set up Chrome OS to boot into developer modeSimon Glass2020-11-061-6/+20
| | | | | | | | | | | | | | | | Set up a few fields necessarily to make Chrome OS boot without showing a firmware error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Use CONFIG_CHROMEOS_VBOOT for verified bootSimon Glass2020-11-067-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Define the Chrome OS GNVS regionSimon Glass2020-11-061-1/+50
| | | | | | | | | | | | | | | | | | It is not possible to boot Chrome OS properly without passing some basic information from U-Boot. This applies even if verified boot is not being used. Add a structure definition for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * acpi: Don't reset the tables with every new generationSimon Glass2020-11-064-4/+20
| | | | | | | | | | | | | | | | | | At present if SSDT and DSDT code is created, only the latter is retained for examination by the 'acpi items' command. Fix this by only resetting the list when explicitly requested. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: acpi: Put the generated code first in DSDTSimon Glass2020-11-061-9/+18
| | | | | | | | | | | | | | | | | | | | | | The current implementation for DSDT tables is not correct for the case where there is generated code, as the length ends up being incorrect. Also, we want the generated code to go first in the table. Rewrite this piece to correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: acpi: Allow the SSDT to be emptySimon Glass2020-11-061-7/+15
| | | | | | | | | | | | | | | | If there is nothing in the SSDT we should not include it in the tables. Update the implementation to check this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * acpi: Correct reset handling in acpi_device_add_power_res()Simon Glass2020-11-061-1/+1
| | | | | | | | | | | | | | | | If there is no reset line, this still emits ACPI code for the reset GPIO. Fix it by updating the check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: sound: Correct error handlingSimon Glass2020-11-062-3/+3
| | | | | | | | | | | | | | | | A few functions have changed to return pin numbers or I2C addresses. The error checking for some of the callers is therefore wrong. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Show the interrupt pointer with 'irqinfo'Simon Glass2020-11-063-7/+27
| | | | | | | | | | | | | | | | It is useful for this command to show the address of the interrupt table. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: nhlt: Fix a few bugs in the table generationSimon Glass2020-11-061-1/+3
| | | | | | | | | | | | | | | | At present these tables do not have the correct header, and there is an occasional incorrect value due to uninited data. Fix these bugs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: nhlt: Correct output of bytes and 16-bit dataSimon Glass2020-11-061-3/+10
| | | | | | | | | | | | | | | | At present these functions are incorrect. Fix them and add some logging and checking to avoid future problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow putting some tables in the bloblistSimon Glass2020-11-065-5/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present all tables are placed starting at address f0000 in memory, and can be up to 64KB in size. If the tables are very large, this may not provide enough space. Also if the tables point to other tables (such as console log or a ramoops area) then we must allocate other memory anyway. The bloblist is a nice place to put these tables since it is contiguous, which makes it easy to reserve this memory for linux using the 820 tables. Add an option to put some of the tables in the bloblist. For SMBIOS and ACPI, create suitable pointers from the f0000 region to the new location of the tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/project/uboot/patch/ 20201105062407.1.I8091ad931cbbb5e3b6f6ababdf3f8d5db0d17bb9@changeid/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Use if instead of #ifdef in write_tables()Simon Glass2020-11-051-19/+19
| | | | | | | | | | | | | | Use if() to remove the extra build path in this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add SMBIOS info for CoralSimon Glass2020-11-051-0/+8
| | | | | | | | | | | | | | | | This is required by Chrome OS so that the audio and other unibuild features work correctly. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coral: Drop the duplicate PCIe settingsSimon Glass2020-11-051-2/+0
| | | | | | | | | | | | | | | | | | These settings are included twice. The second lot are correct, so drop the others. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Don't bother clearing global NVSSimon Glass2020-11-051-1/+0
| | | | | | | | | | | | | | | | The bloblist guarantees that blobs are zeroed so there is no need to do an additional memset(). Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: acpi: Store the ACPI context in global_dataSimon Glass2020-11-052-1/+19
| | | | | | | | | | | | | | | | | | | | | | At present we create the ACPI context but then drop it after generation of tables is complete. This is annoying because we have to then search for tables later. To fix this, allocate the context and store it in global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow writing tables to failSimon Glass2020-11-053-3/+15
| | | | | | | | | | | | | | | | At present write_tables() can fail but does not report this problem to its caller. Fix this by changing the return type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add support for private filesSimon Glass2020-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | Some boards need to include binary data into the image for use during the boot process. Add a node for these. An example is the audio-codec configuration used by some audio drivers on Intel platforms. If no private files are provided, they will be omitted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add a layout for Chrome OS verified bootSimon Glass2020-11-051-0/+38
| | | | | | | | | | | | | | Add definitions for part of the vboot context used with verified boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add core init for the SoCSimon Glass2020-11-057-21/+170
| | | | | | | | | | | | | | | | Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * Add an assembly guard around linux/bitops.hSimon Glass2020-11-051-2/+2
| | | | | | | | | | | | | | | | This file can be included by any header but it includes C code. Guard it to avoid errors when compiling ASL, etc. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * coreboot: make use of smbios parserChristian Gmeiner2020-11-052-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If u-boot gets used as coreboot payload it might be nice to get vendor, model and bios version from smbios. I am not sure about the output of all the read information. With qemu target for coreboot this could look this: CBFS: Found @ offset 14f40 size 3b188 Checking segment from ROM address 0xffc15178 Checking segment from ROM address 0xffc15194 Loading segment from ROM address 0xffc15178 code (compression=1) New segment dstaddr 0x01110000 memsize 0x889ef srcaddr 0xffc151b0 filesize 0x3b150 Loading Segment: addr: 0x01110000 memsz: 0x00000000000889ef filesz: 0x000000000003b150 using LZMA Loading segment from ROM address 0xffc15194 Entry Point 0x01110000 BS: BS_PAYLOAD_LOAD run times (exec / console): 77 / 1 ms Jumping to boot code at 0x01110000(0x07fa7000) U-Boot 2020.10-00536-g5dcf7cc590-dirty (Oct 07 2020 - 14:21:51 +0200) CPU: x86_64, vendor AMD, device 663h DRAM: 127.1 MiB MMC: Video: No video mode configured in coreboot! Video: No video mode configured in coreboot! Vendor: QEMU Model: Standard PC (i440FX + PIIX, 1996) Bios Version: 4.12-3152-g326a499f6f-dirty Net: e1000: 52:54:00:12:34:56 eth0: e1000#0 No working controllers found Finalizing coreboot Hit any key to stop autoboot: 0 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * smbios: add parsing APIChristian Gmeiner2020-11-054-0/+129
| | | | | | | | | | | | | | | | Add a very simple API to be able to access SMBIOS strings like vendor, model and bios version. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Fix up driver names to avoid dtoc warningsSimon Glass2020-11-0514-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | At present there are a lot of dtoc warnings reported when building chromebook_coral, of the form: WARNING: the driver intel_apl_lpc was not found in the driver list Correct these by using driver names that matches their compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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